ISCAS 2000 - IEEE International Symposium on Circuits and Systems, May 28-31, 2000, Geneva, Switzerland

A New Chaotic Key-Based Design for Image Encryption and Decryption

Jui-Cheng Yen and Jim-In Guo
Department of Electronics Engineering National Lien-Ho Institute of Technology Miaoli, Taiwan, Republic of China Phone: 886-37-323406 Ext. 33 Fax: 886-37-323406 Ext. 22 E-mail: jcycnO,mail.lctc.cdu.tw

Abstract - In this paper, an image encryptioddecryption

algorithm and its VLSI architecture are proposed. According to a chaotic binary sequence, the gray level of each pixel is XORed or XNORed bit-by-bit to one of the two predetermined keys. Its features are as follows: 1 ) low computational complexity, 2) high security, and 3) no distortion. In order to implement the algorithm, its VLSI architecture with low hardware cost, high computing speed, and high hardware utilization efficiency is also designed. Moreover, the architecture of integrating the scheme with MPEG2 is proposed. Finally, simulation results are included to demonstrate its effectiveness.

11. THE ENCRYPTION/DECRYPTION ALGORITHM Let f denote an image of size MxN pixels andfix, y ) , 0 I x 5 M-1, 0 5 y S N-1, be the gray level off at position (x, y ) .

I. INTRODUCTION Recently, owing to advances in communication technology, there has been strong interest in digital signal transmission, for instance, in the ISDN networks, the HDTV systems, and the distributed multimedia systems. Because there has been fully developed in communication transmission and receiving equipment, illegal data access has become more easy and prevalent in wireless and general communication networks. Hence, data security has become a critical and imperative issue. In order to protect valuable data from undesirable readers, many encryption techniques [I]-[6] have been proposed. The basic ideas can be classified into three major types: value transformation [ l , 21, position permutation [3, 41, and their combining form [5, 61. The value transformation algorithms transform the original data value. On the other hand, the position permutation algorithms scramble the positions of original data. The combining form performs both position permutation and value transformation. In this paper, we propose a new image encryption/ decryption algorithm belonging to the category of value transformation. According to a binary sequence generated from a chaotic system, the gray level of each pixel is XORed or XNORed bit-by-bit to one of the two predetermined keys. The desirable result of the encrypted image being completely disordered can be obtained. Moreover, its VLSI architecture is designed and the architecture of integrating the encryption scheme with MPEG2 is also proposed. Finally, simulation results are given.

The proposed encryption scheme is as follows. The Chaotic Key-Based Algorithm (CKBA) Step I: Determine the two keys, keyl and key2, and the 4 and N, and set 1 = 0. two parameters, A Step 2: Determine a 1-D chaotic system and its initial point x(0). Generate the chaotic sequence x(O), x( l ) ,x(2),. .. , x(MNI8-1) from the chaotic system and then create b(O), b ( l ) , b(2),..., b(2MN-1) fromx(O), x ( l ) , x(2),...,x(MNI8-1) by the generating scheme that O.b( 16n+O)b(16n+l) b(16n+I 3)b(16n+14)b(16n+l5) is the binary representation ofx(n) for n = 0, 1, 2,...., (MN/8-1) Step 3: Forx = 0 to M - 1 For y = 0 to N - 1 Switch ( 2xb(l) + b(Z+l) ) case 3: f ( x ,y ) =Ax, y ) XOR keyl case 2: f(x,y)=f(x,y)XNORkeyl case 1 : f ( x , y ) = f l x , y ) X O R k e y 2 case 0: f ( x ,y ) =fix, y ) XNOR key2 l=1+2; End End Step 4: The resultf is obtained and stop the algorithm. The block diagram of CKBA is shown in Fig. 1. From Fig. 1 , pixels are XORed or XNORed bit-by-bit to keyl or key2 according to the two bits in the sequence. By the transformation on each pixel, the desirable result of the encrypted image being completely disorder can be obtained. Many combinations of keyl and key2 can result in very disorderly image. The basic criterion to select keyl and key2 is based on the idea of CKBA that the gray level of each pixel is XORed or XNORed bit-by-bit to keyl or key2. Let

keyl

= x I = o a ix

2 and key2 = c 7 di x 2
1=O

The basic

criterion to select keyl and key2 is

i ( a i Bdi)=4.
i=O

In CKBA, the overall computational complexity is

0-7803-5482-6/99/$I0.00 02000 IEEE

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dominated by Step 3. The operation numbers for SwitchCase statement, multiplication with 2, addition, and XOR or XNOR operation are MxNx1, M x N x ~ MXNXS, , and MXNx1, respectively. It is obvious that the computational complexity is low. Besides, the security problem is analyzed. Proposition I : Assume the procedure of CKBA is known except the chaotic binary sequence. The number of possible encryption results is 22xMxN . Proof Since the total required bits in Step 3 are 2xMXN, . the number of possible results is 22xMxN For example, consider the case of M = 256 and N = 256. Since The number of all the possibilities is 231072 the chaotic binary sequence is unpredictable, it is very difficult to decrypt an encrypted image correctly even by making an exhaustive search. Hence, CKBA is one of guaranteed high security. Let CKBAE,,,,,,(f(x, y ) ) denote the encryption result of Ax, y ) by CKBA with the argument value, value E (0,1, 2, 3) and CKBAD,,o,,,eCf(x,y ) ) denote the decryption result off(x, y ) by CKBA. The distortion problem is discussed. Lemma I : CKBAD,,,,(CKBAE,,,,,(Rx,y))) =Ax, y). Proof: Since (fix, y j XOR keyl ) XOR keyl =fix, y), (fix, y)XNOR keyl )XNORkeyl =f(x,y),(f(x,y)XOR key2 j XOR key2 =f(x,y),and(f(x,y)XNORkey2 )XNORkey2 = fix, y ) , the relation CKBAD,,,,(CKBAE,,,,(f(x, y ) ) ) =fix, y ) holds because it is just one of the four relations. Proposition 2: CKBA is an algorithm of no distortion. Proof: It is straightforward according to Lemma 1. In summary, the CKBA is an algorithm of low computational complexity, high security, and no distortion.
111. THE HARDWARE ARCHITECTURE How can we efficiently realize CKBA with simple hardware and high hardware utilization efficiency is our main concern in the architecture design. In Fig. 1, the pixel-based operation is used to simplify the data access from the image frame buffers. Moreover, both the data encryption unit (DEU) and the data decryption unit (DDU) are using the same hardware architecture. Fig. 2 shows the hardware architecture of the DEU and DDU. We adopt the concept of parallel processing such that the data encryption and decryption of eight pixels can be performed at a time with the bit-serial, pixel-parallel (BSPP) style of implementation. This architecture consists of 16 shift registers, 8 parallel-to-serial (P/S) converters, 8 serial-toparallel (S/P) converters and 8 processing elements (PEs). By adopting the BSPP style of implementation, the critical path will be located in the DEU and DDU, since that generating one chaotic bit string value can be used to encrypt and decrypt eight data pixels. Therefore, we can both shorten the critical path and achieve the high hardware utilization efficiency of the proposed design by exploiting the BSPP style of implementation. Fig. 3 shows the architecture of the processing elements (PEs) in the DEU or DDU. It consists of two data

multiplexers, one XOR gate, and one inverter gate. Fig. 4 shows the architecture of the chaotic binary sequence generator (CBSG). It is composed of two multipliers, one subtractor, one DFF, and one data multiplexer. The computation time (denoted as T,,,, ) to generate a chaotic bit string value is assumed to be the time for two multiplications and one data multiplexing. While, the cycle ) time for the computation in DEU or DDU (denoted as TDEu is assumed to be the time for one P/S operation, one XNOR operation, two data multiplexing operations, and one S/P operation. Since that generating one chaotic bit string value can be used to encrypt and decrypteight data pixels, the critical path would be T,,, if T,,,, is smaller than 8 x TCIEU. However, if T,,, is larger than 8 x TDEU, we can adopt suitable pipeline techniques to further reduce the time T,.,, such that the critical path can be reduced to the time T,,,. To summarize, the proposed hardware architecture is one of low hardware cost, high computing speed, and high hardware utilization efficiency
IV. ARCHITECTURES OF SYSTEM INTEGRATION Based on CKBA, the MPEG2/CKBA system is shown in Fig. 5. In the integration, the x and y components of each motion vector in the motion estimation of MPEG2 are encrypted by CKBA. In this way, these two parts are perfectly integrated into a new system and it is easy to be simulated. However, the bitrate is increased. If the compressed and encrypted image can not be decrypted by the correct procedure, either error will occur in the compensation procedure because the new MPEG2/CKBA system may result in undefined motion vectors in the border
blocks or there will be severe blocking artifacts in the

reconstructed image. It will be demonstrated in the experiment. The novelty of the system is threefold. 1) The encryption mechanism will not destroy the original MP13G2 architecture. 2) No processing bottleneck results. 3) The cost ratio of the CKBA to the whole system will be very low.
V. SIMULATION RESULTS The sequence Claire in CIF format of size 352x288 is used and its 42 frame is shown in Figs. 6(a). To perform motion estimation, four settings are made. 1) The frames are partitioned into blocks of size 16x16. 2) The maximum block displacement is set to I5 pixels. 3) The exhaustive search is performed. 4) The adopted dissimilarity measure between two blocks is the sum of the absolute differences of respective gray levels. After performing motion estimation on the 43-th and 44-th frames successively, the motion-compensated (MC) frames are shown in Fig. 6(bj and 6(d). Moreover, the errors between MC frames and current transmitted frames (CTFs) are measured by the sum of the absolute differences of respective gray levels and listed in Table I. To integrate CKBA with the block matching scheme, the x and y components of each motion vector (MV) are

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REFERENCES
[ 11 P. Refregier and B. Javidi, Optical-Image Encryption

[2]

[3]

[4]

[5]

[6]

Based on Input Plane and Fourier Plane Random Encoding, Optics Letters, vol. 20, pp. 767-769, 1995. H. M. Heys and S. E. Tavares, On the Security of the CAST Encryption Algorithm, Proceedings of Canadian Conference on Electrical and Computer Engineering, Halifax, N.S. Canada, pp. 332-335, 1994. N. Bourbakis and C. Alexopoulos, Picture Data Encryption Using SCAN Pattern, Pattern Recognition, vol. 25, no. 6, pp. 567-581, 1992. J. Fridrich, Image Encryption Based on Chaotic Maps, IEEE International Conference on Systems, Man, and Cybernetics, Computaional Cybernetics and Simulations, pp. 1105-1110, 1997. C. J. Kuo and M. S. Chen, A New Signal Encryption Technique and Its Attack Study, IEEE International Conference on Security Technology, Taipei, Taiwan, pp. 149-153, 1991. [6] S. Sridharan, E. Dawson and B. Goldburg, Fast Fourier-Transform Based Speech Encryption System, IEE Proceedings-I Communications Speech and Vision, vol. 138, no. 3,pp. 215:223, 1991.

Original m g e f

Chaotic Binary Sequence Generator

Error Correct Incorrect Correct Incorrect (Id) (1) (2nd) (2nd) Claire 65184 2494824 85286 2672701
Decrypted nmagef

XOR or XNOR
to

key1 or key2

Fig. 1. The block diagram of CKBA VI. CONCLUSION In this paper, the novel chaotic key-based algorithm for image encryptioddecryption has been proposed and its VLSI architecture has been designed. The novel algorithm possesses the following features: 1) low computational complexity, 2) high security, and 3) no distortion. The presented VLSI architecture possesses the following advantages: 1) high hardware utilization efficiency, 2) low hardware cost, and 3) high computing speed. In addition, the novelty of the MPEG2/CKBA system is threefold. 1) The encryption mechanism will not destroy the original architecture. 2) No processing bottleneck results from the integration. 3) The cost ratio of the encryption part to the whole system is very low. Moreover, the simulation results have indicated the following facts. 1) If the errors are not avoided in the compensation procedure intentionally, all frames can not be constructed. 2) Severe blocking artifacts exist in the MC frames and make them unrecognizable, if decryption is not performed.

Fig. 2. The hardware architecture of DEU and DDU.

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Fig. 3. The architecture of PE in the DEU or DDU.

x(0)

CB[Is..o]

LJ

Fig. 4.The architecture of CBSG.

1
Q Quantizer FY : ~ r a m e memory vectnr M E : Motion eStimstion MC : Motion compensation VLC : Vmiablc lenyh coder DCT Discrete cosine rranrform

...............................................

(Mouan

:I I

+:
Conlid si@

path

+:

Dala path

Fig. 5. The block diagram of the MPEG2K-A

system.

Fig. 6. (a) The 42"d frame of "Claire". The reconstructed MC frames (b) under correct decryption on MVs in the first compensation, (c) without performing decryption on MVs in the first compensation, (d) under correct decryption on MVs in the second compensation, and (e) without performing decryption on M v s in the second compensation.

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