ADF4602
ADF4602
ADF4602
FEATURES
Single-chip, multiband 3G transceiver 3GPP 25.104 release 9 WCDMA/HSPA compatible UMTS band coverage Local area Class BS in Band I to Band VI and Band VIII to Band X Direct conversion transmitter and receiver Minimal external components Integrated, multiband, multimode monitoring No Tx SAW or Rx interstage SAW filters Integrated power management (3.1 V to 3.6 V supply) Integrated synthesizers, including PLL loop filters Integrated PA bias control DACs/GPOs WCDMA and GSM receive baseband filter options Easy-to-use with minimal calibration Automatic Rx DC offset control Simple gain, frequency, mode programming Low supply current 50 mA typical Rx current 50 mA to 100 mA Tx current (varies with output power) 6 mm 6 mm 40-pin LFCSP package
DAC1
DAC2
GPO 1 TO 4
ADF4602
Tx_PWR_CONTROL TXBBIB TXBBI
TXLBRF Tx_PWR_ CONTROL TXHBRF Tx_PWR_ CONTROL LO GENERATOR Tx PLL LOOP FILTER FRAC N SYNTHESIZER
VSUP7
VSUP6
Rx_LO_LB SELECTABLE BANDWIDTH BASEBAND FILTERS RXHB1RF I CHANNEL RXBBI RXBBIB DC OFFSET CORRECTION RXBBQ Q CHANNEL Rx_LO_LB REFIN 26MHz 19.2MHz SERIAL INTERFACE VDD LDO1 LDO2 LDO3 LDO4 LDO5 VSUP8 RXBBQB DC OFFSET CORRECTION
APPLICATIONS
3G home base stations (femtocells)
RXHB2RF
RXLBRF
VINT REFCLK
VSUP1
VSUP2
VSUP3
VSUP4
VSUP5
CHIPCLK
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 20092011 Analog Devices, Inc. All rights reserved.
07092-001
REVISION HISTORY
2/11Rev. 0 to Rev. A Changes to Features and Applications........................................... 1 Changes to Table 1............................................................................ 4 Changes to Table 3............................................................................ 9 Changes to Figure 4........................................................................ 10 Changes to Figure 13...................................................................... 13 Changes to Figure 21 and Figure 22............................................. 14 Changes to Figure 26 and Figure 27............................................. 15 Changes to Figure 31 through Figure 33 ..................................... 16 Changes to Figure 44...................................................................... 21 Changes to DC Offset Compensation Section ........................... 23 Changes to Figure 51...................................................................... 26 Changes to Table 13........................................................................ 30 Replaced Applications Information Section ............................... 33 Changes to Figure 53...................................................................... 34 10/09Revision 0: Initial Version
Rev. A | Page 2 of 36
Rev. A | Page 3 of 36
ADF4602 SPECIFICATIONS
VDD = 3.1 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3.3 V and TA = 25C, 26 MHz reference input level = 0.7 V p-p. Table 1.
Parameter REFERENCE SECTION Reference Input Reference Input Frequency Reference Input Amplitude Reference Input Jitter REFCLK Output (26 MHz) Output Load Capacitance Output Swing Output Slew Rate Output Duty Cycle Variation Output Jitter CHIPCLK Output (19.2 MHz) Output Load Capacitance Frequency Multiplication Ratio Output Swing Output Duty Cycle Variation Output Jitter Lock Time TRANSMIT SECTION I/Q Input Input Resistance Input Capacitance Differential Peak Input Voltage Input Common-Mode Voltage Baseband Filter 3 dB Bandwidth TX Gain Control Maximum Gain Gain Control Range Gain Control Resolution Gain Control Accuracy Gain Settling Time RF Specifications (High Band) Carrier Frequency Output Impedance Output Power (POUT) Output Noise Spectral Density Min Typ Max Unit Test Conditions
0.1
2.0
40
48/65 1.5 2 33 50
40 48/65
1.05
550 1.4
k pF mV pd V MHz dB dB dB dB dB s
Single-ended Single-ended
1 V p-p differential baseband input Average of LSB steps Any 1 dB step Any 10 dB step POUT within 0.1 dB of final value
2170
TM1 signal 64 DPCH 40 MHz offset 80 MHz offset 95 MHz offset 190 MHz offset POUT = 8 dBm POUT = 8 dBm 5 MHz, POUT = 8 dBm 10 MHz, POUT = 8 dBm
Rev. A | Page 4 of 36
ADF4602
Parameter RF Specifications (Low Band) Carrier Frequency Output Impedance Output Power (POUT) Output Noise Spectral Density Carrier Leakage FDD EVM FDD ACLR RECEIVE SECTION Baseband I/Q Output Output Common Mode Voltage Differential Output Range Output DC Offset Quadrature Gain Error Quadrature Phase Error In-Band Gain Ripple Low-Pass Filter Rejection (Check) WCDMA (Seventh Order) Min 824 50 6 158 35 5 55 70 Typ Max 960 Unit MHz dBm dBc/Hz dBc % dB dB Test Conditions
TM1 signal 64 DPCH 45 MHz offset POUT = 6 dBm POUT = 6 dBm 5 MHz, POUT = 6 dBm 10 MHz, POUT = 6 dBm
1.15 1.35
1.35 1.55
0.7
V V V p-p d mV dB rms dB dB dB dB dB dB dB dB dB dB dB dB ns ns dB dB dB dB dB
Mode 1 Mode 2
GSM
@2.7 MHz @3.5 MHz @5.9 MHz @10 MHz @2.7 MHz @3.5 MHz @5.9 MHz @10 MHz @200 kHz @400 kHz @800 kHz 1.92 MHz band 100 kHz band WCDMA mode
Differential Group Delay WCDMA GSM Receiver Gain Control Maximum Voltage Gain Gain Control Range Gain Control Resolution Gain Control Step Error RF Specifications (High Band) Input Frequency Input Impedance Input Return Loss Noise Figure Maximum Input Power 3 Input IP3 Input IP2 EVM RF Specifications (Low Band)
1 dB step 10 dB step
1710 50 20 4.0
2170
20 2 7 0 53 65 8
TX power of 8 dBm, spur-free measurement 2 Maximum LNA gain Minimum LNA gain 10 MHz and 20 MHz Offset, 59 dB gain 85 MHz and 190 MHz Offset, 59 dB gain 80 MHz offset 190 MHz offset 60 dBm input
Rev. A | Page 5 of 36
ADF4602
Parameter Input Frequency Input Impedance Input Return Loss Noise Figure Maximum Input Power3 Input IP3 Input IP2 EVM Synthesizer Section Channel Resolution Lock Time3 DAC/GPO CONTROL DAC1 Resolution Output Range Absolute Accuracy Output LSB Step Output Capacitive Load Output Current Output Impedance DAC2 Resolution Output Range DNL INL Output Capacitive Load Output Current Output Impedance GPO1 to GPO4 Output Current Output High Voltage Output Low Voltage Switching Time LOGIC INPUTS Input High Voltage, VINH Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN LOGIC OUTPUTS (SDATA) Output High Voltage, VOH Output Low Voltage, VOL CLKOUT Rise/Fall CLKOUT Load TEMPERATURE RANGE (TA) Min 824 Typ 50 20 4.0 20 2 2 5 40 7 50 200 Max 960 Unit MHz dB dB dBm dBm dBm dBm dBm % kHz s Test Conditions
80 dB gain, TX power of 8 dBm Maximum LNA gain Minimum LNA gain 10 MHz and 20 MHz offset, 59 dB gain 45 MHz and 90 MHz offset, 59 dB gain 45 MHz offset 60 dBm input
5 2.3 50 25 10 1 6 0 0.5 1.0 5 5 2 10 2.6 0.2 1 1.2 1.2 2.1 3.3 0.6 1 10 1 +5 2.85 1 +10 3.15
No load No load
GPO1, GPO2, GPO3 GPO4 Maximum output current Maximum output current 5 pF load 1.8 V readback mode 4 2.8 V readback mode4
VX 0.45 0.45 5 10 85
Rev. A | Page 6 of 36
ADF4602
Parameter POWER SUPPLIES Voltage Supply VDD VSUP1 VSUP2 Min Typ Max Unit Test Conditions
3.1
3.6
V V V
V V V
VSUP6 VSUP7 VSUP8 VINT CURRENT CONSUMPTION Transmit Current Consumption 8 dBm Output Level 28 dBm Output Level Receive Current Consumption
1 2
V V V V
Main supply input Output from internal LDO1, 10 mA rating, supply for RX VCO Output from Internal LDO2, 30 mA rating, supply for RX baseband and RX downconverter Output from internal LDO3, 10 mA rating, supply for RX LNAs Output from internal LDO4, 10 mA rating, supply for TX VCO Output from internal LDO5, 100 mA rating, supply for TX modulator, TX baseband, PA control DACs Supply input for RX synthesizer, connect to VSUP3 Supply input for TX synthesizer, connect to VSUP3 Supply input for reference section, connect to VSUP2 Supply input for serial interface control logic VDD = 3.6 V, output is matched into 50 FRF = 2170 MHz FRF = 2170 MHz
100 50 50
mA mA mA
The reference frequency should be dc coupled to the REFIN pin. It is ac-coupled internally. The noise figure measurement does not include spurious noise due to harmonics of the 26 MHz reference frequency. Spurs appear at integer multiples of the reference frequency (every 26 MHz), degrading the receive sensitivity by about 6 dB. 3 Guaranteed by design, not production tested. 4 Bit sif_vsup8 in Register 2 controls whether 1.8 V readback mode or 2.8 V readback mode is selected. See the Serial Port Interface (SPI) section for more details.
Rev. A | Page 7 of 36
WRITE SCLK
t5
t6
t3
SDATA W[25]
t4
W[1] W[0]
W[24]
SEN
t1
READ REQUEST
READ
SCLK
t9
SDATA Q[25] Q[24] Q[1] Q[0] R[25] R[24] R[1] R[0]
07092-002
t2
t7
t10
SEN
t8
3 orMORE more 3 OR SYSCLK periods SCLK PERIODS
ADF4602 selected device DRIVES SDATA drives RSDATA
Rev. A | Page 8 of 36
07092-003
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly.
ESD CAUTION
Rev. A | Page 9 of 36
PIN 1 INDICATOR
ADF4602
TOP VIEW (Not to Scale)
30 29 28 27 26 25 24 23 22 21
DAC1 DAC2 VSUP5 TXRFGND TXHBRF TXRFGND TXLBRF TXBBQB TXBBQ VSUP4
NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PADDLE MUST BE CONNECTED TO GROUND FOR CORRECT CHIP OPERATION. IT PROVIDES BOTH A THERMAL AND ELECTRICAL CONNECTION TO THE PCB.
11 12 13 14 15 16 17 18 19 20
07092-004
ADF4602
Pin No. 31 32 33 34 35 36 37 38 39 40 Mnemonic VDD GPO4 CHIPCLK VSUP81 REFCLK REFIN NC VSUP61 GPO1 GPO2 EPAD Function Main Supply Input. Digital Output. This is used for switch or PA control. Chip Clock Output. Reference Clock Supply Input. Connect to VSUP2, and decouple to ground with 100 nF. Reference Clock Output. Reference Clock Input. The reference is ac-coupled internally. No Connect. Do not connect to this pin. Receive Synthesizer Supply Input. Connect to VSUP3 and decouple to ground with 100 nF. Digital Output. This is used for switch or PA control. Digital Output. This is used for switch or PA control. Exposed Paddle Under Chip. This must be connected to ground for correct chip operation. It provides both a thermal and electrical connection to the PCB.
Y5V capacitors are not recommended for use with these pins. X7R, X5R, C0G or a similar type of capacitor should be used.
Rev. A | Page 11 of 36
20 18 16
COMPOSITE EVM (%)
07092-006
14 12 10 8 6 4 2
30 25 20 15 10 5 0 5
07092-107
GLOBAL RESULTS FOR FRAME Total Power Chip Rate Error IQ Offset Composite EVM CPICH Slot No CHANNEL RESULTS Symbol Rate Channel Code No of Pilot Bits Channel Power Rel Symbol EVM
1 CLRWR
3DB
0 35
txpwr_set (dBm)
Figure 8. TXHBRF, UMTS Band II. Transmit EVM vs. txpwr_set (dBm), Four Calibration Points Applied, Transmit Frequency 1960 MHz.
20 18 16
COMPOSITE EVM (%)
14 12 10 8 6 4 2 30 25 20 15 10 5 0 5
07092-108
07092-005
GLOBAL RESULTS Total PWR Chip Rate Err IQ Offset Composite EVM CPICH Slot Number CHANNEL RESULTS Symb Rate Channel Code Modulation Type Chan Pow rel. Symbol EVM
RESULT SUMMARY Carr Freq Err dBm -92.42 Hz Trg to Frame ppm 22.62 s IQ Imbalance % 0.36 % % rms Pk Code Dom Err -49.96 dB rms ( 15 ksps) Timing Offset ksps 0 Chips Chan Slot Number 0 No. of Pilot Bits 0 Chan Pow abs. dB -14.60 dBm % rms Symbol EVM 1.21 % Pk
B LN
0 35
txpwr_set (dBm)
Figure 9. TXLBRF,UMTS Band V, Transmit EVM vs. tpwr_set (dBm), Four Calibration Points Applied, Transmit Frequency 881 MHz.
30
14 12 10 8 6 4 2
1 4 6 8 10
2 5 7 9 3
35 40 45
ACLR (dB)
07092-007
50 55 60 65
07092-008
0 35
30
25
20 15 10 txpwr_set (dBm)
70 14
12
Figure 7. TXHBRF, UMTS Band I. Transmit EVM vs. txpwr_set (dBm), Measured Across 10 DUTS, Four Calibration Points Applied, Transmit Frequency 2140 MHz
Figure 10. TXHBRF Transmit ACLR vs. Output Power, Test Model 1 Signal, 10.54 dB PAR, 2170 MHz
Rev. A | Page 12 of 36
ADF4602
30 35 40 45 +5MHz 5MHz +10MHz 10MHz
*RBW 30kHz MARKER 1 (T1) *VBW 300kHz 23.01dBm REF 10.9dBm *ATT 5dB *SWT 100ms 880.877403846MHz 4.39dBm CH PWR POS 10.895dBm ACP LOW 60.63dBm 20 58.52dBm ACP UP ALT1 LOW 72.07dBm 30 72.13dBm ALT1 UP 40 50 60
ACLR (dB)
50 55 60 65
07092-009
70 80 90 100
20 15 10 5 OUTPUT POWER (dBm/3.84MHz) 0
07092-011
70 25
110
CENTER 881MHz
2.55MHz/DIV
SPAN 25.5MHz
Figure 11. TXLBRF Transmit ACLR vs. Output Power, Test Model 1 Signal, 10.54 dB PAR, 881 MHz
*RBW 30kHz *VBW 300kHz *SWT 100ms CH PWR ACP LOW ACP UP ALT1 LOW ALT1 UP
51
*ATT 0dB
POS 12.698dBm
53 55
57 59 61 63 65 2110
2120
2160
2170
Figure 15. Transmit ACLR vs. Frequency and Temperature (UMTS Band I), Transmit Output Power = 8 dBm
20 30 40 50 60 70 80 90
51 53 55 0C 5MHz HIGH 25C 5MHZ HIGH 85C 5MHz HIGH 0C 5MHz LOW 25C 5MHz LOW 85C 5MHz LOW
57 59 61 63
100
07092-110
CENTER 1.96GHz
2.6MHz/
SPAN 26MHz
1940
1980
1990
Figure 16. Transmit ACLR vs. Frequency and Temperature (UMTS Band II), Transmit Output Power = 8 dBm
Rev. A | Page 13 of 36
07092-013
110
65 1930
07092-012
ADF4602
54 0C 5MHz HIGH 25C 5MHZ HIGH 85C 5MHz HIGH 0C 5MHz LOW 25C 5MHz LOW 85C 5MHz LOW 0.14 0.12
56
58
60
62
64
870
890
895
Figure 17. Transmit ACLR vs. Frequency and Temperature (UMTS Band V), Transmit Output Power = 7 dBm
Figure 20. Current Consumption vs. Transmit Output Power; Frequency = 2170 MHz, VDD = 3.3 V, Test Model 5 Signal, Receiver Disabled
0
5 0 5
MAGNITUDE (dBm)
20
15 20 25 30 35
07092-015
MAGNITUDE (dB)
10
40
60
80
100
10 FREQUENCY (MHz)
100
1 FREQUENCY (MHz)
10
70 80 90
PHASE NOISE (dBc/Hz)
10 0 10 20
MAGNITUDE (dBm)
170 1k
10k
10M
100M
100 10
Rev. A | Page 14 of 36
07092-118
40 0.1
120 0.1
07092-017
66 865
ADF4602
40
16 14 12 10 MIXSTEP = 10 LNASTEP = 6 GAINCAL = 8 NOISE FIGURE (dB)
35 30 25 20 15 10
EVM (%)
8 6 4
5
2
07092-020
0 20
45
50
55
60
65
70
75
80
85
90
30
80
90
GAIN (dB)
Figure 23. Receive EVM vs. Gain; 2.84 MHz QPSK Modulated Input Signal, WCDMA Receive Baseband Filter
2.0 1.8 1.6 1.4 MIXSTEP = 10 LNASTEP = 6 GAINCAL = 8
Figure 26. RXHB2RF, Receiver Noise Figure vs. Gain, UMTS Band II, Rx Frequency = 1880 MHz
40 35 30 MIXSTEP = 10 LNASTEP = 6 GAINCAL = 8
25 20 15 10 5 0 45
1.2 1.0 0.8 0.6 0.4 0.2 30 40 50 60 70 80 RECEIVE GAIN SETTING (dB) 90 100
07092-021
0 20
50
55
60
65
70
75
80
85
90
GAIN (dB)
Figure 24. Receive Gain Step Error vs. Gain Setting, 1 dB Steps, Measurement was taken by injecting known signal level and measuring the gain through the device. The gain was then stepped through all settings in 1 dB steps, and the gain step change measured in each case.
Figure 27. RXLBRF, Receiver Noise Figure vs. Gain, UMTS Band V, Rx Frequency = 836 MHz
40 35 30
25 20 15 10 5 0 45
14 12 10 8 6 4 2
50
55
60
65
70
75
80
85
90
07092-122
1930
RX GAIN (dB)
1970
1980
Figure 25. RXHB1RF, Receiver Noise Figure vs. Gain, UMTS Band I, Rx Frequency = 1955 MHz
Rev. A | Page 15 of 36
07092-023
0 1920
07092-124
07092-123
ADF4602
100
16 GAIN = 80dB 14 12
NOISE FIGURE (dB)
102
25C 0C 85C
104
SENSITIVITY (dBm)
10 8 6 4 2
07092-024
0 1850
1870
1880
1890
1900
1910
1920
1860
1900
1910
RX FREQUENCY (MHz)
Figure 32. RXHB2RF Receive Sensitivity vs. Frequency. UMTS Band II.
100
102
25C 0C 85C
SENSITIVITY (dBm)
104 106 108 110 112 114 116 118 825 830 835 840 845 850 855
07092-128 07092-026
0 822
120 820
827
847
RX FREQUENCY (MHz)
4 6 8 10 12 14 16
1940
1950
1960
1970
1980
1990
07092-126
120 1910
18
10
20
RX FREQUENCY (MHz)
90
100
110
Figure 31. RXHB1RF Receive Sensitivity vs. Frequency, UMTS Band I (see the Receive Sensitivity section for more details)
Figure 34. RXHB1RF Receive IP3, 10 MHz + 19.8 MHz vs. Gain Setting
Rev. A | Page 16 of 36
07092-127
120 1840
ADF4602
8 6 4 25C 0C 85C 100 25C 0C 85C
90
2 0 2 4 6 8 10 12
07092-027
80
70
60
50
10
20
90
100
110
10
20
90
100
110
Figure 35. RXHB1RF Receive IP3, 85 MHz + 190 MHz vs. Gain Setting
110 105 100 95 25C 0C 85C 16 14 12 10 8 6 4 2 0 2 4 6 8 10
07092-028
25C 0C 85C
10
20
90
100
110
Figure 36. RXHB1RF Receive IP2, 190 MHz vs. Gain Setting
8 6 4 25C 0C 85C
Figure 39. RXLBRF Receive IP3, 10 MHz + 19.8 MHz vs. Gain Setting
16 14 12 25C 0C 85C
2 0 2 4 6 8 10 12
07092-029
10 8 6 4 2 0 2 4 6 8
10
20
90
100
110
10
20
90
100
110
Figure 37. RXHB2RF Receive IP3, 80 MHz + 40 MHz vs. Gain Setting
Figure 40. RXLBRF Receive IP3, 45 MHz + 22.5 MHz vs. Gain Setting
Rev. A | Page 17 of 36
07092-032
14
10
07092-031
12
07092-030
14
40
ADF4602
100 90 80 25C 0C 85C
70 60 50 40 30
10
20
90
100
110
07092-033
Rev. A | Page 18 of 36
TX OUTPUT
PA
TXBs
TXPWR_SET[11:0]
The ADF4602 contains a highly innovative low noise variable gain direct conversion transmitter architecture, that removes the need for external transmit SAW filters. The direct conversion architecture significantly reduces the risk of transmit harmonics across all bands due to the simplified nature of the frequency plan. See Figure 42 for a block diagram.
For ease of PCB routing between the ADF4602 and the transmit DAC, the I and Q differential inputs can be internally swapped. For user test purposes, the I and Q inputs can also be internally shorted together and a dc offset applied. This produces a large carrier at the RF output, which is useful for signal path integrity testing.
VOLTS I OR Q
I/Q Baseband
The baseband interface for the I and Q channels is a differential, dc-coupled input, supporting a wide range of input commonmode voltages (VCM). The allowable input common-mode range is 1.05 V to 1.4 V. The maximum signal swing allowed is 550 mV peak differential. This corresponds to a 1.1 V peak-topeak differential on either the I or Q channel. Figure 43 shows a graphical definition of peak differential voltage and VCM. The baseband input signals pass through a second order Butterworth filter prior to the quadrature modulator. The cutoff frequency is 4 MHz. This gives some rejection of the DAC images. The filter also helps to suppress any spurious signals that might be coupled to the baseband terminals on the PCB.
IB OR QB PEAK V DIF
07092-035
VCM TIME
Rev. A | Page 19 of 36
ADF4602
I/Q Modulator
The I/Q modulator converts the transmit baseband input signals to RF. Calibration techniques are used to maintain accurate IQ balance and phase across frequency and environmental conditions, thus ensuring that 3GPP carrier leakage and EVM and ACLR requirements are met with good margin under all conditions. The on-chip calibrations are carried out during the transmit PLL lock time specified and are self-contained, requiring no additional input from the user. The modulator has an 80 dB gain control range, programmable in 1/32 of a decibel step. The 12-bit word txpwr_set[11:0] in Register 28 controls the transmit output power. The setting is referenced to a full-scale (500 mV peak differential) sine wave signal applied to the transmit baseband inputs. To calculate the output power when a WCDMA modulated signal with a certain peak-to-average ratio is applied, Equation 1 should be used. Output Power (dBm/3.84 MHz) = txpwr(dBm) PAR(dB) (1) where txpwr(dBm) is the txpwr_set[11:0] value converted to dBm, and PAR is the peak-to-average ratio of the WCDMA signal. For example, if an output power of 8 dBm is required for a WCDMA signal with a peak-to-average ratio of 10 dB txpwr(dBm) = 8 dBm + 10 dB = +2 dBm The current consumption of the modulator scales with output power. When the TX power is backed off from maximum, the transceiver benefits from lower power dissipation. user because most power amplifiers (PAs) are singled-ended. This situation would normally require additional external matching components or a differential to single-ended SAW filter structure. With the ADF4602, the SAW filter is not necessary, and the required low loss balun is fully integrated, converting the differential internal signals to a single-ended 50 output, thus allowing easy interfacing to the PA. The high band output is available at the TXHBRF pin, and the low band output is available at the TXLBRF pin. These are directly connected to a 50 load, if necessary, and do not require ac-coupling.
DACS
The ADF4602 integrates two DACs that are designed to interface to an external PA to control reference or bias nodes within the PA. If this function is not required, the DACs are used for any general purpose or powered down if not required. DAC1 is a 5-bit voltage output DAC. The output range is from 2.3 V to 3.15 V (for VDD > 3.15 V). The DAC1 output stage is supplied directly from VDD, with the capability to supply 10 mA of current to within 50 mV of VDD. For high accuracy, the DAC reference is supplied from LDO5, which is internally trimmed to 25 mV accuracy. The DAC1 output is set by the PADAC1[4:0] word. DAC2 is a 6-bit voltage output DAC with a range from 0 V to 2.8 V. LDO5 supplies both the reference voltage and full-scale output voltage for DAC2. The output voltage is set by the padac2_ow[5:0] word. The dacgpo_owen bit must also be set high if control of DAC2 is required. Both DACS are powered down by writing the code, 0x0, to the respective control register.
VCO Output
The TX VCO output is fed to a tuned buffer stage and then to the quadrature generation circuitry. The tuned buffer ensures that minimum current and LO related noise is generated in the VCO transport. This action is transparent to the user. The quadrature generator creates the highly accurate phased signals required to drive the modulator and also acts as a divide-by-2. In low band, an additional divide-by-2 is used in the VCO transport path, which is bypassed in high band. This is done to minimize the VCO tuning range required to cover all the bands. The phase accuracy of the signals is important in ensuring good modulation quality and accurate output power. An on-chip calibration ensures that the phased signals are exactly 90 out of phase. This calibration runs each time the frequency is changed or if the txpwr_set[11:0] word is written to. If the temperature of the device changes, this calibration should be updated. To run the calibration, the user should simply write to the txpwr_set[11:0] word for each five degree change in temperature, or update the value regularly (every few seconds) between WCDMA frames or timeslots. This ensures that good EVM and accurate output power are maintained as the temperature of the device changes.
RECEIVER DESCRIPTION
The ADF4602 contains a fully integrated direct conversion receiver designed for multiband WCDMA femtocell applications. High performance, low power consumption, and minimal external components are the key features of the design. Figure 44 shows a block diagram of the receiver, which consists of three LNA blocks for multiband operation, high linearity I/Q mixers, advanced baseband channel filtering, and a DC offset compensation circuit.
TX Output Baluns
The baseband input, modulator, and all associated circuitry are fully differential to maintain high signal integrity and noise immunity. However, a differential output is not optimal for the
Rev. A | Page 20 of 36
ADF4602
LNA 0dB TO 18dB 3 6dB STEPS RxEN[1:0] MIXER TRANSCONDUCTANCE 18dB TO 30dB (WCDMA) 27dB TO 39dB (CDMA) 2 6dB STEPS ACTIVE FILTER CHANGES 0dB TO 18dB 0dB TO 18dB 3 6dB STEPS 3 6dB STEPS VGA 6dB TO +18dB 24 1dB STEPS
RXBBI RXHB2RF BPF HIGH BAND LNA 2 RXHB1RF BPF HIGH BAND LNA 1 RXLBRF BPF LOW BAND LNA LPF LPF LPF VCMSEL GAIN CONTROL RXBW_TOGGLE
07092-036
LPF
RXBBIB
RXBBQ RXBBQB
RxGAIN[6:0]
LNAs
The ADF4602 contains three tunable RF front ends suitable for all major 3GPP frequency bands. Two are suitable for high band operation in the region 1700 MHz to 2170 MHz. One is suitable for operation from 824 MHz to 960 MHz. Thus, the three integrated LNAs offer the designer the opportunity to create multiband and regional specific variants with no additional components. LNA power control and internal band switching is fully controlled by the serial interface. The ADF4602 LNAs are designed for 50 single-ended inputs, thus further simplifying the front-end design and providing easy matching with minimal components. Typically, a twocomponent match is required: a series and shunt inductor. Within the LNA, the signal is converted to a differential path for signal processing in subsequent blocks within the receive signal chain. Interstage RF filtering is fully integrated, ensuring that external out-of-band blockers are suitably attenuated prior to the mixer stages. The LNA characteristic is designed to provide additional filtering at the transmitter frequency offset. The LNAs are enabled by programming bits rxbs[1:0] in Register 1. LNA input RXHB1RF should be used for UMTS Band I operation, and RXHB2RF should be used for UMTS Band II operation.
Quadrature drive is provided to the mixers from the receiver synthesizer section by the VCO transport system, which includes a programmable divider, so that the same VCO is used for both high and low bands. Excellent 90 quadrature phase and amplitude match are achieved by careful design and layout of the mixers and VCO transport circuits.
Baseband Section
The ADF4602 baseband section is a distributed gain and filter function designed to provide a maximum of 54 dB gain with 60 dB gain control range. Through careful design, pass band ripple, group delay, signal loss, and power consumption are kept to a minimum. Filter calibration is performed during the manufacturing process, resulting in a high degree of accuracy and ease of use. Three baseband filters are available on the ADF4602, as shown in Table 5. Bits rxbw_toggle[2:0] are used to select the mode of operation. The seventh order WCDMA filter with 1.92 MHz cutoff ensures that good attenuation of the adjacent channel should be used to meet blocking/adjacent channel selection specifications in femtocell applications. The GSM filter has a 100 kHz cut-off and is intended for use as a monitoring receiver in a home base station. The fifth order WCDMA filter provides less attenuation of the adjacent channel, so it should not be used in femtocell applications. The I and Q channels can be internally swapped, thus allowing optimum PCB routing between radio and analog baseband. This is achieved using the swapi and swapq bits. Table 5. Receive Baseband Filter Modes
Mode Seventh Order WCDMA Fifth Order WCDMA GSM Filter Cutoff Frequency (fC) 1.92 MHz 1.92 MHz 100 kHz
Mixers
High linearity quadrature mixer circuits are used to convert the RF signal to baseband in-phase and quadrature components. Although not shown in Figure 44, two mixer sections exist: one optimized for the high band LNA outputs and one optimized for the low band. The high band and low band mixer outputs are combined and then driven directly into the first stage of the baseband low-pass filter, which also acts to reduce the level of the largest blocking signals, prior to baseband amplification.
Rev. A | Page 21 of 36
ADF4602
The receive baseband outputs have a programmable common mode voltage of 1.2 V or 1.4 V, selectable via the vcmsel bit in Register 15.
BLOCK GAIN (dB)
120 110 100 90 80 70 60 50 40 30 20 10 0 10 0 10 20 30 RF GAIN BASEBAND GAIN CHIP GAIN 40 50 60 70 80 90 REQUESTED Rx GAIN (dB) 100 110 120
07092-037 07092-038
Gain Control
Gain control is distributed throughout the receive signal chain as shown in Figure 46. The RF front end contains 30 dB of control range: 18 dB in the LNA and 12 dB in the mixer transconductance stage. The two baseband active filter stages each provide 18 dB of gain control range in 6 dB steps. Filter characteristics (ripple and group delay) are best conserved if the active filter stages have equal gain. This results in a total of 36 dB gain control in 4 12 dB steps for the filter stage. The variable gain amplifier (VGA) implements 24 dB of gain controllable in 1 dB steps. The base gain of the mixer is 18 dB, and the base gain of the VGA is 6 dB. This gives a total of 102 dB gain with 90 dB of gain control range. The base gain of the mixer stage is 18 dB in WCDMA mode and 27 dB in GSM mode.
Figure 45. Gain Distribution Between RF and Baseband Blocks for Default Setting
50 45 40 35
BLOCK GAIN (dB)
To simplify programming and to ensure optimum receiver performance and dynamic range, the user simply programs the total desired receive gain in dB via the rx_gain[6:0] bits in Register 11. The ADF4602 then decodes the gain setting and automatically distributes the gain between the various blocks. To allow some flexibility, predefined user inputs control the gain threshold points at which the LNA and mixer gain steps occur. Bit settings mixstep[3:0] and lnastep[3:0] control the mixer and LNA gain threshold steps, respectively. An Excel spreadsheet detailing the receive gain decode system is available from Analog Devices, Inc., on request. Figure 45 shows an example gain distribution profile.
In addition, a gain calibration setting in Register 15 (gaincal[4:0]) is used to account for losses in the RF front end. The total gain in the ADF4602 is given by ReceiveGain = rxgain[6:0] gaincal[4:0] + X (2) where X = 8 in WCDMA filter mode, and X = 17 in GSM filter mode. Rxgain[6:0] is the receive gain programmed in Register 11. Gaincal[4:0] is the gain calibration setting in Register 15, and is calculated using the following formula: gaincal[4:0] = 8 front_end_losses (3) where front_end_losses is the loss in the receive path due to duplexers/switches. This is useful for referencing the programmed gain to the antenna and accounting for any losses in the path. For example, if the total receive front-end loss is 2 dB, the user should program gaincal[4:0] to 6 dB. If the user then requestes 80 dB of gain by programming rxgain[6:0] to 80 dB, the ADF4602 uses Equation 4 to give ReceiveGain = 80 6 + 8 = 82 dB 82 dB is the receive gain used internally by the ADF4602. (4)
Rev. A | Page 22 of 36
ADF4602
DC Offset Compensation
Due to the very high proportion of the total system gain assigned to the analog baseband function, compensating for dc offsets is an inherent part of any direct conversion solution. DC offsets are characterized as falling into two categories: static or slow varying and time varying The ADF4602 architecture has been designed to reduce the amount of time varying dc offsets. The device also includes a dc offset control system. The control system consists of ADCs at the baseband output to digitize dc offsets: a digital signal processing block where the characteristics of the loop are programmed for customization of the loops transfer function, and trim DACs that are used to introduce the error term back into the signal path. The offset control transfer function can either be programmed to act as a servo loop that is automatically triggered by a gain change or as a high-pass filter (HPF) with an automatic fast settling mode that is also triggered by a gain change. Parameters of the servo loop, high-pass filter, and fast settling mode are set by the initial ADF4602 programming. In operation, the dc offset control system is fully automatic and does not require any external programming. Recommended default programming conditions for the dc offset compensation loop are shown in the Register Description section.
SERIAL INTERFACE 1.8V LDO 1 LDO 2 LDO 3 LDO 4 LDO 5 RX BASEBAND AND RX VCO MIXERS RX LNAs TX VCO TX MOD TX BB PWR DET DACs RX PLL TX PLL REF PATH REF OP (SER INT READ) 2.8V
VBAT
VSUP1 C1
VSUP2 C2
VSUP3
VSUP4 C4
VSUP5 C5
VSUP6
VSUP7
VSUP8
1.9V C3 C6 C7
ANALOG BB OR VSUP2
07092-039
VINT supplies the serial interface enabling register data preservation with minimum current consumption during power-down. This should be supplied with 1.8 V externally. The five LDOs are individually powered up/down via bits ldoen[4:0] in Register 1. Table 7 summarizes the supply strategy. Note that the reference path (VSUP8) supply is supplied from an external source or the internal VSUP2. The external supply option may be convenient so that the entire reference path can be shut down by collapsing a single supply. VSUP8 can also be programmed to supply the voltage used for serial interface readback. See the Serial Port Interface (SPI) section for more information. Table 7. Power Management Strategy
Pin VINT VDD VSUP1 VSUP2 VSUP3 VSUP4 VSUP5 Connection External External Internal LDO1 Internal LDO2 Internal LDO3 Internal LDO4 Internal LDO5 Usage Serial interface control logic Main device supply, DAC1 Receive VCO Receive baseband and down-converter Receive LNAs Transmit VCO Transmit baseband, modulator, DAC2, and GPOs Receive synthesizer Transmit synthesizer Reference path, reference buffer outputs; Optional: serial interface readback Volts 1.8 V 3.3 V 2.6 V 2.8 V 1.9 V 2.6 V 2.8 V
POWER MANAGEMENT
The ADF4602 contains integrated power management requiring two external power supplies: 3.3 V VDD and 1.8 V VINT. Figure 47 shows a block diagram. VDD supplies the five integrated low drop-out regulators (LDOs), VSUP1 to VSUP5, that are used to supply the vast majority of the internal circuitry. VSUP6, VSUP7, and VSUP8 supply the receive PLL, transmit PLL, and reference block, respectively. These nodes require external connections to ensure good supply isolation and ensure a minimum level of interference between the PLL/reference blocks and the rest of the transceiver. VSUP6 and VSUP7 should be connected to VSUP3, whereas VSUP8 should be connected to VSUP2. Each node, VSUP1 to VSUP8, should be externally decoupled to ground with a 0.1 F capacitor. Y5V capacitors are not recommended for use here. X7R, X5R, C0G, or a similar type of capacitor should be used.
Rev. A | Page 23 of 36
ADF4602
FREQUENCY SYNTHESIS
The ADF4602 contains two fully integrated programmable frequency synthesizers for generation of transmit and receive local oscillator (LO) signals. The design uses a fractional-N architecture for low noise and fast lock-time. The fractional-N functionality is implemented with a third order - modulator. Figure 48 shows a block diagram of the synthesizer architecture.
LOOP FILTER FREF PFD C P VCO FVCO : 3.4GHz TO 4.4GHz RANGE 2 LPF
When the high band is enabled, the programmed frequency is equal to the LO frequency. For low band operation, the programmed frequency should be set to 2 the desired LO frequency. The transmit and receive synthesizers are enabled by setting Bit txsynthen and Bit rxsynthen in Register 1, respectively.
Reference Path
The ADF4602 requires a 26 MHz reference frequency input. A VCTCXO is used to provide this. The reference input is accoupled internally, so external ac coupling is not necessary. The 26 MHz reference is internally buffered and distributed to the respective blocks, such as the synthesizer PFD inputs. Figure 49 shows a block diagram.
DIGITAL DECODE
07092-040
RxFREQ[15:0]
The ADF4602 provides two buffered outputs: a buffered version of the 26 MHz reference on Pin REFCLK and a 19.2 MHz WCDMA chip clock on Pin CHIPCLK. The 19.2 MHz chip clock is a multiple of the 3.84 MHz chip rate used in WCDMA. Thus, it can be used to clock ADCs/DACs elsewhere in the system. The chip clock is generated by an integrated PLL and contains no user settings. Both outputs are slew rate limited and produce low swing digital outputs. The buffers contain their own 1.5 V regulator circuits to improve isolation and minimize unwanted supply noise. The 26 MHz and 19.2 MHz buffer outputs are enabled or disabled by programming Bit refclken and Bit chipclken (Register 1).
26MHz CLOCK DISTRIBUTION VSUP8 REFIN (26MHz)
All necessary components are fully integrated for both transmit and receive synthesizers, including loop filters, VCOs, and tank components. The VCOs run at 2 the high band frequency and 4 the low band frequency. The dividers are external to the synthesizer loop. This minimizes VCO leakage power at the desired frequency and tuning range requirements of the VCO. The VCOs use a multiband structure to cover the wide frequency range required. The design incorporates both frequency and amplitude calibration to ensure that the oscillator is always operating with its optimum performance. The calibrations occur during the 200 s PLL lock time and are fully self contained, requiring no user inputs. The charge pump and loop filter are internally trimmed to remove variations associated with manufacture and frequency. This process is fully automated. To aid simplified programming, the ADF4602 contains a frequency decode table for the synthesizers, meaning the programmer is not concerned with the internal operation of the counters and fractional-N system. Frequency step sizes of 50 kHz are possible with both transmit and receive synthesizers. The programming words rxfreq[15:0] and txfreq[15:0] set the frequency in 50 kHz steps from 0 MHz to 3276.75 MHz. Note that the synthesizers do not cover this full range. The frequency range for each synthesizer in high and low bands is given in the Specifications section.
REFCLK
CHIPCLK
VSUP8
All reference sections are powered from VSUP8, which can safely be removed from the chip in isolation, to enter a low current power-down mode. Calibration data is not lost, but the reference frequency ceases to exist. As soon as VSUP8 is reapplied, oscillation begins. This is visible at the buffer outputs, as long as they were previously enabled.
Rev. A | Page 24 of 36
07092-041
Format
Figure 50 shows the format of the register write. This consists of a 5-bit address and 16-bit data words. The exception is register A1 = 00000, where the lower data byte is used as an 8-bit subaddress. In total, this creates 31 16-bit registers and 256 8-bit registers. The 31 16 bit registers are referred to in the text as Register 31 for example, while the 256 8-bit sub registers are referred to as Register 0.144. OP is a 2-bit code specifying the type of operation being performed (see Table 8 for more information). The chip select code, CS, is a 3-bit field indicating which device on the bus is being programmed. For the ADF4602, CS should be set to 001 (D2, D1, D0). Table 8. SPI Operation Code
OP[1] 0 0 OP[0] 0 1 Operation Write Set Description Normal register write. Register bits corresponding to 1s in the data word are set. Other bits are not modified. Register bits corresponding to 1s in the data word are cleared. Other bits are not modified. Register read request.
Read
Figure 3 shows a read operation. First, a read request is written by the host to the ADF4602. SEN must remain high for at least three SCLK periods between the read request operation and the following read operation. The host must release the SDATA line during this period. The ADF4602 takes control of SDATA, and the read operation commences when the host device drives SEN low. The SDATA output voltage during readback is set to 1.8 V or 2.8 V. Bit sif_vsup8 (Register 2) controls this. A 0 in this bit configures the device to use the 1.8 V VINT supply, whereas a 1 configures the 2.8 V VSUP8 supply. After power-up or after a soft reset, the ADF4602 defaults to 2.8 V readback mode.
Clear
Read
OPERATION WRITE REGISTER 1 TO 31 W[25:0] WRITE REGISTER 0 W[25:0] READ REQUEST REGISTER 1 TO 31 Q[25:0] READ REQUEST REGISTER 0 Q[25:0] READ REGISTER 1 TO 31 Q[25:0] READ REGISTER 0 Q[25:0]
BIT POSITION 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 DATA D[15:0] DATA D[7:0] SUBADDRESS A2[7:0] RANDOM PADDING P[15:0] RANDOM PADDING P[7:0] DATA D[15:0] DATA D[7:0] SUBADDRESS A2[7:0] SUBADDRESS A2[7:0] 9 8 7 6 5 4 3 2 1 CS [2:0] CS [2:0] CS [2:0] CS [2:0] CS [2:0]
07092-042
ADDRESS A1[4:0] ADDRESS A1 = 00000 ADDRESS A1[4:0] ADDRESS A1[4:0] ADDRESS A1[4:0] ADDRESS A1 = 00000
OP = 11
OP = 11
CS [2:0]
Rev. A | Page 25 of 36
ADF4602 REGISTERS
REGISTER MAP
GENERAL USER REGISTERS A1 1 2 D15 D14 D13 rxen D12 refclk en D11 chipclk en D10 D9 D8 ldoen[4:0] D7 D6 D5 txen D4 txbs D3 txsynth en D2 D1 D0 rxsynth en reset_ soft DEFAULT1 R/W 0x2FFD 0x0002 W W
RECEIVER USER REGISTERS A1 10 11 12 13 14 15 rfskip[3:0] osadc2x[3:0] nint3[3:0] vcmsel sdmen[3:0] nper2[3:0] nint2[3:0] swapq swapi rxbw[2:0] mixstep[3:0] nper1[3:0] nint1[3:0] gaincal[4:0] D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DEFAULT1 R/W 0x9858 rxgain[6:0] lnastep[3:0] nper0[3:0] nint0[3:0] sdmosr 0x0000 0x0FA6 0x103E 0xEE53 0x0890 W W W W W W
rxfreq[15:0]
TRANSMITTER USER REGISTERS A1 21 22 26 28 31 31 dacgpo _owen D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 cmmod D5 D4 D3 D2 D1 D0 DEFAULT1 R/W 0x001F 0x8000 0x0000 cntrl_ mode nvmld revid[7:0] 0x0001 0x0000 0x0021 W W W W W R
test_I/swap_I gpo_ow[3:0]
test_Q/swap_Q
vcm_sat_thres[5:0] padac1[4:0]
txfreq[15:0] txpwr_set[11:0]
SUB-ADDRESS REGISTERS A1 0 0 0 0 0 0 A2 144 151 153 155 165 170 en_mix[3:0] vsup2[7:0] reserved[7:0] reserved[7:0] reserved[7:0] D7 D6 D5 D4 D3 D2 D1 D0 DEFAULT1 R/W 0x06 0x6F 0x85 0x78 0x20 0xF0 W W W W W W
07092-043
reserved[1:0]
NOTES 1THESE ARE RECOMMENDED DEFAULT SETTINGS THAT SHOULD BE PROGRAMMED INTO THE REGISTERS.
Rev. A | Page 26 of 36
ADF4602
REGISTER DESCRIPTION
Table 10. General User Registers
Register 1, A1, Write Bit 13 12 11 [10:6] Bit Name rxen refclken chipclken ldoen Description Set this bit high to enable the receiver. A low here disables the receiver. Setting this bit high enables the 26 MHz reference output buffer. Setting this bit high enables the19.2 MHz chip clock output buffer. The on-chip LDOs are powered down individually. For normal operation all LDOs should be enabled (Bits[10 : 6] = [11111]) ldoen[10:6] 1 Mode XXXX1 VSUP1 2.6 V enable XXX1X VSUP2 2.8 V enable XX1XX VSUP3 1.8 V enable X1XXX VSUP4 2.6 V enable 1XXXX VSUP5 2.8 V enable Setting this bit high enables the transmitter. This bit controls which of the transmit outputs is in use. 0 = low band (TXLBRF), 1 = high band (TXHBRF). Setting this bit high enables the transmit synthesizer. These bits control the receiver band select. rxbs[2:1] Operation 00 Reserved 01 Low band enable (RXLBRF) 10 High Band 1 enable (RXHB1RF) (default) 11 High Band 2 enable (RXHB2RF) Setting this bit high enables the receive synthesizer The serial port readback (SDATA) output voltage is changed from 1.8 V to 2.8 V with this bit. 0 = use 1.8 V VINT supply, 1 = use 2.8 V VSUP8 supply. After power-up or after a soft reset, the ADF4602 defaults to 2.8 V readback mode. A rising edge on this bit starts a 50 s reset pulse for the full chip. This bit is self clearing. It is recommended that a soft reset be performed after power-up.
5 4 3 [2:1]
2, A1, Write
0 1
rxsynthen sif_vsup8
0
1
reset_soft
X = dont care.
Rev. A | Page 27 of 36
ADF4602
Table 11. Receiver User Registers
Register 10, A1, Write Bit [15:0] Bit Name rxfreq Description These bits set the receive synthesizer frequency in 50 kHz steps from 0 MHz to 3276.75 MHz. For the high bands this is equal to the channel frequency, and for the low bands it is 2 the channel frequency. For example: RXHB1RF, RXHB2RF Synthesizer Bit 15 to Bit 0 (Hex) Frequency RXLBRF Synthesizer Frequency 0x9470 1900 MHz 950 MHz 0x9858 1950 MHz 975 MHz These bits set the receiver gain in conjunction with the gaincal[4:0] setting in register 15. LSB = 1 dB. 0x00 = 0dB, 0x7F = 127 dB. Gain = rxgain gaincal + X where X is 8 in WCDMA mode and 17 in GSM mode. The mode is selected by the rxbw bits in Register 15. With mixstep = 6 and lnastep = 10, the valid range for rxgain is from 12 dB to 102 dB. Settings outside of these are clipped at 12 dB and 102 dB. See Figure 45 for an example. Skip offset control state when no RF gain step occurred for State 3 to State 0. Default = 0x0 = 0. - modulator enable for State 3 to State 0. Default = 0xF = 15. Gain decode threshold for mixer gain reduction step. LSB = 4 dB steps. Default = 0xA = 10. Gain decode threshold for LNA gain reduction step. LSB = 4 dB steps. Default = 0x6 = 6. Offset measurement ADC range for State 3 to State 0. Default = 0x1 = 1. State duration for State 2. Default = 0x0 = 0. State duration for State 1. Default = 0x3 = 3. State duration for State 0. Default = 0xE = 14. Integrator time constant for State 3. Default = 0xE = 14. Integrator time constant for State 2. Default =0xE = 14. Integrator time constant for State 1. Default = 0x5 = 5. Integrator time constant for State 0. Default = 0x3 = 3. This sets the receive baseband output common-mode voltage. 0 = 1.2 V, 1 = 1.4 V. Setting this bit high swaps the differential Q outputs, RXBBQ and RXBBQB. Setting this bit high swaps the differential I outputs, RXBBI and RXBBIB. This bit controls the receive baseband filter bandwidth. rxbw [8:6] Filter Mode 000 Fifth order WCDMA filter (not recommended for femtocells) 010 Seventh order WCDMA filter (recommended WCDMA filter for femtocells) 111 GSM filter Else Reserved These bits are used for calibration of front-end loss. LSB = 1 dB, 0x00 = 0 dB, 0x1F = 31 dB. It is used in the calculation of the receive gain. See rxgain in Register 11. If not used for calibration, this should be set to 8 in WCDMA mode and 17 in GSM mode. Offset loop - modulator over sampling ratio. 1 = 4, 0 = 2 (default)
[6:0]
rxgain
[15:12] [11:8] [7:4] [3:0] [15:12] [11:8] [7:4] [3:0] [15:12] [11:8] [7:4] [3:0] 11 10 9 [8:6]
rfskip sdmen mixstep lnastep osadc2x nper2 nper1 nper0 nint3 nint2 nint1 nint0 vcmsel swapq swapi rxbw
[5:1]
gaincal
sdmosr
Rev. A | Page 28 of 36
ADF4602
Table 12. Transmitter User Registers
Register 21, A1, Write Bit [12:11] Bit Name test_I/swap_I Description These bits allow various options on the I inputs as detailed in the following table: Bits Function 00 Normal operation 01 Swap I differential inputs for ease of PCB routing to DAC 10 Zero input on I inputs 11 DC offset applied to I inputs; creates large carrier at RF These bits allow various options on the Q inputs as detailed in the table below: Bits Function 00 Normal operation 01 Swap Q differential inputs for ease of PCB routing to DAC 10 Zero input on Q inputs 11 DC offset applied to Q inputs: creates large carrier at RF During a transmit gain change, some spectral splatter may occur at the output of the transmitter. These bits allow the input baseband signal at the input to the low-pass filter to be blanked for a short period, to reduce the spectral splatter observed during the gain change. gain_blanksel[8:7] Operation 00 Default setting; no blanking 01 230 ns blanking 10 540 ns blanking 11 850 ns blanking This bit adjusts the internal modulator common-mode setting. It should be set to 0. Setting this bit to 1 results in reduced power consumption but degrades transmit linearity. This bit should be set to 0x1F for normal operation. Setting this bit high allows the user to have manual control over DAC2 and GPO1 to GPO4. These bits allow manual control of GPO 1 to GPO 4. Bit dacgpo_owen must be set to 1 to allow this mode of operation. Each bit controls one of the GPOs as per the following table. This allows all possible permutations of GPO output combinations. gpo_ow[14 :11] 1 Mode XXX1 GPO1 high XX1X GPO2 high X1XX GPO3 high 1XXX GPO4 high These bits allow manual control of DAC2. Bit dacgpo_owen must be set to 1 to allow this mode of operation. These bits control DAC1. These bits set the transmitter synthesizer frequency in 50 kHz steps from 0 MHz to 3276.75 MHz. For the high bands, this is equal to the channel frequency, and for the low bands it is 2 the channel frequency. For example: Bit 15 to Bit 0 (Hex) HB Synthesizer Frequency LB synthesizer Frequency 0xA730 2140 MHz 1070 MHz 0xA988 2170 MHz 1085 MHz
[10:9]
test_Q/swap_Q
[8:7]
gain_blanksel
Rev. A | Page 29 of 36
ADF4602
Register 28, A1 Write Bit [15:4] Bit Name txpwr_set Description Requested transmit power at antenna. LSB = 1/32 dBm, 0x000 = 80 dBm, 0xFFF = 47.96875 dBm. The output power is referenced to a full scale sine wave applied to the transmit baseband inputs. For WCDMA modulated signals, the output power measured in a 3.84 MHz bandwidth is reduced by the peak to average ratio of the signal. See the I/Q Modulator section for more details. The valid range of transmit output power setting is 80 dBm to +10 dBm. Output clipping may occur sooner, depending on the PAR of the applied signal. The txpwr_set register should be updated periodically, or with every 5C change in temperature to ensure accurate output power. See the VCO Output section for more details. Set this bit to 1 to control the output power from the txpwr_set bits. Setting this bit to 1 triggers a manual load of the nonvolatile memory contents. See the Software Initialization Procedure section for more details. Chip Revision ID. Revision represented in hex value. A readback of 0x21 represents Rev 2.1.
0 4 [7:0]
nvmld revid
X = dont care.
Rev. A | Page 30 of 36
2 3 4 5 6
0.151 31 31 0.151 01
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
1
0x0FA6 0x103E 0xEE53 0x0890 0x001F 0x8000 0x06 0x78 0x85 0x20 0xF0 0x0050 0x9858 0xA730 0x2FFD 0xA001
Register numbers 0.xxx are 8-bit registers as described in the SPI Interface section of the ADF4602-x data sheet.
Rev. A | Page 31 of 36
ADF4602
Nonvolatile Memory (NVM) Initialization
The ADF4602 has on-chip non-volatile memory (NVM) that contains chip factory calibration coefficients. A soft reset of the device transfers the contents of NVM to internal registers; however, this has been found to be unreliable if performed at temperatures below 0C. The software work-around outlined in Step 2 to Step 5 of Table 14 ensures that the NVM data is transferred reliably under all operating conditions. It involves setting the VSUP2 on-chip regulator to 3.1 V, manually transferring the data by setting the nvmld bit in Register 31, and then resetting the VSUP2 regulator to 2.8 V. Device programming can then continue as normal. matically turned off to prevent any unwanted transmissions as the PLL locks. The user should wait 200 s (time taken for PLL to lock), and then set the output power to the desired value by writing to Register 28. If the user disables the transmit synthesizer, the transmit output power must be turned off before reenabling the transmit synthesizer. This is achieved by two means: setting Bit D5 in Register 1 or setting the output power in Register 28 to a minimum. After reenabling the synthesizer, and then locking the synthesizer to a frequency by programming the frequency word in Register 26, the user can reenable the output power. To change the receive frequency, simply program the new frequency in Register 10, and wait 200 s before using the device as a transceiver. The receive gain is set at any time (apart from during the 200 s PLL locking transient).
Rev. A | Page 32 of 36
AD9963
RXBBIB 100 68pF RXIN
08801-118
ADC
ADF4602
RECEIVE SENSITIVITY
Figure 31 shows the ADF4602 receive sensitivity vs. frequency for UMTS Band I using the RXHB1RF input port. The sensitivity degradation due to the 63rd and 64th harmonics of the 30.72 MHz ADC sampling frequency can be seen near 1935 MHz and 1966 MHz. The sensitivity degradation caused by these harmonics was minimized by placing 100 series resistors and 68 pF filtering capacitors at the ADC inputs (see Figure 52). Note the sensitivity degradation due to the 76th frequency harmonic of the 26 MHz reference at 1976 MHz. The degraation in sensitivity is less than 3 dB for these harmonics. Overall, the solution exceeds the 3GPP sensitivity specifications by 7 dB across the frequency range. In addition, note that the 100 F capacitors to ground at the AD9963 DAC outputs will minimize sensitivity degradation due to DAC clock harmonics, particularly in UMTS sniff mode.
In this configuration, the ADF4602 is setting the commonmode input voltage of the AD9963 ADCs to 1.4 V. The input common-mode buffer of the AD9963 should be disabled (set Register 0x7E, Bit 1 = 1) to avoid contention with the ADF4602 output driver.
Reference Voltage
There is a single reference voltage that is used by both the I and Q channel DACs. The AD9963 REFIO reference voltage is generated by an internal 100 A current source terminated into
Rev. A | Page 33 of 36
ADF4602
Interfacing to the AD9963 TX Baseband Outputs
The ADF4602 transmit baseband inputs accept a 1.2 V commonmode input signal with 1 V p-p differential swing. The configuration in Figure 53 is used to provide this from the AD9963 TxDACs.
TXBBIB TXBBI 249 249 226 249 0.1uF
100pF
TXIP TXCML
The AD9963 can be dc coupled to the ADF4602 as shown in Figure 53. When configured for a 2 mA full-scale current, the output swing of the circuit is 1 V p-pd. centered at 1.2 V. The AD9963 TXMCL pin is biased at 0.5 V to increase the headroom of the DAC outputs. The AD9963 TXVDD and CLK33V supplies must be supplied with 3.3 V to support this output compliance range from the DACs. The optional 100 k resistors connected between the AUXIO pins and the TXIN (and TXQN) pins allow a dc offset to be provided to null out carrier leakage at the ADF4602 outputs. .
100pF
TXIN
AUXIO2 TXQP
100pF
ADF4602
TXBBQB
249
AD9963
100pF
TXQN
07092-129
100k
AUXIO3
Rev. A | Page 34 of 36
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
5.75 BSC SQ
EXPOSED PAD
(BOT TOM VIEW)
21 20
11
12 MAX
Figure 54. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm 6 mm Body, Very Thin Quad (CP-40-1) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 ADF4602BCPZ ADF4602BCPZ-RL EV-ADF4602EB3ZTST EVAL-ADF4602EB3Z EVAL-ADF4602EB5Z
1
Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Baseband Adapter Board UMTS Band I Femtocell Base Station Evaluation Board. Includes UMTS Mode. UMTS Band II/Band V Femtocell Base Station Evaluation Board. Includes UMTS Mode.
072108-A
SEATING PLANE
0.20 REF
COPLANARITY 0.08
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
Rev. A | Page 35 of 36
ADF4602 NOTES
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