ADF4002
ADF4002
ADF4002
FEATURES
400 MHz bandwidth 2.7 V to 3.3 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3 V systems Programmable charge pump currents 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode 104 MHz phase detector
APPLICATIONS
Clock conditioning Clock generation IF LO generation
CHARGE PUMP
CP
22
SDOUT
M3 M2 M1
ADF4002
CE AGND DGND
06052-001
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 20062011 Analog Devices, Inc. All rights reserved.
Data Sheet
MUXOUT and Lock Detect.........................................................9 Input Shift Register .......................................................................9 Latch Maps and Descriptions ....................................................... 10 Latch Summary........................................................................... 10 Reference Counter Latch Map.................................................. 11 N Counter Latch Map................................................................ 12 Function Latch Map................................................................... 13 Initialization Latch Map ............................................................ 14 Function Latch............................................................................ 15 Initialization Latch ..................................................................... 16 Applications..................................................................................... 17 Very Low Jitter Encode Clock for High Speed Converters... 17 PFD............................................................................................... 17 Interfacing ................................................................................... 17 PCB Design Guidelines for Chip Scale Package .................... 18 Outline Dimensions ....................................................................... 19 Ordering Guide .......................................................................... 19
REVISION HISTORY
9/11Rev. A to Rev. B Changes to Normalized Phase Noise Floor (PNSYNTH) Parameter and Endnote 6, Table 1..................................................................... 4 Added Normalized 1/f Noise (PN1_f) Parameter and Endnote 7, Table 1 ................................................................................................ 4 Changes to Figure 4 and Table 5..................................................... 6 Updated Outline Dimensions ....................................................... 19 4/07Rev. 0 to Rev. A Changes to Features List .................................................................. 1 Changes to Table 1............................................................................ 3 Deleted Figure ................................................................................... 7 Changes to Figure 16...................................................................... 11 4/06Revision 0: Initial Version
Rev. B | Page 2 of 20
ADF4002
For RFIN < 5 MHz, ensure slew rate (SR) > 4 V/s For REFIN < 20 MHz, ensure SR > 50 V/s Biased at AVDD/23
ABP = 0, 0 (2.9 ns antibacklash pulse width) Programmable, see Figure 18 With RSET = 5.1 k With RSET = 5.1 k See Figure 18 TA = 25C 0.5 V VCP VP 0.5 V 0.5 V VCP VP 0.5 V VCP = VP/2
5 625 2.5 3.0 1 1.5 2 2 1.4 0.6 1 10 1.4 VDD 0.4 100 0.4 2.7 AVDD AVDD 5.0 1 3.3 5.5 6.0 0.4 11
mA A % k nA % % % V V A pF V V A V V V mA mA A
Open-drain output chosen, 1 k pull-up resistor to 1.8 V CMOS output chosen IOL = 500 A
Rev. B | Page 3 of 20
ADF4002
Parameter NOISE CHARACTERISTICS Normalized Phase Noise Floor (PNSYNTH) 6 Normalized 1/f Noise (PN1_f) 7
1 2
Data Sheet
Min B Version 1 Typ Max 222 119 Unit dBc/Hz dBc/Hz Test Conditions/Comments PLL loop bandwidth = 500 kHz, measured at 100 kHz offset 10 kHz offset; normalized to 1 GHz
Operating temperature range (B version) is 40C to +85C. AVDD = DVDD = 3 V. 3 AC coupling ensures AVDD/2 bias. 4 Guaranteed by design. Sample tested to ensure compliance. 5 TA = 25C; AVDD = DVDD = 3 V; RFIN = 350 MHz. The current for any other setup (25C, 3.0 V) in mA is given by 2.35 + 0.0046 (REFIN) + 0.0062 (RF), RF frequency and REFIN frequency in MHz. 6 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value) and 10 logFPFD. PNSYNTH = PNTOT 10 logFPFD 20 logN. 7 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF, and at a frequency offset, f, is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). All phase noise measurements were performed with the EVAL-ADF4002EBZ1 and the Agilent E5500 phase noise system. Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
TIMING CHARACTERISTICS
AVDD = DVDD = 3 V 10%, AVDD VP 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 k, dBm referred to 50 , TA = TMAX to TMIN, unless otherwise noted. 1 Table 2.
Parameter t1 t2 t3 t4 t5 t6
1 2
Limit (B Version) 2 10 10 25 25 10 20
Test Conditions/Comments DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width
Guaranteed by design, but not production tested. Operating temperature range (B version) is 40C to +85C.
Timing Diagram
t3
CLK
t4
t1
DATA DB23 (MSB) DB22
t2
DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1)
t6
LE
t5
LE
06052-022
Rev. B | Page 4 of 20
ADF4002
This device is a high performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly.
Rating 0.3 V to +3.6 V 0.3 V to +0.3 V 0.3 V to +5.8 V 0.3 V to +5.8 V 0.3 V to VDD + 0.3 V 0.3 V to VP + 0.3 V 0.3 V to VDD + 0.3 V 40C to +85C 65C to +125C 150C 215C 220C 6425 303
THERMAL CHARACTERISTICS
Table 4. Thermal Impedance
Package Type TSSOP LFCSP JA 150.4 122 Unit C/W C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. B | Page 5 of 20
Data Sheet
PIN 1 16 INDICATOR 15 14
VP DVDD MUXOUT
PIN 1 INDICATOR
ADF4002
TOP VIEW (Not to Scale)
11 10 9
CLK
06052-002
DGND
2 3 4 5 6 7 8
20 1 2, 3 4 5 6, 7 8
9 10 11 12 13 14 15 16
9, 10 11 12 13 14 15 16, 17 18
where RSET = 5.1 k and ICP MAX = 5 mA. Charge Pump Output. When enabled, this provides ICP to the external loop filter that, in turn, drives the external VCO. Charge Pump Ground. This is the ground return path for the charge pump. Analog Ground. This is the ground return path of the RF input. Complementary Input to the RF Input. This point must be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. See Figure 11. Input to the RF Input. This small signal input is ac-coupled to the external VCO. Analog Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to the AVDD pin. AVDD must be the same value as DVDD. Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of 100 k. See Figure 10. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled. Digital Ground. Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into threestate mode. Taking this pin high powers up the device, depending on the status of the Power-Down Bit F2. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches; the latch is selected using the control bits. Multiplexer Output. This allows either the lock detect, the scaled RF, or the scaled reference frequency to be accessed externally. Digital Power Supply. This can range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD. Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V. Exposed Pad. The exposed pad must be connected to AGND.
Rev. B | Page 6 of 20
06052-003
CE
ADF4002
130 135 140
PHASE NOISE (dBc/Hz)
40C
06052-027
06052-033
10
POWER (dBm)
145 155 160 165 170 175 180 100k 1M 10M PFD FREQUENCY (Hz) 100M
15 20 25 30 35 40 +85C
+25C
100
200
300
400
500
600
1G
FREQUENCY (MHz)
0
5
ATTN 10dB 1R
10
40C +25C
20 30 40
POWER (dBm)
10
15
+85C
50 60
20
06052-026
70 80 90 100 CENTER 399.995MHz RES BW 20kHz VBW 20kHz SPAN 2.2MHz SWEEP 21ms (601pts) 1 94.5dBc
06052-030
25
10
FREQUENCY (MHz)
10M
Rev. B | Page 7 of 20
Data Sheet
The equation for the VCO frequency is
f VCO = N
where:
f REFIN R
fVCO is the output frequency of external voltage controlled oscillator (VCO). N is the preset divide ratio of binary 13-bit counter (1 to 8191). fREFIN is the external reference frequency oscillator.
FROM N COUNTER LATCH
NC REFIN
100k SW2
NC SW1
TO R COUNTER BUFFER
13-BIT N COUNTER TO PFD
06052-021
NO
SW3
R COUNTER
The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed.
RF INPUT STAGE
The RF input stage is shown in Figure 11. It is followed by a 2-stage limiting amplifier to generate the CML clock levels needed for the N counter.
BIAS GENERATOR
500 1.6V AVDD 500
RFINA
RFINB
AGND
N COUNTER
The N CMOS counter allows a wide ranging division ratio in the PLL feedback counter. Division ratios from 1 to 8191 are allowed.
HI R DIVIDER
06052-014
D1
Q1 U1
UP
CLR1
N and R Relationship
The N counter makes it possible to generate output frequencies that are spaced only by the reference frequency divided by R.
U3 CP
HI
CLR2 DOWN D2 Q2
06052-023
U2 N DIVIDER CPGND
Rev. B | Page 8 of 20
Data Sheet
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4002 allows the user to access various internal points on the chip. The state of MUXOUT is controlled by M3, M2, and M1 in the function latch. Figure 18 shows the full truth table. Figure 14 shows the MUXOUT section in block diagram form.
DVDD
ADF4002
analog lock detect is more accurate because of the smaller pulse widths. The N-channel, open-drain, analog lock detect should be operated with an external pull-up resistor of 10 k nominal. When lock has been detected, this output is high with narrow, low going pulses.
ANALOG LOCK DETECT DIGITAL LOCK DETECT R COUNTER OUTPUT N COUNTER OUTPUT SDOUT MUX CONTROL
MUXOUT
DGND
Lock Detect
MUXOUT can be programmed for two types of lock detect: digital lock detect and analog lock detect. Digital lock detect is active high. When LDP in the R counter latch is set to 0, digital lock detect is set high when the phase error on three consecutive phase detector (PD) cycles is less than 15 ns. With LDP set to 1, five consecutive cycles of less than 15 ns are required to set the lock detect. It stays set at high until a phase error of greater than 25 ns is detected on any subsequent PD cycle. For PFD frequencies greater than 10 MHz,
Rev. B | Page 9 of 20
06052-024
Data Sheet
RESERVED
ANTIBACKLASH WIDTH
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 X 0 0 LDP T2 T1 ABP2 ABP1 R14 R13 R12 R11 R10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1 C2 (0)
DB0 C1 (0)
N COUNTER LATCH
CP GAIN
RESERVED
13-BIT N COUNTER
RESERVED
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 X X G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3
DB9 B2
DB8 B1
DB7 X
DB6 X
DB5 X
DB4 X
DB3 X
DB2 X
DB1
DB0
C2 (0) C1 (1)
FUNCTION LATCH
FASTLOCK ENABLE
FASTLOCK MODE
CP THREESTATE
PD POLARITY
RESERVED
CURRENT SETTING 2
COUNTER RESET
POWERDOWN 2
POWERDOWN 1
CURRENT SETTING 1
MUXOUT CONTROL
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 X X PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5
DB9 F4
DB8 F3
DB7 F2
DB6 M3
DB5 M2
DB4 M1
DB3 PD1
DB2 F1
DB1
DB0
C2 (1) C1 (0)
INITIALIZATION LATCH
FASTLOCK ENABLE
FASTLOCK MODE
CP THREESTATE
PD POLARITY
RESERVED
CURRENT SETTING 2
CURRENT SETTING 1
COUNTER RESET
POWERDOWN 2
POWERDOWN 1
MUXOUT CONTROL
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 X X PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5
DB9 F4
DB8
F3
DB7 F2
DB6 M3
DB5 M2
DB4 M1
DB3 PD1
DB2 F1
DB1
DB0
06052-015
C2 (1) C1 (1)
Rev. B | Page 10 of 20
Data Sheet
REFERENCE COUNTER LATCH MAP
LOCK DETECT PRECISION
RESERVED TEST MODE BITS ANTIBACKLASH WIDTH 14-BIT REFERENCE COUNTER
ADF4002
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 X 0 0 LDP T2 T1 ABP2 ABP1 R14 R13 R12 R11 R10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1 C2 (0)
DB0 C1 (0)
X = DONT CARE
R14 0 0 0 0 . . . 1 1 1 1 R13 0 0 0 0 . . . 1 1 1 1 R12 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... R3 0 0 0 1 . . . 1 1 1 1 R2 0 1 1 0 . . . 0 0 1 1 R1 1 0 1 0 . . . 0 1 0 1 DIVIDE RATIO 1 2 3 4 . . . 16380 16381 16382 16383
ABP2 0 0 1 1
ABP1 0 1 0 1
LDP 0 1
OPERATION THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET. FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN 15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
Rev. B | Page 11 of 20
06052-025
ADF4002
N COUNTER LATCH MAP
CP GAIN
RESERVED 13-BIT N COUNTER RESERVED
Data Sheet
CONTROL BITS
DB23 X
DB22 X
DB21 G1
DB20 B13
DB19 B12
DB18 B11
DB17 B10
DB16 B9
DB15 B8
DB14 B7
DB13 B6
DB12 B5
DB11 B4
DB10 B3
DB9 B2
DB8 B1
DB7 X
DB6 X
DB5 X
DB4 X
DB3 X
DB2 X
DB1
DB0
C2 (0) C1 (1)
X = DONT CARE
N13 0 0 0 0 . . . 1 1 1 1
N12 0 0 0 0 . . . 1 1 1 1
N11 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
N3 0 0 0 0 . . . 1 1 1 1
N2 0 0 1 1 . . . 0 0 1 1
N1 0 1 0 1 . . . 0 1 0 1
OPERATION
0 0 1 1
0 1 0 1
CHARGE PUMP CURRENT SETTING 1 IS PERMANENTLY USED. CHARGE PUMP CURRENT SETTING 2 IS PERMANENTLY USED. CHARGE PUMP CURRENT SETTING 1 IS USED. CHARGE PUMP CURRENT IS SWITCHED TO SETTING 2. THE TIME SPENT IN SETTING 2 IS DEPENDENT ON WHICH FASTLOCK MODE IS USED. SEE FUNCTION LATCH DESCRIPTION.
THESE BITS ARE NOT USED BY THE DEVICE AND ARE DON'T CARE BITS.
Rev. B | Page 12 of 20
06052-016
THESE BITS ARE NOT USED BY THE DEVICE AND ARE DON'T CARE BITS.
Data Sheet
FUNCTION LATCH MAP
FASTLOCK MODE FASTLOCK ENABLE CP THREESTATE PD POLARITY COUNTER RESET POWERDOWN 2 POWERDOWN 1
ADF4002
RESERVED
CURRENT SETTING 2
CURRENT SETTING 1
MUXOUT CONTROL
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 X X PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5
DB9 F4
DB8 F3
DB7 F2
DB6 M3
DB5 M2
DB4 M1
DB3 PD1
DB2 F1
DB1
DB0
C2 (1) C1 (0)
F2 0 1
F1 0 1
F3 0 1
F4 0 1 1
F5 X 0 1
TC4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
TC3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
TC2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
TC1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
M3 0 0 0 0 1 1 1 1
M2 0 0 1 1 0 0 1 1
M1 0 1 0 1 0 1 0 1
OUTPUT THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) N DIVIDER OUTPUT DVDD R DIVIDER OUTPUT N-CHANNEL OPEN-DRAIN LOCK DETECT SERIAL DATA OUTPUT DGND
CPI6 CPI3 0 0 0 0 1 1 1 1
CPI5 CPI2 0 0 1 1 0 0 1 1
CP14 CPI1 0 1 0 1 0 1 0 1 3k 1.088 2.176 3.264 4.352 5.440 6.528 7.616 8.704
ICP (mA) 5.1k 0.625 1.250 1.875 2.500 3.125 3.750 4.375 5.000 11k 0.294 0.588 0.882 1.176 1.470 1.764 2.058 2.352
CE PIN 0 1 1 1
PD2 X X 0 1
PD1 X 0 1 1
Rev. B | Page 13 of 20
06052-017
THESE BITS ARE NOT USED BY THE DEVICE AND ARE DON'T CARE BITS.
ADF4002
INITIALIZATION LATCH MAP
FASTLOCK MODE FASTLOCK ENABLE CP THREESTATE PD POLARITY
RESERVED CURRENT SETTING 2 CURRENT SETTING 1
Data Sheet
COUNTER RESET
DB2 F1
POWERDOWN 2
POWERDOWN 1
MUXOUT CONTROL
CONTROL BITS
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 X X PD2 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2 TC1 F5
DB9 F4
DB8 F3
DB7 F2
DB6 M3
DB5 M2
DB4 M1
DB3 PD1
DB1
DB0
C2 (1) C1 (1)
F2 0 1
F1 0 1
F3 0 1
F4 0 1 1
F5 X 0 1
TC4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
TC3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
TC2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
TC1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
M3 0 0 0 0 1 1 1 1
M2 0 0 1 1 0 0 1 1
M1 0 1 0 1 0 1 0 1
OUTPUT THREE-STATE OUTPUT DIGITAL LOCK DETECT (ACTIVE HIGH) N DIVIDER OUTPUT DVDD R DIVIDER OUTPUT N-CHANNEL OPEN-DRAIN LOCK DETECT SERIAL DATA OUTPUT DGND
CPI6 CPI3 0 0 0 0 1 1 1 1
CPI5 CPI2 0 0 1 1 0 0 1 1
CP14 CPI1 0 1 0 1 0 1 0 1 3k 1.088 2.176 3.264 4.352 5.440 6.528 7.616 8.704
ICP (mA) 5.1k 0.625 1.250 1.875 2.500 3.125 3.750 4.375 5.000 11k 0.294 0.588 0.882 1.176 1.470 1.764 2.058 2.352
CE PIN 0 1 1 1
PD2 X X 0 1
PD1 X 0 1 1
Rev. B | Page 14 of 20
06052-036
THESE BITS ARE NOT USED BY THE DEVICE AND ARE DON'T CARE BITS.
Data Sheet
FUNCTION LATCH
With C2, C1 set to 1, 0, the on-chip function latch is programmed. Figure 18 shows the input data format for programming the function latch.
ADF4002
Fastlock Mode Bit
DB10 of the function latch is the fastlock mode bit. When fastlock is enabled, this bit determines the fastlock mode to be used. If the fastlock mode bit is 0, then Fastlock Mode 1 is selected, and if the fastlock mode bit is 1, then Fastlock Mode 2 is selected.
Counter Reset
DB2 (F1) is the counter reset bit. When this bit is set to 1, the R counter and the N counter are reset. For normal operation, set this bit to 0. Upon powering up, the F1 bit needs to be disabled (set to 0). Then, the N counter resumes counting in close alignment with the R counter (the maximum error is one prescaler cycle).
Fastlock Mode 1
In this mode, the charge pump current is switched to the contents of Current Setting 2. The device enters fastlock by having a 1 written to the CP gain bit in the N counter latch. The device exits fastlock by having a 0 written to the CP gain bit in the AB counter latch.
Power-Down
DB3 (PD1) and DB21 (PD2) provide programmable powerdown modes. These bits are enabled by the CE pin. When the CE pin is low, the device is immediately disabled regardless of the states of the PD2, PD1 bits. In the programmed asynchronous power-down, the device powers down immediately after latching a 1 into Bit PD1, with the condition that Bit PD2 has been loaded with a 0. In the programmed synchronous power-down, the device power-down is gated by the charge pump to prevent unwanted frequency jumps. Once the power-down is enabled by writing a 1 into Bit PD1 (on condition that a 1 has also been loaded to Bit PD2), then the device enters power-down on the occurrence of the next charge pump event. When a power-down is activated (either in synchronous or asynchronous mode, including a CE pin activated powerdown), the following events occur: All active dc current paths are removed. The R, N, and timeout counters are forced to their load state conditions. The charge pump is forced into three-state mode. The digital lock detect circuitry is reset. The RFIN input is debiased. The reference input buffer circuitry is disabled. The input register remains active and capable of loading and latching data.
Fastlock Mode 2
In this mode, the charge pump current is switched to the contents of Current Setting 2. The device enters fastlock by having a 1 written to the CP gain bit in the N counter latch. The device exits fastlock under the control of the timer counter. After the timeout period determined by the value in TC4 to TC1, the CP gain bit in the N counter latch is automatically reset to 0 and the device reverts to normal mode instead of fastlock. See Figure 18 for the timeout periods.
MUXOUT Control
The on-chip multiplexer is controlled by M3, M2, and M1 on the ADF4002. Figure 18 shows the truth table.
Rev. B | Page 15 of 20
ADF4002
Charge Pump Currents
CPI3, CPI2, and CPI1 program Current Setting 1 for the charge pump. CPI6, CPI5, and CPI4 program Current Setting 2 for the charge pump. See Figure 18 for the truth table. The function latch contents are loaded.
Data Sheet
When the initialization latch is loaded, the following occurs:
PD Polarity
This bit sets the phase detector polarity bit (see Figure 18).
CP Three-State
This bit controls the CP output pin. Setting the bit high puts the CP output into three-state. With the bit set low, the CP output is enabled.
An internal pulse resets the R, N, and timeout counters to load state conditions and three-states the charge pump. Note that the prescaler band gap reference and the oscillator input buffer are unaffected by the internal reset pulse, allowing close phase alignment when counting resumes. Latching the first N counter data after the initialization word activates the same internal reset pulse. Successive N loads do not trigger the internal reset pulse unless there is another initialization. Apply VDD. Bring CE low to put the device into power-down. This is an asynchronous power-down because it happens immediately. Program the function latch (10). Program the R counter latch (00). Program the N counter latch (01). Bring CE high to take the device out of power-down. The R and N counters resume counting in close alignment. Note that after CE goes high, a duration of 1 s can be required for the prescaler band gap voltage and oscillator input buffer bias to reach steady state.
INITIALIZATION LATCH
The initialization latch is programmed when C2, C1 = 1, 1. This is essentially the same as the function latch (programmed when C2, C1 = 1, 0). However, when the initialization latch is programmed there is an additional internal reset pulse applied to the R and N counters. This pulse ensures that the N counter is at load point when the N counter data is latched and the device begins counting in close phase alignment. If the latch is programmed for synchronous power-down (CE pin is high; PD1 bit is high; and PD2 bit is low), the internal pulse also triggers this power-down. The prescaler reference and the oscillator input buffer are unaffected by the internal reset pulse, thereby maintaining close phase alignment when counting resumes. When the first N counter data is latched after initialization, the internal reset pulse is reactivated. However, successive AB counter loads after this do not trigger the internal reset pulse.
CE Pin Method
1. 2. 3. 4. 5. 6.
CE can be used to power the device up and down to check for channel activity. The input register does not need to be reprogrammed each time the device is disabled and enabled, as long as it has been programmed at least once after VDD was initially applied.
This sequence provides the same close alignment as the initialization method. It offers direct control over the internal reset. Note that counter reset holds the counters at load point and three-states the charge pump, but does not trigger synchronous power-down.
Rev. B | Page 16 of 20
ADF4002
PFD
As the ADF4002 permits both R and N counters to be programmed to 1, the part can effectively be used as a standalone PFD and charge pump. This is particularly useful in either a clock cleaning application or a high performance LO. Additionally, the very low normalized phase noise floor (222 dBc/Hz) enables very low in-band phase noise levels. It is possible to operate the PFD up to a maximum frequency of 104 MHz. In Figure 21, the reference frequency equals the PFD; therefore, R = 1. The charge pump output integrates into a stable control voltage for the VCXO, and the output from the VCXO is divided down to the desired PFD frequency using an external divider.
VDD 7
AVDD
VP 100pF
RFOUT
15
DVDD
16
CE VP
2 1
LOOP FILTER
VCC
REFIN
REFIN
RSET
18
18
ADF4002
CPGND AGND DGND
10k 100pF
RFINA RFINB 9
6 5
100pF DECOUPLING CAPACITORS AND INTERFACE SIGNALS HAVE BEEN OMITTED FROM THE DIAGRAM IN THE INTERESTS OF GREATER CLARITY.
INTERFACING
The ADF4002 has a simple SPI-compatible serial interface for writing to the device. CLK, DATA, and LE control the data transfer. When the latch enable (Pin LE) goes high, the 24 bits that have been clocked into the input register on each rising edge of CLK are transferred to the appropriate latch. For more information, see Figure 2 for the timing diagram and Table 6 for the latch truth table. The maximum allowable serial clock rate is 20 MHz. This means that the maximum update rate possible for the device is 833 kHz, or one update every 1.2 s. This is certainly more than adequate for systems that have typical lock times in hundreds of microseconds.
AIN
HC-ADC-EVALA-SC
USB
Rev. B | Page 17 of 20
06052-035
ADF4002
ADuC812 Interface
Figure 22 shows the interface between the ADF4002 and the ADuC812 MicroConverter. Because the ADuC812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. The MicroConverter is set up for SPI master mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF4002 needs a 24-bit word. This is accomplished by writing three 8-bit bytes from the MicroConverter to the device. When the third byte has been written, bring the LE input high to complete the transfer. On first applying power to the ADF4002, it needs four writes (one each to the initialization latch, function latch, R counter latch, and N counter latch) for the output to become active. I/O port lines on the ADuC812 are also used to control powerdown (CE input) and to detect lock (MUXOUT configured as lock detect and polled by the port input). When operating in the SPI master mode, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed is 166 kHz.
SCLOCK MOSI CLK DATA
Data Sheet
interrupt is generated. Set up the word length for eight bits and use three memory locations for each 24-bit word. To program each 24-bit latch, store the three 8-bit bytes, enable the autobuffered mode, and then write to the transmit register of the DSP. This last operation initiates the autobuffer transfer.
SCLK DT CLK DATA
ADSP21xx
TFS LE
ADF4002
CE MUXOUT (LOCK DETECT)
06052-020
I/O FLAGS
ADuC812
LE I/O PORTS
ADF4002
CE MUXOUT (LOCK DETECT)
06052-019
ADSP21xx Interface
Figure 23 shows the interface between the ADF4002 and the ADSP21xx digital signal processor. The ADF4002 needs a 24-bit serial word for each latch write. The easiest way to accomplish this using the ADSP21xx family is to use the autobuffered transmit mode of operation with alternate framing. This provides a means for transmitting an entire block of serial data before an
Rev. B | Page 18 of 20
ADF4002
6.40 BSC
PIN 1 0.15 0.05 0.65 BSC 0.30 0.19 COPLANARITY 0.10 1.20 MAX
0.20 0.09
SEATING PLANE
8 0
Figure 24. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters
0.60 MAX
15
16
20 1
PIN 1 INDICATOR
2.25 2.10 SQ 1.95
5
PIN 1 INDICATOR
3.75 BCS SQ
0.50 BSC
EXPOSED PAD
(BOTTOM VIEW)
11
10
0.25 MIN
12 MAX
Figure 25. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm 4 mm Body, Very Thin Quad (CP-20-1) Dimensions shown in millimeters
ORDERING GUIDE
Model 1 ADF4002BRUZ ADF4002BRUZ-RL ADF4002BRUZ-RL7 ADF4002BCPZ ADF4002BCPZ-RL ADF4002BCPZ-RL7 EVAL-ADF4002EBZ1 EVAL-ADF411XEBZ1
1
Temperature Range 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C 40C to +85C
Package Description 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ 20-Lead LFCSP_VQ Evaluation Board Evaluation Board
012508-B
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
Rev. B | Page 19 of 20
ADF4002 NOTES
Data Sheet
20062011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06052-0-9/11(B)
Rev. B | Page 20 of 20