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ListOf Experment - Final - 2024

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School of Electrical, Electronics & Communication Engineering (SEEC)

Department of Electronics & Communication Engineering


List of Experiments
Course Code: ECE2131/VDT2131 Course Name: Digital Electronics Lab

Academic Session: July-Nov 2024

List of Experiments
Exp. Experiments
No.
1. Study and Implementation of Logic Gates ……………………….………….
i) Verification of truth table for basic logic gates (AND, OR, NOT, NAND, NOR , XOR)
ii) Study of Universality of NAND and NOR gates and realization of basic gates
2. Study of basic arithmetic circuits
i) Design and study of Half adder/ Half Subtractor
ii) Design and study of Full adder/ Full Subtractor
3. Design and implementation of combinational circuit using NAND and NOR
gates……………………………………………………………………………
i) Design, build and test simple combinational circuits using logic gates like NAND and
NOR ( Software)
4. Code converters Circuits……………………………………………………
i) Design of 4-bit Binary to Gray Code converter
ii) Design of BCD to Excess-3 Code converter
iii) Design of BCD to seven segments decoder
5. Magnitude Comparator and Parity Checker/Generator (Odd/even parity)……..
i) Study and implementation of 2-bit magnitude comparator
ii) Design and study of 4-bit magnitude comparator using IC 7485
iii) Design and implementation of Parity Checker and Generator (for Odd/even parity)
6. Multiplexers ……………………………………………...
i) Implement 4:1 multiplexer using IC 74153.
ii) Implement f = ∑ m (0, 3, 5, 7, 8, 10, 14) using i) 8:1 MUX
7 Demultiplxer…….
i) Design a 1:4 De-multiplexer using basic gates
ii) Design a 1:8 De-multiplexer using IC.
8. Encoders and Decoders…………………………………………………………
i) Design and implement 2 to 4 decoder using basic gates
ii) Design and implement 2 to 4 decoder with enable input using only NAND gates
9. Basics of Flip-Flops…………………………………………………………
i) SR Flip-flop using NAND gates
ii) JK Flip-Flop using NAND gates
iii) T-Flip Flop using NAND gates
10. Study of Flip-Flop ICs
i) Study of IC 7474: Positive edge triggered dual D flip-flops with preset and clear
ii) Study of 74LS73 A: Negative edge triggered dual JK Flip-flops with clear
11. Counters…………………………………………………………………………
i) Implement Synchronous 4-bit up counter using IC 7473
ii) Design 4 bit Ring Counter
iii) Design Johnson Counter
12. Shift Registers …………………
i) Design SISO, SIPO using D Flip-flop,
ii) Design PISO and PIPO register using D Flipflop.
13. Finite State Machine…………………………………………………………….
i) Design a sequence detector which will detect an overlapping sequence 101 from an input
sequence.
14. Asynchronous Circuit design……..
i) Design an fundamental mode asynchronous sequential circuit with two inputs X and Y
and one output Z. Whenever Y is „1‟, input X is transferred to Z. Whenever Y is „0‟,
output does not change for any change in X.
15. Implement TTL logic for NAND and NOR Gate.

Course Coordinator Lab In-charge HoD

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