Chapter 11. Input-Output Organization (11.1, 11.2, 11.4, 11.

6)

Interface consists of logic circuits and registers. Two types of interfaces are:

● Memory interface

● I/O interface (depends on the nature of I/O device)

Memory interface contains circuit to perform read and write operations and decodes address in
memory. I/O interface contains I/O ports/registers so that CPU and memory can communicate
with the device.
System bus / Memory bus(Address bus, data bus, control bus) is used for communication
between CPU & memory.
I/O bus (Address bus, data bus, control bus) is used for communication between CPU and I/O
devices.
I/O interface circuit functions:

● Data conversion: Conversion between digital and analog signals, conversion between
serial and parallel data formats.
 ● Synchronisation: matching operating speeds of CPU and peripherals.

● Device selection: selection of I/O device by CPU in a queue manner.

To communicate with a particular device, CPU places a device address on address bus (Bus/
wire/line are used interchangeably). Each interface has an address decoder. CPU provides a
function code in control line. This function code is called I/O command.

I/O BUS versus Memory BUS

Three ways , CPU can communicate with memory and I/O :
(1) use two separate buses, one to communicate with memory (System bus) and the
other with I/O interfaces (IO bus)
The computer has independent sets of data, address, and control buses, one for
accessing memory and the other for I/O. This is done in computers that provide a separate
IO processor (lOP) in addition to the CPU. The memory communicates with both the
CPU and the lOP through a memory bus. The lOP communicates also with the input and
output devices through a separate I/O bus with its own address, data and control lines.
The purpose of the lOP is to provide an independent pathway for the transfer of
information between external devices and internal memory. The I/O processor is
sometimes called a data channel.
 (2) Use one common bus (address bus, data bus) for memory and I/O but separate
control lines for each (also called Isolated I/O or I/O mapped I/O)

If memory and I/O share address and data bus, there are two ways to distinguish
between them.

● In isolated I/O, common address and data bus lines are used to address both
memory and I/O devices. Separate read/write control lines enable either
memory or an I/O device, but never both, to accept the address. This scheme
allows an I/O device and memory to use same address, since only one of them
will be activated during any given clock cycle. A given address can refer to a
memory cell at one time and to an I/O device at another.
Systems using isolated I/O and systems with separate memory and I/O buses
have distinct I/O instructions that activate the I/O read or write control lines.
Memory reference instructions activate the memory read or write control lines.
(3) Use one common bus for memory and I/O with commoncontrol lines for both (also
called memory-mapped I/O)

There is only one address space, and it is divided between memory cells and I/O
device registers. Any given address is wired to either to a memory cell or an I/O
device register.
In memory-mapped I/O systems, there are no distinct I/O instructions. The
CPU does not distinguish between memory access and I/O operations. The only
difference between them is the address. Hence, we can use load and store
instructions to access the registers in I/O devices on a load-store architecture.
We can use almost any instruction (move, add, sub, etc.) to perform I/O on a
memory-to-memory or register-memory computer.
The main difference between memory mapped IO and Isolated I/O (also called I/O mapped IO)
is that the memory mapped IO uses the same address space for both memory and IO device
while the Isolated I/O uses two separate address spaces for memory and IO device.

Modes of transfer
Data transfer to and from peripherals may be handled in one of the 3 possible ways:
● Programmed I/O (studied in chapter 5)

● Interrupt initiated I/O(studied in chapter 5)

● DMA

Programmed control transfer (Programmed I/O)

Studied in Chapter 5

OUT instruction states that OUTR<-AC when FGO=1.

INP instruction states that AC<-INPR when FGI=1.

As you can see in the following instruction codes, CPU keeps checking the flag bits (FGI and
FGO). Till FGI=0, instructions at locations 20 and 21 repeats and in the same way, till FGO=0,
instructions at locations 50 and 51 repeats. When these flag bits are set(=1) , INP and OUT are
executed i.e. character transfer takes place. This method is called programmed control
transfer.

20 SKI
21 BUN 20
22 INP
50 SKO
51 BUN 50
52 OUT

Disadvantage of this technique: Due to mismatch in data transfer speed between CPU and I/O
device, much of CPU time is wasted in checking status of flags.

Fig 11.10 Data transfer from I/O device to CPU

Eg. Keyboard to CPU (AC<-INPR<-keyboard)

The device transfers bytes of data one at a time as they are available.

● When a byte of data is available, the device places it in the IO bus and enables its data
valid line.
● The interface accepts the byte into its data register and enables the data accepted line.

● The interface sets a bit in the status register that we will refer to as an F or "flag" bit.

● The device can now disable the data valid line, but it will not transfer another byte until
the data accepted line is disabled by the interface.

A program is written for the computer to check the flag in the status register to determine if a
byte has been placed in the data register by the IO device. This is done by reading the status
register into a CPU register and checking the value of the flag bit. If the flag is equal to 1, the
CPU reads the data from the data register. The flag bit is then cleared to 0 by either the CPU
or the interface, depending on how the interface circuits are designed. Once the flag is cleared,
the interface disables the data accepted line and the device can then transfer the next data byte.

Eg. (book)

1 sec=106 microseconds

Let us assume that a computer executes 2 instructions (read the status register and check the flag
in 1 microseconds.

Assume that100 bytes can be transferred from input device in 106 microsec. Then 1 byte will be
transferred in 106/100=10000 microsec. So CPU checks the flag 10000 times between each
transfer thus wasting time in checking rather than wasting time in checking.
Interrupt initiated I/O
Example
MOV AH, 01H
INT 21H
Returns the input character in AL register.
By calling INT 21h with a subfunction number in the AH processor register and
other parameters in other registers, various services can be invoked. These
include handling keyboard input, video output, disk file access, program
execution, memory allocation, and various other activities.

Both the methods programmed I/O and Interrupt-driven I/O require the active
intervention of the processor to transfer data between memory and the I/O
module, and any data transfer must transverse a path through the processor.
Thus both these forms of I/O suffer from two inherent drawbacks.
● The I/O transfer rate is limited by the speed with which the processor can test
and service a device.
● The processor is tied up in managing an I/O transfer; a number of instructions
must be executed for each I/O transfer.
DMA (Direct Memory Access)

DMA is a hardware solution that allows blocks of data to be transferred between memory and an
I/O device with no involvement of the CPU. The size of the block transferred may vary, but in
any case DMA reduces the number of interrupts generated by at least an order of magnitude, and
reduces the amount of work the ISR must perform.

When a DMA transfer occurs, the CPU relinquishes access to memory, and the DMA
controller associated with the I/O device becomes the bus master.

DMA controller (DMAC) communicates with CPU via data bus and control bus (RD and WR
signals). Registers in DMAC are selected by CPU via address bus by enabling DS( DMA select)
and RS(register select). RD and WR of DMAC are bi-directional.

DMA controller communicates with memory via address bus, RD and WR signals.

When BG(Bus Grant)=0, RD and WR(of DMA controller) are input lines i.e. CPU can
communicate with DMA register through data bus to read from or write to DMA register.

When BG=1, RD and WR (of DMA controller) are output lines i.e. CPU has relinquished the
buses and DMA can communicate directly with memory by specifying address in address bus
and activating RD/ WR signal.

Fig. 11.18 DMA transfer in a computer system

a) I/O device sends DMA request to DMA controller.

b) To initiate a transfer, the DMA controller issues a bus request BR to CPU.
c) When the CPU is ready to relinquish the memory buses, it responds with a bus grant
(BG).
d) DMA controller puts address register value into address bus, initiates RD / WR signal
and sends ACK (acknowledgement) to I/O device.
e) When I/O receives ACK, it puts word in data bus (for WR=1) or receives word from data
bus (for RD=1).
f) DMA controller controls read /write operations and supplies address for memory.
g) I/O communicates with memory through data bus for direct transfer.