l /0 Bus and Interface Modules

I/O Bus and Interface Modules: The I/O bus connects the processor to multiple peripheral
devices. It consists of data lines, address lines, and control lines. Each peripheral device is associated
with an interface unit. The interface unit decodes the address and control signals received from the
I/O bus, interprets them for the peripheral device, and provides signals for the peripheral controller.
It also synchronizes the data flow and supervises the transfer between the peripheral and processor.

Addressing Peripheral Devices: To communicate with a specific peripheral device, the processor
places the device's address on the address lines of the I/O bus. Each interface attached to the I/O
bus contains an address decoder that monitors the address lines. When the interface detects its own
address, it activates the path between the bus lines and the device it controls. Peripheral devices
whose addresses do not match the address on the bus are disabled by their respective interfaces.

Function Codes and Commands: Simultaneously with providing the address on the address lines,
the processor sends a function code on the control lines. This function code, also known as an I/O
command, instructs the selected interface to execute a specific action. There are four types of
commands: control commands, status commands, data output commands, and data input
commands.

Control Commands: A control command activates the peripheral device and instructs it on what
action to perform. For example, a magnetic tape unit may be instructed to rewind the tape or start
moving it in a specific direction.

Status Commands: Status commands are used to check various status conditions in the interface
and peripheral device. For instance, the computer may want to verify the status of the peripheral
before initiating a data transfer.

Data Output Commands: Data output commands cause the interface to transfer data from the
bus into one of its registers. For example, when storing data on a tape unit, the processor issues a
 data output command, and the interface transfers the data from the bus to its buffer register before
communicating with the tape controller.

Data Input Commands: Conversely, data input commands instruct the interface to receive data
from the peripheral device and place it in its buffer register. The processor can then retrieve the
data from the buffer register for further processing.

Isolated versus Memory-Mapped I/0

Isolated I/O:

1. Addressing: In isolated I/O, separate read and write control lines are used to distinguish
between memory transfers and I/O transfers.
2. Address Space: I/O addresses are isolated from memory addresses, ensuring that memory
address values are not affected by I/O address assignments.
3. Distinct Instructions: The CPU has specific input and output instructions associated with
addresses of interface registers.
4. Control Signals: When performing I/O operations, the CPU enables the I/O read or write
control line, indicating that the address on the bus is for an interface register, not for
memory.
5. Addressing Method: Addresses for interface registers are distinct from memory addresses,
allowing separate address spaces for I/O and memory.

Memory-Mapped I/O:

1. Addressing: Memory-mapped I/O uses the same address space for both memory and I/O
operations.
2. Control Signals: There are no specific input or output instructions. Memory-type
instructions are used to access I/O data.
3. Shared Address Space: Interface registers are treated as part of the memory system,
sharing the same address space with memory words.
4. Instruction Set: All instructions that refer to memory are also used for I/O operations,
enabling the use of load and store instructions for I/O data transfers.
5. Availability of Instructions: Since memory-reference instructions are more common than
specific I/O instructions, memory-mapped I/O ensures that all memory instructions can also
be used for I/O operations.

Difference:

 Addressing Method: Isolated I/O uses separate address spaces for memory and I/O,
while memory-mapped I/O shares the same address space for both.
 Control Signals: Isolated I/O uses distinct read and write control lines for memory
and I/O operations, while memory-mapped I/O uses memory control lines for both.
 Instruction Set: Isolated I/O has specific input and output instructions, while
memory-mapped I/O uses memory instructions for I/O operations.
  Address Space Management: Isolated I/O provides dedicated address spaces for
memory and I/O, ensuring no overlap, while memory-mapped I/O requires careful
management to avoid conflicts between memory and I/O addresses.

Example of I/O Interface

1. Components of the Interface:

 Data Registers (Ports A and B): These registers serve as temporary storage for data being
transferred to or from the connected I/O devices. They communicate directly with the CPU
via the data bus.
 Control Register: This register receives control information from the CPU, allowing the
interface and the connected I/O device to be configured into different operating modes. For
example, it can define whether Port A is an input or output port.
 Status Register: This register stores status information and records any errors that may
occur during data transfer. Status bits indicate various conditions such as new data reception
or parity errors.
  Bus Buffers and Timing/Control Circuits: These components manage the flow of data
between the CPU, data registers, control register, status register, and the connected I/O
devices.
2. Data Transfer:
 Data to and from the I/O device can be transferred into either Port A or Port B, depending
on the configuration.
 The CPU communicates with the interface unit through the bidirectional data bus. The
address bus selects the interface unit by activating the chip select (CS) input.
 The two register select inputs (RS1 and RS0) determine which of the four registers in the
interface is accessed by the CPU.
3. Control and Status Monitoring:
 Control commands from the CPU are loaded into the control register, allowing the interface
and the connected I/O device to perform various operations.
 Status information and error detection are managed through the status register, which
indicates conditions such as data reception and parity errors.
 The CPU reads status information from the status register and sends control commands by
writing to the control register via the data bus.
4. Address Decoding:
 External circuitry, usually a decoder, detects the address assigned to the interface registers,
enabling the chip select input when the interface is selected by the address bus.
 The two register select inputs are connected to the two least significant lines of the address
bus, determining which register is accessed based on the address provided.

Asynchronous Serial Transfer

Asynchronous serial transfer is a method of transmitting data between two units where each bit of
the message is sent one at a time in sequence. This method requires only one pair of conductors or
one conductor and a common ground, making it less expensive compared to parallel transmission,
which requires multiple conductor paths.

In asynchronous serial transmission, special bits are inserted at both ends of the character code to
indicate the beginning and end of each character. The character consists of three parts: a start bit,
the character bits, and stop bits. When no characters are being transmitted, the line remains in the
1-state. The start bit, always a 0, indicates the beginning of a character, followed by the character
bits, and then one or two stop bits, always in the 1-state, to signify the end of the character and
return to the idle state.

The receiver detects the start bit when the line changes from 1 to 0 and examines the line at proper
bit times using a clock. After receiving the character bits, the receiver waits for the line to return to
the 1-state for at least one or two bit times to detect the stop bit. This ensures that both the
transmitter and receiver can resynchronize. The line remains in the 1-state until another character is
transmitted, providing a stop time to prevent the immediate transmission of a new character.

For example, in a terminal with a transfer rate of 10 characters per second, each character takes 0.1
seconds for transfer, resulting in a bit time of 9.09 milliseconds. With an 11-bit format (start bit, 8
information bits, and 1 or 2 stop bits), the transfer rate is 110 baud.
An asynchronous communication interface or universal asynchronous receiver transmitter (UART) is
often used to facilitate asynchronous serial transfer between devices. These integrated circuits are
specifically designed to handle the serial communication protocol, enabling the exchange of data
between computers and interactive terminals, such as keyboards and printers.

synchronous Communication Interface

 Transmitter Operation:

1. Data Transmission Preparation: The CPU checks the status register to determine if
the transmitter register is empty. If empty, it transfers a character to the transmitter
register.
2. Start Bit Generation: The interface sets the first bit in the transmitter shift register to
0 to generate a start bit.
3. Character Transmission: The character is transferred in parallel from the transmitter
register to the shift register, followed by the appropriate number of stop bits.
4. Serial Transmission: The character is transmitted one bit at a time by shifting the
data in the shift register at the specified baud rate.
5. Double Buffering: As soon as transmission starts, the CPU can load a new character
into the transmitter register, allowing for continuous transmission.

Receiver Operation:

1. Detection of Start Bit: The receiver control monitors the receive-data line for a
transition from 1 to 0, indicating the start bit.
2. Character Reception: Once a start bit is detected, the incoming bits of the character
are shifted into the shift register at the prescribed baud rate.
3. Parity and Stop Bit Check: After receiving the data bits, the interface checks for
parity and stop bits.
4. Data Transfer: The character without start and stop bits is transferred in parallel
from the shift register to the receiver register.
5. Status Flag Setting: The flag in the status register is set to indicate that the receiver
register is full.
6. Data Retrieval: The CPU reads the status register and checks the flag to retrieve the
data from the receiver register.

Error Handling:

 Parity Error: Occurs if the number of 1's in the received data does not match
the correct parity.
 Framing Error: Occurs if the correct number of stop bits is not detected at the
end of the received character.
 Overrun Error: Occurs if the CPU fails to read the character from the receiver
register before the next one becomes available in the shift register, resulting
in a loss of characters in the received data stream

EXAMPLE OF PROGGRAMMED I/O

The example of programmed I/O (Input/Output) described above illustrates the
 process of transferring data from an I/O device to memory using the CPU as an
intermediary. Here's a breakdown of the example:

1. Initial Setup:
 In programmed I/O, the I/O device (e.g., an input device) doesn't have direct
access to memory.
 Transferring data from the I/O device to memory involves several CPU
instructions, including input and store instructions.
2. Data Transfer Procedure:
 When data is available, the I/O device transfers it one byte at a time to the I/O
bus and enables its data valid line.
 The interface accepts the byte into its data register and enables the data
accepted line.
 A flag bit in the status register is set by the interface to indicate that data is
ready.
 After accepting the byte, the I/O device can disable the data valid line, but it
won't transfer another byte until the data accepted line is disabled by the
interface, following a handshaking procedure.
3. CPU Program:
 A program is written for the CPU to check the flag in the status register to
determine if a byte is available in the data register.
 This involves reading the status register into a CPU register and checking the
value of the flag bit.
 If the flag is set, indicating data availability, the CPU reads the data from the
data register.
 After reading the data, the flag bit is cleared (set to 0) by either the CPU or the
interface, depending on the interface design.
 Once the flag is cleared, the interface disables the data accepted line, allowing
the I/O device to transfer the next data byte.
4. Flowchart and Instructions:
 A flowchart illustrates the program flow for the CPU, assuming the device
sends a sequence of bytes to be stored in memory.
 Each byte transfer requires three instructions: read the status register, check
the flag status, and read the data register.
 Once data is read, it's transferred to memory using a store instruction.
5. Efficiency Considerations:
 Programmed I/O is suitable for small, low-speed computers or systems
continuously monitoring a device.
 However, it's inefficient when the CPU must frequently check the flag for data
availability, especially if the I/O device's transfer rate is slow compared to the
CPU's processing speed.
 Priority Interrupt

1. Initiation of Data Transfer: In the context of data transfer between the CPU and an
I/O device, the CPU initiates the transfer, but it can only proceed if the device is ready
to communicate. This readiness is signaled through an interrupt request.
2. Handling Interrupt Requests: When an interrupt request occurs, the CPU responds
by storing the return address from the program counter (PC) into a memory stack. It
then branches to a service routine dedicated to processing the interrupt.
3. Priority Determination: In systems with multiple interrupt sources, the priority
interrupt system plays a crucial role in determining which interrupt to service first,
especially when multiple requests arrive simultaneously. This prioritization ensures
that critical tasks are handled promptly.
4. Priority Levels: Devices and interrupt sources are assigned different priority levels
based on the urgency and importance of their tasks. For example, high-speed
devices like magnetic disks may have higher priority than slower devices like
keyboards.
5. Software vs. Hardware Implementation:
 Software Method (Polling): In this approach, a polling procedure is
employed to identify the highest-priority source. The CPU sequentially checks
each interrupt source's status to determine which one requires immediate
attention. However, if there are numerous interrupts, the polling process can
become time-consuming and may exceed the available time to service the
devices.
 Hardware Method: A hardware priority-interrupt unit serves as the manager
in the interrupt system. It receives interrupt requests from various sources,
determines the highest-priority request, and issues an interrupt request to the
CPU accordingly. Each interrupt source has its own interrupt vector, enabling
direct access to its dedicated service routine without the need for polling. This
hardware-based approach significantly speeds up the interrupt handling
process.
6. Hardware Priority Function: The hardware priority function can be implemented
using either serial or parallel connection of interrupt lines. In the serial connection
(daisy chaining method), interrupt signals are passed from one device to another in a
sequential manner until the highest-priority interrupt is identified.
 DAISY CHAIN INTERRUPT

1. Serial Connection of Devices:

 In the daisy-chaining method, all devices that request interrupts are
connected in a serial manner.
 The device with the highest priority is placed first in the chain, followed by
devices of decreasing priority, with the lowest priority device placed last.
2. Interrupt Line Logic:
 The interrupt request line is common to all devices and forms a wired logic
connection.
 If any device has its interrupt signal in the low-level state, indicating an
interrupt request, the interrupt line goes to the low-level state and enables the
interrupt input in the CPU.
 Conversely, when no interrupts are pending, the interrupt line stays in the
high-level state, and no interrupts are recognized by the CPU. This logic
operation is equivalent to a negative logic OR operation.
3. Interrupt Handling Process:
 When a device requests an interrupt, the CPU responds by enabling the
interrupt acknowledge line.
 The acknowledge signal is received by the first device in the chain at its
Priority In (PI) input.
 If the first device (Device 1) is not requesting an interrupt, it allows the
acknowledge signal to pass to the next device through its Priority Out (PO)
output.
 If Device 1 has a pending interrupt, it blocks the acknowledge signal from
reaching the next device by placing a 0 in its PO output.
 Device 1 then proceeds to insert its interrupt vector address (VAD) into the
data bus for the CPU to use during the interrupt cycle.
  Similarly, subsequent devices in the chain behave based on their interrupt
request status and priority levels, allowing the highest priority device with a
pending interrupt to have its vector address placed on the data bus.
4. Internal Logic within Devices:
 Each device in the daisy chain includes internal logic to handle interrupts.
 This logic involves setting a Request For Interrupt (RF) flip-flop when the
device wants to interrupt the CPU.
 Depending on the state of the RF flip-flop and the Priority In (PI) input, each
device determines whether to allow the acknowledge signal to pass through
or to block it.
 The device's RF flip-flop is reset after a delay to ensure that the CPU has
received the interrupt vector address.

Parallel Priority Interrupt

1. Parallel Priority Interrupt:
 In the parallel priority interrupt method, a register is used to receive interrupt
signals from each device separately.
 Priority is established based on the position of the bits in the register, with
higher-priority devices setting their corresponding bits before lower-priority
devices.
 This method allows for efficient determination of which interrupt source
should be serviced first based on priority levels.
2. Mask Register:
 Alongside the interrupt register, there may be a mask register included in the
circuit.
 The mask register allows control over the status of each interrupt request by
enabling or disabling individual interrupt sources.
 It can be programmed to disable lower-priority interrupts while a higher-
priority device is being serviced, or to allow a high-priority device to interrupt
even if a lower-priority device is being serviced.
3. Priority Encoder:
 The priority encoder is a crucial component of the parallel priority interrupt
system.
 It receives inputs from both the interrupt register and the mask register.
 The encoder generates outputs based on the priority levels of the interrupt
requests and the masking settings.
 The truth table of the priority encoder defines the logic for determining which
interrupt source has the highest priority and should be serviced first.
 The output of the priority encoder is used to form part of the interrupt vector
address for each interrupt source, allowing the CPU to identify the source of
the interrupt accurately.
4. Interrupt Handling Process:
 When an interrupt occurs, the priority encoder identifies the highest-priority
interrupt source based on the settings of the interrupt and mask registers.
 The interrupt status flip-flop (IST) is set when an interrupt that is not masked
occurs, indicating that an interrupt request needs to be serviced.
 The interrupt enable flip-flop (IEN) provides overall control over the interrupt
system and can be set or cleared by the program.
  The output of the priority encoder, along with the interrupt status and enable
signals, generates a common interrupt signal for the CPU, prompting it to
respond to the interrupt request.

Interrupt Cycle

1. Interrupt Enable Flip-Flop (IEN):

 The IEN flip-flop can be set or cleared by program instructions.
 When cleared (set to 0), the CPU ignores interrupt requests coming from the
interrupt status flip-flop (IST).
 When set (set to 1), the CPU acknowledges interrupt requests and enters the
interrupt cycle.
2. Checking IEN and IST:
 At the end of each instruction cycle, the CPU checks the status of both the IEN
flip-flop and the interrupt signal from IST.
 If either IEN or IST is equal to 0, indicating that interrupts are disabled or no
interrupt request is pending, the CPU continues with the next instruction in
the program.
 If both IEN and IST are equal to 1, indicating that interrupts are enabled and
an interrupt request is pending, the CPU proceeds to the interrupt cycle.
3. Interrupt Cycle Sequence:
 Stack Pointer Adjustment: The stack pointer (SP) is decremented by 1 to
allocate space for storing the return address from the interrupted program.
 Saving Return Address: The current program counter (PC) value, which
points to the next instruction in the interrupted program, is pushed onto the
stack (M[SP] <- PC).
 Interrupt Acknowledgement: The CPU acknowledges the interrupt by
enabling the interrupt acknowledge line (INTACK).
 Transfer of Vector Address: The priority interrupt unit responds by placing a
unique interrupt vector onto the CPU data bus.
 Updating Interrupt Enable: The CPU transfers the interrupt vector address
into PC and clears the IEN flip-flop to disable further interrupts.
 Fetch Next Instruction: With the new vector address loaded into the PC, the
CPU proceeds to fetch the instruction located at that address, initiating the
execution of the interrupt service routine.
 Initial Operations:

1. Clear Lower-Level Mask Register Bits:

 Purpose: Prevents lower-priority interrupt sources from being enabled.
 Explanation: Lower-level mask register bits, including the bit corresponding to
the interrupt source, are cleared to ensure that these interrupts are
temporarily disabled during the execution of the current interrupt service
routine.
2. Clear Interrupt Status Bit (IST):
 Purpose: Prepares for the detection of subsequent interrupt requests.
 Explanation: The interrupt status bit (IST) is cleared to reset the indication that
an interrupt has occurred, allowing it to be set again when a higher-priority
interrupt request is received.
3. Save Contents of Processor Registers:
 Purpose: Preserves the current state of processor registers for later restoration.
 Explanation: The contents of processor registers are saved in memory or on
the stack to ensure that the interrupted program can resume execution with
its original register values once the interrupt service routine is completed.
4. Set Interrupt Enable Bit (IEN):
 Purpose: Allows other (higher-priority) interrupts to occur while servicing the
current interrupt.
 Explanation: The interrupt enable bit (IEN) is set to enable the detection and
handling of other interrupt requests, particularly those with higher priority,
after the current interrupt is serviced.
5. Proceed with Service Routine:
  Purpose: Executes the specific operations required to handle the interrupt.
 Explanation: With the interrupt hardware properly configured and enabled,
the CPU proceeds to execute the interrupt service routine, which typically
involves tasks specific to the interrupting device or event.

Final Operations:

1. Clear Interrupt Enable Bit (IEN):

 Purpose: Disables further interrupts to prevent interruptions during critical
final operations.
 Explanation: The IEN is cleared to prevent any additional interrupts from
occurring while the final operations of the interrupt service routine are
executed.
2. Restore Contents of Processor Registers:
 Purpose: Returns the processor registers to their original state before the
interrupt occurred.
 Explanation: The saved contents of processor registers are restored from
memory or the stack to ensure that the interrupted program can resume
execution with its original register values.
3. Clear Interrupt Register Bit and Set Lower-Level Priority Bits:
 Purpose: Prepares the system for potential future interrupts.
 Explanation: The bit in the interrupt register corresponding to the serviced
interrupt source is cleared to indicate that the interrupt has been handled.
Additionally, lower-level priority bits in the mask register, including the bit for
the interrupted source, are set to enable these interrupts again.
4. Restore Return Address into PC and Set IEN:
 Purpose: Returns control to the interrupted program and enables further
interrupts.
 Explanation: The return address stored on the stack is restored into the
program counter (PC), allowing the interrupted program to resume execution.
Subsequently, the IEN is set again to enable the detection and handling of
subsequent interrupts.

CPU-lOP Communication
1. CPU Operations:
 Send Instruction to Test IOP Path: The CPU initiates communication with
the IOP by sending an instruction to test the IOP path. This instruction serves
as a signal to the IOP to prepare for communication.
2. IOP Operations:
  Request IOP Status: Upon receiving the instruction from the CPU, the IOP
retrieves its status information and prepares to communicate it back to the
CPU.
 Transfer Status Word to Memory Location: The IOP inserts a status word
into a designated memory location. This status word contains information
about the IOP's condition and the status of connected devices, such as
overload conditions, device busy status, or readiness for data transfer.
3. CPU Response:
 Check Status Word: The CPU refers to the status word stored in memory to
determine the next course of action based on the IOP's condition. If the status
indicates that the IOP and connected devices are ready for data transfer, the
CPU proceeds accordingly.
4. Data Transfer:
 Send Instruction to Start I/O Transfer: If the status indicates that the IOP
and connected devices are ready, the CPU sends an instruction to start the I/O
transfer process. This instruction includes the memory address where the IOP
can find its program instructions.
5. Concurrent Operation:
 CPU Continues with Another Program: While the IOP is busy executing the
I/O transfer program, the CPU can continue executing other programs
concurrently. Both the CPU and the IOP access memory using Direct Memory
Access (DMA) transfers.
6. Completion and Status Reporting:
 IOP Program Termination and Interrupt Request: Once the IOP completes
the I/O transfer program, it sends an interrupt request to the CPU to notify it
of the completion.
 CPU Response to Interrupt: Upon receiving the interrupt request from the
IOP, the CPU issues an instruction to read the status from the IOP.
 Transfer Status Word to Memory Location: The IOP responds by placing its
status report, indicating the completion status of the transfer and any errors
encountered, into a specified memory location.
7. Final Status Check by CPU:
 CPU Checks Status Word: The CPU inspects the status word stored in
memory to determine whether the I/O operation was completed satisfactorily
and without errors.
 SERIAL COMMUNICATION
1. Data Communication Processor (DCP):
 A DCP is an I/O processor specialized in distributing and collecting data from
remote terminals via communication lines.
 It communicates directly with data communication networks, facilitating
efficient operation in a time-sharing environment.
2. Serial Communication with Terminals:
 Unlike traditional I/O processors that use a common bus, a DCP
communicates with each terminal through a single pair of wires.
 Data and control information are transferred serially, resulting in slower
transfer rates compared to parallel communication.
3. Terminal Connection via Telephone Lines:
 Remote terminals are connected to the DCP via telephone lines or other
communication facilities.
 Converters like data sets, acoustic couplers, or modems are used to convert
digital signals into audio tones for transmission over telephone lines and vice
versa.
4. Transmission Methods:
  Asynchronous transmission involves framing each character with start and
stop bits, whereas synchronous transmission transmits continuous messages
without start-stop bits.
 Synchronous transmission is more efficient but requires clock synchronization
between the transmitter and receiver.
5. Error Detection and Correction:
 Various methods, including parity checks, longitudinal redundancy checks
(LRC), and cyclic redundancy checks (CRC), are employed for error detection.
 Error detection protocols ensure that transmitted data is received accurately,
with mechanisms in place for retransmission if errors occur.
6. Transmission Modes:
 Data can be transmitted in simplex (one-way), half-duplex (one direction at a
time), or full-duplex (both directions simultaneously) modes.
 Full-duplex communication requires either four-wire links or frequency
division on a two-wire circuit.
7. Data Link Protocols:
 Data link control protocols facilitate orderly data transfer between
interconnected computers and terminals.
 These protocols establish and terminate connections, identify senders and
receivers, ensure error-free data transfer, and manage control functions.
8. Protocol Types:
 Protocols can be categorized as character-oriented or bit-oriented, depending
on the framing technique used for message transmission.

Character-Oriented Protocol
1. Character Set and Encoding:
 Utilizes the ASCII (American Standard Code for Information Interchange)
character set, consisting of 128 characters, including 95 graphic characters and
33 control characters.
 ASCII is a 7-bit code, with an eighth bit often used for parity. Each character
has a unique 7-bit code.
2. Control Characters:
 Control characters are used for routing data, formatting text, and managing
the layout of printed pages.
 They include communication control characters such as SYN, SOH, STX, ETX,
EOT, ACK, NAK, ENQ, ETB, and DLE.
3. SYN Character and Synchronization:
 The SYN character serves as a synchronizing agent between the transmitter
and receiver.
  It has an 8-bit code (0 0010110) chosen for its property of repeating itself only
after a full 8-bit cycle.
 Upon receiving a continuous string of bits, the receiver checks for the SYN
character to establish synchronization.
 Continuous strings of SYN characters are sent when the transmitter is idle to
maintain synchronization.
4. Message Format:
 Messages are transmitted with a defined format consisting of a header field, a
text field, and an error-checking field.
 The header begins with an SOH character and contains address and control
information.
 The text field follows, terminated by an ETX character, and may contain any
ASCII characters except control characters.
 The error-checking field typically includes a Block Check Character (BCC),
which can be a Longitudinal Redundancy Check (LRC) or a Cyclic Redundancy
Check (CRC).
5. Error Detection and Handling:
 The receiver calculates its own BCC and compares it with the transmitted BCC.
 If they match, the receiver sends a positive acknowledgment (ACK) character;
otherwise, it sends a negative acknowledgment (NAK) character, indicating the
need for retransmission.
 Retransmission is attempted several times before assuming a faulty line.
6. Synchronous Idle State:
 In the absence of meaningful information, the transmitter sends a continuous
string of SYN characters, and the receiver recognizes them as a condition for
synchronizing the line.
 Both units maintain bit and character synchronism in a synchronous idle state,
ensuring readiness for data transmission.
 Bit-Oriented Protocol
1. Independence from Character Codes:
 Bit-oriented protocols are not tied to any specific character code like ASCII.
 They allow the transmission of serial bit streams of any length without
character boundaries.
2. Frame Format:
 Messages are organized into frames, consisting of address, control,
information, and error-checking fields.
 Frame boundaries are indicated by a special flag, typically an 8-bit pattern
(01111110).
3. Examples of Bit-Oriented Protocols:
 Common examples include SDLC (Synchronous Data Link Control), HDLC
(High-Level Data Link Control), and ADCCP (Advanced Data Communication
Control Procedure).
4. Primary and Secondary Stations:
 Bit-oriented protocols assume the presence of at least one primary station
and one or more secondary stations.
 Communication occurs from the primary station to the secondary station(s) or
vice versa.
5. Frame Structure:
 Begins with a flag, followed by an address field, control field, information field,
and error-checking field.
 The frame ends with another flag, indicating the end of the frame.
6. Zero Insertion Technique:
 To prevent flags from occurring in the middle of frames, a method called zero
insertion is used.
 A '0' is inserted after every sequence of five continuous '1's, and the receiver
removes the '0' after receiving five '1's.
7. Address Field:
 Specifies the destination address (for secondary stations) or the source and
destination addresses (for primary stations).
8. Control Field:
 Comes in different formats: information transfer, supervisory, and
unnumbered.
 Information transfer format includes send and receive counts for sequenced
frames.
 Supervisory format is used for commands, acknowledgments, and error
reporting.
 Unnumbered format is for initialization, procedural errors, and control
operations.
9. Poll/Final Bit:
  Used by the primary station to poll secondary stations or indicate the final
transmitted frame.
 Determines when data transmission from a station is finished.
10. Error Detection:
 Error-checking fields, typically containing CRC sequences, are used for
detecting errors in transmission.