I B. Tech II Semester Supplementary Examinations, November - 2021
DIGITAL LOGIC DESIGN (Com. to CSE, IT) Time: 3 hours Max. Marks: 75 Answer any five Questions one Question from Each Unit All Questions Carry Equal Marks ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ UNIT-I 1. a) Convert the following to Decimal and then to octal (8M) (i) (125F)16 (ii) (10111111)2 (iii) (392)10 b) Perform the subtraction using 1’s complement and 2’s complement methods. (7M) (i) 11010 – 10000 (ii) 11010 – 1101 (iii) 100 - 110000 Or 2. a) How do you convert a gray number to binary? Generate a 4-bit gray code directly (8M) using the mirror image property? b) Find the 12-bit 1’s complement form of the following decimal numbers. (7M) (i) -97 (ii) -224 (iii) -205.75 (iv) -29.375
UNIT-II 3. a) Without reducing, implement the following expressions in AOI logic and then (8M) convert them into NAND logic and NOR logic. (i) A + BC + (A + B’C) + D (ii) A + B’C + (B + C)’ + B’C’ b) Reduce using mapping the following expression and implement the real minimal (7M) expression in Universal logic. F= m (0, 2, 4, 6, 7, 8, 10, 12, 13, 15) Or 4. a) State and prove consensus theorem? Solve the given expression using consensus (8M) theorem. (i) AB + AC + BC + BC + AB (ii) (A + B)(A + C)(B + C)(A + D)(B + D) b) Reduce the following expression to the simplest possible POS and SOP forms. (7M) F= m (6,8,13,18,19,25,27,29,31) + d (2,3,11,15,17,24,28) UNIT-III 5. a) Realize the following functions using a PROM of size 8 × 3 (8M) F1= m(0,4,7) F2= m(1,3,6) F3= m(1,2,4,6)
b) Perform the realization of full subtractor using decoder and logic gates. (7M) Or 1 of 2
|''|'|''|''|''|||'|| www.manaresults.co.in Code No: R19ES1213 R19 SET - 1
6. a) Design an arithmetic circuit that adds 2 binary digits. The circuit should have 2 (8M) outputs, one for the sum and the other for the carry. Implement the same in a PAL. b) Explain the design procedure for multiplexers and de-multiplexers and draw the (7M) logic diagram of a 4-to-1 line multiplexer with logic gates.
UNIT-IV
7. a) Draw the schematic circuit of a D flip flop with negative edge triggering using (8M) NAND gates. Give its truth table and explain its operation? b) Distinguish between combinational and sequential circuits. List some (7M) applications of sequential circuits. Or 8. a) Draw the circuit diagram of a positive edge triggered JK flip flop and explain its (8M) operation with the help of a truth table. b) Convert a D flip flop into SR flip flop and JK flip flop. (7M) UNIT-V
9. a) Design a 4 bit synchronous counter with D flip - flops and explain its working. (8M) b) What is a serial-in, serial-out shift registers? Explain with suitable diagrams. (7M)
Or 10. a) Draw the logic diagram of a 4-bit binary ripple counter using flip flops that (8M) trigger on negative edge transition? Explain the operation.
b) With suitable diagram explain an n-bit left to right shift register. (7M)
