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    Boe310 Lecture

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    Raj Gopal Mishra

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    © All Rights Reserved
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    Boe310 Lecture

    Uploaded by

    Raj Gopal Mishra
    117 views25 pages

    Original Title

    BOE310 LECTURE

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    117 views25 pages

    Boe310 Lecture

    Uploaded by

    Raj Gopal Mishra

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 25

    IMS ENGINEERING COLLEGE, GHAZIABAD

    DEPARTMENT : INFORMATION TECHNOLOGY


    Faculty Name:RAJ GOPAL Designation: Asst. Professor Contact No./Email ID: 8920889064 / raj.g
    Subject with Code: DEGITAL ELECTRONICS (BOE310) Session: 2023-24 Semester: 3RD
    Section/Branch: LECTURE PLAN Academic Period: Total Lectures:
    Lecture. Text/Reference Book
    Topics to be Covered
    No. No.

    Mission & Vision of the college and the Department, Introduction


    0
    to the subject, Course Outcomes and Awareness of OBE practices

    UNIT-1:
    Digital System And Binary Numbers: Number System and its arithmetic
    T1,T2
    1 Signed binary numbers
    Logic simplification and combinational logic design: Binary codes, code
    T1, T2
    2 conversion
    Logic simplification and combinational logic design: code conversion, review
    T1, T2
    3 of Boolean algebra and Demorgans theorem
    Logic simplification and combinational logic design: SOP & POS forms,
    T1, T2
    4 Canonical forms
    Logic simplification and combinational logic design: Karnaugh maps method
    T1, T2
    5 up to five variable
    Logic simplification and combinational logic design: Don’t care conditions T1, T2
    6
    Logic simplification and combinational logic design: POS simplification,
    T1, T2
    7 NAND and NOR implementation
    Logic simplification and combinational logic design: Quine McClusky
    T2
    8 method (Tabular method)
    UNIT-2:
    9 Combinational Logic: MSI devices like Magnitude comparator T1, T2
    10 Combinational Logic: Multiplexers, Demultiplexers T1, T2
    11 Combinational Logic: Decoders, Encoders T1, T2
    12 Combinational Logic: Multiplexed display T2
    13 Combinational Logic: half and full adders T1, T2
    14 Combinational Logic: subtractors T1, T2
    15 Combinational Logic: serial and parallel adders T1, T2
    16 Combinational Logic: BCD adder T1, T2
    UNIT-3:

    T1, T2
    17 Sequential Logic And Its Applications: Storage elements: latches & flip flops
    18 Characteristic Equations of Flip Flops T1, T2
    19 Flip Flop Conversion T1, T2
    20 Shift Registers T1, T2
    21 Ripple Counters T1, T2
    22 Synchronous Counters T1, T2
    23 Synchronous Counters continue T1, T2
    24 Other Counters: Johnson & Ring Counter T1, T2
    UNIT-4:
    Synchronous & Asynchronous Sequential Circuits: Analysis of clocked
    sequential circuits with state T1
    25 machine designing
    Synchronous & Asynchronous Sequential Circuits: State reduction and
    T1
    26 assignments

    T1
    27 Synchronous & Asynchronous Sequential Circuits: Design procedure
    28 Analysis procedure of Asynchronous sequential circuits T1
    29 circuit with latches, Design procedure T1
    30 Reduction of state and flow table T1
    31 Race-free state assignment T1
    32 Hazards. T1
    UNIT-5:
    Memory & Programmable Logic Devices: Digital Logic Families: DTL,
    T2
    33 DCTL

    T2
    34 Memory & Programmable Logic Devices: Digital Logic Families: TTL, ECL
    Memory & Programmable Logic Devices: Digital Logic Families: CMOS
    T2
    35 etc., Fan Out, Fan in, Noise Margin
    36 Memory & Programmable Logic Devices: RAM, ROM T1
    37 Memory & Programmable Logic Devices: PLA, PAL T1
    T1
    38 Memory & Programmable Logic Devices: Circuits of Logic Families
    Memory & Programmable Logic Devices: Interfacing of Digital Logic
    T1
    39 Families
    Memory & Programmable Logic Devices: Circuit Implementation using
    T1
    40 ROM, PLA and PAL

    REFERRENCE BOOKS:

    Text BOOKS:
    T1. M. Morris Mano and M. D. Ciletti, “Digital Design”, Pearson Education.
    T2. Digital Circuits and Design, S. Salivahanan, Oxford University Press

    Name and Signature of Faculty: RAJ GOPAL


    Subject Coordinator Coordinator/HOD Director
    EGE, GHAZIABAD
    ION TECHNOLOGY
    ontact No./Email ID: 8920889064 / raj.gopal@imsec.ac.in
    Semester: 3RD
    Total Lectures:
    Reason for
    Date (Scheduled) Date (Held) Course Outcome
    Deviation/Remarks

    9/13/2023

    13/09/2023

    18/09/2023 CO1:Apply concepts


    of Digital Binary
    18/09/2023 System and
    implementation of
    19/09/2023 Gates
    (K3)
    20/09/2023

    21/09/2023

    26/09/2023
    27/09/2023

    03/10/2023 CO2:Analyze and


    04/10/2023 design of
    04/10/2023 Combinational logic
    09/10/2023 circuits.
    9/10/2023 (K4)
    10/10/2023

    11/10/2023

    11/10/2023

    CO3:Analyze and
    30/10/2023
    design of Sequential
    31/11/2023
    logic circuits with
    1/11/2023
    their applications.
    1/11/2023
    (K4)
    6/11/2023
    6/11/2023
    8/11/2023

    8/11/2023

    CO4:Implement the
    8/11/2023 Design procedure of
    Synchronous &
    14/11/2023 Asynchronous
    Sequential Circuits.
    14/11/2023
    (K3)
    20/11/2023
    20/11/2023
    21/11/2023
    21/11/2023

    22/11/2023

    22/11/2023

    28/11/2023
    CO5:Apply the
    concept of Digital
    28/11/2023 Logic Families with
    29/11/2023 circuit implementation.
    (K3)
    29/11/2023

    30/11/2023

    30/11/2023

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