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    Arithmatic

    Uploaded by

    Miraz Ahmed

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd

    Arithmatic

    Uploaded by

    Miraz Ahmed
    7 views2 pages

    Original Title

    arithmatic

    Copyright

    © © All Rights Reserved

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    TXT, PDF, TXT or read online from Scribd

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    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Download as txt, pdf, or txt
    7 views2 pages

    Arithmatic

    Uploaded by

    Miraz Ahmed

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Download as txt, pdf, or txt
    of 2

    ----------------------------------------------------------------------------------

    -- Company:
    -- Engineer:
    --
    -- Create Date: 14:59:25 11/19/2023
    -- Design Name:
    -- Module Name: arithmaticcircuit - Behavioral
    -- Project Name:
    -- Target Devices:
    -- Tool versions:
    -- Description:
    --
    -- Dependencies:
    --
    -- Revision:
    -- Revision 0.01 - File Created
    -- Additional Comments:
    --
    ----------------------------------------------------------------------------------
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    ---- Uncomment the following library declaration if instantiating


    ---- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity arithmaticcircuit is
    PORT(A, B: in std_logic_vector(3 downto 0);
    s: in std_logic_vector(1 downto 0);
    cin: in std_logic;
    F: out std_logic_vector(3 downto 0);
    cout: out std_logic
    );

    end arithmaticcircuit;

    architecture Behavioral of arithmaticcircuit is

    component fa
    PORT(x, y, c1: in std_logic;
    f, cout: out std_logic
    );
    end component;
    signal c2, c3, c4: std_logic;
    signal b1, b2, b3, b4: std_logic;
    begin
    b1<=( B(0) and s(0)) or (not(B(0)) and s(1));
    b2<=(B(1) and s(0)) or (not(B(1)) and s(1));
    b3<=(B(2) and s(0)) or (not(B(2)) and s(1));
    b4<=(B(3) and s(0)) or (not(B(3)) and s(1));

    Comp1: fa port map(x=>A(0), y=>b1, c1=>cin, f=>F(0), cout=>c2);


    Comp2: fa port map(x=>A(1), y=>b2, c1=>c2, f=>F(1), cout=>c3);
    Comp3: fa port map(x=>A(2), y=>b3, c1=>c3, f=>F(2), cout=>c4);
    Comp4: fa port map(x=>A(3), y=>b4, c1=>c4, f=>F(3), cout=>cout);
    end Behavioral;
    --------------------Full-adder
    --------------------------------------------------------------
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    ---- Uncomment the following library declaration if instantiating


    ---- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity full_adder_process is
    Port ( a : in STD_LOGIC;
    b : in STD_LOGIC;
    c : in STD_LOGIC;
    sum : out STD_LOGIC;
    cout : out STD_LOGIC);
    end full_adder_process;

    architecture Behavioral of full_adder_process is

    begin
    full_process: process (a, b, c)
    begin
    sum <= a xor b xor c;
    cout <= ((a and b) or (a and c) or (b and c));
    end process;

    end Behavioral;

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