VHDL Digital NAND Gate Program

VHDL program for NAND Gate behavioral design in Xilinx integrated software environment-------------------------------------------------------------------------------- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal
-- Create Date:20:36:38 03/28/12
-- Design Name:NAND Gate Design
-- Module Name:NAND1 - Behavioral
-- Project Name:VHDL Program for "Universal Logic Gates" in XILINX Integrated Software Environment
-- Target Device:XC2S15
-- Tool versions:XST(VHDL/Verilog)
-- Revision 0.01 - File Created
-- Additional Comments:
-------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------------------- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-------------------------------------------------------------------------------entity NAND1 is
Port ( X : in std_logic;
Y : in std_logic;
F : out std_logic);
end NAND1;
architecture Behavioral of NAND1 is
begin
Process (X,Y)
begin
F <= X NAND Y;
end process;
end Behavioral;
VHDL program for NAND Gate architectural design in Xilinx integrated software environment-------------------------------------------------------------------------------- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal
-- Create Date:20:36:38 03/28/12
-- Design Name:NAND Gate Design
-- Module Name:NAND2 - Architectural
-- Project Name:VHDL Program for "Universal Logic Gates" in XILINX Integrated Software Environment
-- Target Device:XC2S15
-- Tool versions:XST(VHDL/Verilog)
-- Revision 0.01 - File Created
-- Additional Comments:
-------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---------------------------------------------------------------------------------

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
---------------------------------------------------------------------------------entity NAND2 is
Port ( X : in std_logic;
Y : in std_logic;
F : out std_logic);
end NAND2;
architecture NAND2_arch of NAND2 is
begin
process(X,Y)
begin
if((X='1') and (Y='1')) then
F<='0';
else
F<='1';
end if;
end process;
end NAND2_arch;

VHDL Digital NOT Gate Program

VHDL program for NOT Gate behavioral design in Xilinx integrated software environment--------------------------------------------------------------------------------- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal
-- Create Date: 20:19:26 03/28/12
-- Design Name:NOT Gate Design
-- Module Name:NOT1 - Behavioral
-- Project Name:VHDL Program for "Basic Gates" in XILINX Integrated Software Environment
-- Target Device:XC2S15
-- Tool versions:XST(VHDL/Verilog)
-- Revision 0.01 - File Created
-- Additional Comments:
-------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------------------- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-------------------------------------------------------------------------------entity NOT1 is
Port ( X : in std_logic;
F : out std_logic);
end NOT1;
architecture Behavioral of NOT1 is
begin
Process (X)
begin
F <= NOT X;
end process;

end Behavioral;
VHDL program for NOT Gate architectural design in Xilinx integrated software environment-------------------------------------------------------------------------------- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal
-- Create Date:20:19:26 03/28/12
-- Design Name:NOT Gate Design
-- Module Name:NOT2 - Architectural
-- Project Name:VHDL Program for "Basic Gates" in XILINX Integrated Software Environment
-- Target Device:XC2S15
-- Tool versions:XST(VHDL/Verilog)
-- Revision 0.01 - File Created
-- Additional Comments:
-------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
------------------------------------------------------------------------------------ Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--------------------------------------------------------------------------------entity NOT2 is
Port ( X : in std_logic;
F : out std_logic);
end NOT2;
architecture NOT2_arch of NOT2 is
begin
process(X)
begin
if(X='1') then
F<='0';
else
F<='1';
end if;
end process;
end NOT2_arch;

VHDL Digital PARITY ENCODER Logic Program

VHDL program for Parity Encoder behavioral design in Xilinx integrated software environment-------------------------------------------------------------------------------- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal
-- Create Date: 12:13:00 03/30/12
-- Design Name: Parity Encoder Design
-- Module Name: ENC4 - Behavioral
-- Project Name:VHDL Program for " Parity Encoder Design" in XILINX Integrated Software Environment
-- Target Device:XC2S15
-- Tool versions:XST(VHDL/Verilog)
-- Revision 0.01 - File Created
-- Additional Comments:
-------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------------------- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-------------------------------------------------------------------------------entity ENC4 is
Port ( W : in std_logic;
X : in std_logic;
Y : in std_logic;
Z : in std_logic;

OUTP : out std_logic;

OUT1 : out std_logic;
OUT2 : out std_logic);
end ENC4;
architecture Behavioral of ENC4 is
begin
process (W,X,Y,Z)
begin
OUTP <= W OR X OR Y OR Z;
OUT1 <= X OR Z;
OUT2 <= Y OR Z;
end process;
end Behavioral;
Posted by Jitditya Mondal at 05:33 1 comment:
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VHDL Digital OCT:BIN ENCODER Logic Program
VHDL program for Octal To Binary Encoder behavioral design in Xilinx integrated software environment-------------------------------------------------------------------------------- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal
-- Create Date: 14:31:54 04/01/12
-- Design Name: Octal To Binary Encoder Design
-- Module Name: OCT2BIN - Behavioral
-- Project Name:VHDL Program for " Octal To Binary Encoder Design" in XILINX Integrated Software Environment
-- Target Device:XC2S15
-- Tool versions:XST(VHDL/Verilog)
-- Revision 0.01 - File Created
-- Additional Comments:
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------------------- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-------------------------------------------------------------------------------entity OCT2BIN is
Port ( D : in std_logic_vector (7 downto 0);
Y : out std_logic_vector (2 downto 0));
end OCT2BIN;
architecture Behavioral of OCT2BIN is
begin
Y(0) <= D(1) OR D(3) OR D(5) OR D(7);
Y(1) <= D(2) OR D(3) OR D(6) OR D(7);
Y(2) <= D(4) OR D(5) OR D(6) OR D(7);
end Behavioral;
Posted by Jitditya Mondal at 05:32 1 comment:
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VHDL Digital DEC:BCD ENCODER Logic Program
VHDL program for Decimal To BCD Encoder behavioral design in Xilinx integrated software environment-------------------------------------------------------------------------------- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal
-- Create Date: 12:13:00 03/30/12
-- Design Name: Decimal to BCD Encoder Design

-- Module Name: ENC3 - Behavioral

-- Project Name:VHDL Program for " Decimal to BCD Encoder Design" in XILINX Integrated Software Environment
-- Target Device:XC2S15
-- Tool versions:XST(VHDL/Verilog)
-- Revision 0.01 - File Created
-- Additional Comments:
-------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------------------- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-------------------------------------------------------------------------------entity ENC3 is
Port ( Q : in std_logic;
R : in std_logic;
S : in std_logic;
T : in std_logic;
U : in std_logic;
V : in std_logic;
W : in std_logic;
X : in std_logic;
Y : in std_logic;
Z : in std_logic;
OUT0 : out std_logic;
OUT1 : out std_logic;

OUT2 : out std_logic;

OUT3 : out std_logic);
end ENC3;
architecture Behavioral of ENC3 is
begin
process (Q,R,S,T,U,V,W,X,Y,Z)
begin
OUT0 <= R OR T OR V OR X OR Z;
OUT1 <= S OR T OR W OR X;
OUT2 <= U OR V OR W OR X;
OUT3 <= Y OR Z;
end process;
end Behavioral;
Posted by Jitditya Mondal at 05:31 1 comment:
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VHDL Digital 8:3 ENCODER Logic Program
VHDL program for 8:3 Encoder behavioral design in Xilinx integrated software environment-------------------------------------------------------------------------------- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal
-- Create Date: 12:13:00 03/30/12
-- Design Name: 8:3 Encoder Design
-- Module Name: ENC2 - Behavioral
-- Project Name:VHDL Program for " 8:3 Encoder Design" in XILINX Integrated Software Environment
-- Target Device:XC2S15
-- Tool versions:XST(VHDL/Verilog)
-- Revision 0.01 - File Created
-- Additional Comments:
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------------------- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-------------------------------------------------------------------------------entity ENC2 is
Port ( S : in std_logic;
T : in std_logic;
U : in std_logic;
V : in std_logic;
W : in std_logic;
X : in std_logic;
Y : in std_logic;
Z : in std_logic;
OUT0 : out std_logic;
OUT1 : out std_logic;
OUT2 : out std_logic);
end ENC2;
architecture Behavioral of ENC2 is
begin
process(S,T,U,V,W,X,Y,Z)
begin
OUT0 <= T OR V OR X OR Z;
OUT1 <= U OR V OR Y OR Z;
OUT2 <= W OR X OR Y OR Z;

end process;
end Behavioral;
Posted by Jitditya Mondal at 05:29 1 comment:
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VHDL Digital 4:2 ENCODER Logic Program
VHDL program for 4:2 Encoder behavioral design in Xilinx integrated software environment-------------------------------------------------------------------------------- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal
-- Create Date: 12:13:00 03/30/12
-- Design Name: 4:2 Encoder Design
-- Module Name: ENC1 - Behavioral
-- Project Name:VHDL Program for " 4:2 Encoder Design" in XILINX Integrated Software Environment
-- Target Device:XC2S15
-- Tool versions:XST(VHDL/Verilog)
-- Revision 0.01 - File Created
-- Additional Comments:
-------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------------------- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-------------------------------------------------------------------------------entity ENC1 is

Port ( W : in std_logic;
X : in std_logic;
Y : in std_logic;
Z : in std_logic;
OUT0 : out std_logic;
OUT1 : out std_logic);
end ENC1;
architecture Behavioral of ENC1 is
begin
process(W,X,Y,X)
begin
OUT0 <= X OR Z;
OUT1 <= Y OR Z;
end process;
end Behavioral;
Posted by Jitditya Mondal at 05:28 1 comment:
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Sunday, 8 April 2012
VHDL Digital N - Bit Full SUBSTRUCTURE Logic Program
VHDL program for N Bit Substructure behavioral design in Xilinx integrated software environment-------------------------------------------------------------------------------- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal
-- Create Date:20:36:38 03/28/12
-- Design Name:N Bit Substructure Design
-- Module Name: SUB3 - Behavioral
-- Project Name:VHDL Program for "N Bit Substructure " in XILINX Integrated Software Environment
-- Target Device:XC2S15
-- Tool versions:XST(VHDL/Verilog)

-- Revision 0.01 - File Created

-- Additional Comments:
-------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------------------- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-------------------------------------------------------------------------------entity SUB3 is
generic(N: natural :=2);
Port ( X : in std_logic_vector (N-1 downto 0);
Y : in std_logic_vector (N-1 downto 0);
SUB : out std_logic_vector (N-1 downto 0);
BORROW : out std_logic);
end SUB3;
architecture Behavioral of SUB3 is
signal result: std_logic_vector (N downto 0);
begin
result<=('0' & X)-('0' & Y);
SUB <= result(N-1 downto 0);
BORROW <= result(N);
end Behavioral;

Posted by Jitditya Mondal at 12:14 1 comment:

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VHDL Digital 8 - Bit SUBSTRUCTURE Logic Program

VHDL program for 8 Bit Substructure behavioral design in Xilinx integrated software environment-------------------------------------------------------------------------------- Company:Techno Global - Balurghat
-- Engineer:Mr. Jitaditya Mondal
-- Create Date:20:36:38 03/28/12
-- Design Name:8 Bit Substructure Design
-- Module Name: SUB4 - Behavioral
-- Project Name:VHDL Program for "8 Bit Substructure " in XILINX Integrated Software Environment
-- Target Device:XC2S15
-- Tool versions:XST(VHDL/Verilog)
-- Revision 0.01 - File Created
-- Additional Comments:
-------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------------------------------------------- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-------------------------------------------------------------------------------entity SUB4 is
generic(N: natural :=2);
Port ( X : in std_logic_vector (7 downto 0);
Y : in std_logic_vector (7 downto 0);
SUB : out std_logic_vector (7 downto 0);

BORROW : out std_logic);

end SUB4;
architecture Behavioral of SUB4 is
signal result: std_logic_vector (8 downto 0);
begin
result<=('0' & X)-('0' & Y);
SUB <= result(7 downto 0);
BORROW <= result(8);
end Behavioral;