Physical Design - PLACEMENT

PHYSIACL DESIGN
PLACEMENT
PLACEMENT : Placement is process of placing the std cells in

the legalized position ( on site rows) in the core area .
➢ In this stage, all the standard cells are placed in the design (size,
shape & macro-placement is done in floor-plan).
➢ The tool tries to place the standard cell in such a way that the
design should have minimal congestions and the best timing.
❖ Placement Strategies:
➢ Timing Driven Placement :
- Tool tries to place the standard cells along timing critical

path close together to reduce net RC and meet setup timing.
- In this stratage tool try to reduce the net length to meet
timing
➢ Congestion Driven Placement :
- Minimize the congestion in this stratage .

- Tool tries to spread the cells where the density of cells are
more for the reduction of congestion.
- To spreading standard cell instances from each other such
that more routing tracks are created between them
➢ Area Driven Placement:

- In Area driven stratage tool tries to optimize the are
utilization
- Instead of using AND-OR-INV cells it will use AOI, OAI cells
➢ Power Driven Placement:
- In this stratage tool will try to reduce the lekage power by

using SVT(RVT) , HVT cells instead of LVT cells.
❖ Stages in Placement:
- Global / Coarse placement

- Deatail placement
- Optimization
➢ Global / Coarse placement :
- During the coarse placement, the tool determines an

approximate location for each cell according to the timing,
congestion and multi-voltage constraints.
- Cell overlapping may occur .

➢ Detail Placement / Ligalization :
- The tool moves the cells to legal locations on the placement

grid and eliminate any overlap between cells.
These small changes to cell location cause the lengths of the wire
connections to change, possibly causing new timing violations. Such
violations can often be fixed by incremental optimization.
-
➢ Optimization:
- Place_opt: This command performs coarse placement,

HFNS, optimization and legalization.
- In the place_opt command, the –congestion option

causes the tool to apply –high effort to congestion removal
for better routability, this will require more runtime and
cause area utilization to be less uniform across the available
- placement area.
✓ Place_opt (synopsis) : perform 5 stages
i) Initial_opt :
- Tool perform the coarse placement
- No ligalization
- Scan chain optimizatin
- Buffer aware , timing driven placemnt .
ii) initial_drc :
- Remove existing buffer tree and it will add HFN synthesis
- Fixing drc violations max tran , max cap , max fanout .
iii) Initial_opt :
- Quick timing optimization
iv) Final_place:
- Performs the Detail placement
- Incremental timing driven optimiztion
- Fixing global congestion
- Scan chain optimization
v) Final_opt : (cmd : place_opt -to final_opt)

- Legalization
- Fixing timing violations
✓ Refine_opt (cadance) :
i) Initial path optimization: it incrementally moves registers

along timing paths to improve timing.
ii) Incremental placement: to reduce congestion and improve

routability.
iii) Incremental optimization: perform incremental timing,

area, congestion and leakage power optimization.
iv) Final placement: final phase of path optimization to improve

timing
v) Legalization: tool legalize the placement.
➢ High Fan-out Net Synthesis (HFNS):
In the placement stage we do this process. The process of buffering the

high fan-out to balance the load because if design has too many loads
then it affects delay and transition time. We know delay is load is directly
proportional to the delay. By buffering the HFN the load can be balanced
and this process is called the HFNS.
➢ Scan chain Re-Ordering :
DFT tool flow makes a list of all the scan-able flops in the design, and
sorts them based on their hierarchy and perform scan stitching (clock
domains, maximum chain length constraints will be considered). Scan-
chain at this stage will not be layout friendly.
In APR tool scan chains are reordered on the basis of placement of flops
& Q-SI routing. This is nothing but scan-chain reordering.
• Reduce congestion, Total wire-length
• Require fewer repeaters in Q-SI path
➢ DFT optimization:
If block contains scan chains by default create_placement, place_opt and

clock_opt commands perform DFT optimization. During initial
placement, the tool focuses on the QOR for the function nets by ignoring
the scan chains. After initial placement, the tool further improves the QOR
by repartitioning and reordering the scan chains based on the initial
placement.
Scan chains reordering reduces wire length so timing will improve.
Scan chains reordering minimize congestions and improves routability
The scan chain information (SCANDEF) from synthesis can be transferred
to ICC compiler into two ways:
By loading the netlist in DDC format
By loading a SCANDEF file.
Tools used for Placement :

Synopsis : ICCII
Cadance : Innoves
➢ Inputs and output of placement:

- Netlist
- Floorplan def
- Logical and physical library (.lib, lef)
- Design constraint (SDC)
- Technology file
Before the start of placement optimization all wire load models are
removed. Placement uses RC values from the virtual route to calculate
timing. The virtual route is the shortest Manhattan distance between two
pins. Virtual route RC values are more accurate than WLM RC’s.
➢ Checks before placement :
- Netlist should be clean
- Proper pin placement
- Macros and preplace cells are fixed
- Power routes should be free of drc’s
❖ Different task during placement:
• Placement of standard cells

• Optimization of area, power, congestion and timing.
• Legalization
• HFNS
• Scan chain reordering
❖ Fixes for congestion and timing :
Placement constraints provide guidance during placement and placement

optimization and legalization so that congestion and timing
violations will be reduced.
• Placement blockages for cell density

• Placement bounds for cell density
• Cell padding for pin density
• Module padding / instance padding
• Uniform cell distribution
❖ Placement bounds:
It is a constraint that controls the placement of groups of leaf cells and

hierarchical cells. It allows you to group cells to minimize wire length
and place the cells at most appropriate locations. When our timing is
critical during placement then we create bounds in that area where two
communicating cells are sitting far from another. It is a fixed region in
which we placed a set of cells.
Types of bounds:
1. Soft move bound

2. Hard move bound
3. Exclusive move bound
➢ Soft move bound:
In this tool tries to place the cells in the move bound within a specified
region, however, there is no guarantee that the cells are placed inside the
bounds.
Create bound –name b0 –type soft –boundary {10 10 20 20}
instance_1 #define softbound for instance_1 with its left corner at (10 10)
and its upper-right corner at (20 20).
➢ Hard move bound:
In this tool must place the cells in the move bound within a specified
region.
Create bound –name b1 –type soft –boundary {10 10 20 20} instance_2
➢ Exclusive move bound:
In this tool tries to place the cells in the group bound within a floating
region, however, there is no guarantee that the cells are placed inside the
bounds
Create bound –name b2 –exclusive –boundary {10 10 20 20} instance_1
❖ Congestion: (report_congestion) :
Congestion occurs when the number of available routing resources is
less than the required routing resources.
i) Global congestion
ii) Local congestion
Congestion = no. of required routing nets/ avalable routing

tracks
What are the reasons for congestion?
• High standard cell density in a small area

• Placement of standard cells near the macros
• High pin density at the edges of macros due to high fan in
cells like AOI, OAI
• Bad floorplan (no proper blockages, halos are present)
• Macros/standard cell might have used all the metal layers
inside and routing resources will be less
• Placing macros at the center instead of the boundary.
• During IO optimization tool does buffering so lot of cells
placed in the core area
Cell Density:
• Refers to the tightness of packing of standard cells (pre-
designed logic blocks) within a designated area of the chip's
layout.
• It's typically expressed as a percentage of the total area
occupied by the cells within that region.
Pin Density:
• Focuses on the concentration of pins (connection points)
associated with the cells within a specific area.
• It's often measured as the number of pins per unit area.
• Similar to cell density, a higher pin density can pose routing
difficulties. With more pins crammed together, the routing tool
has a tougher time finding available tracks (spaces for metal
wires) to establish connections between the cells.
• This can again result in routing congestion and design issues.
➢ How to control the congestion:
• Set_congestion_options –max_util 0.45 –coordinate {x1 y1 x2 y2}

Here we set the maximum cell density upto 45% and given the
coordinates for the particular area.
• Place_opt –congestion_driven –effort high
Reduce the local cell density using partial placement blockages

• Create_placement_blockage –boundary {10 20 100 200} –type
partial –blocked_percentage 40
If we have more pin density, which can be reduced by adding cell

padding to the cells which is causing congestion. Cell padding can
be applied by setting the keepout margin command
• Create_keepout_margin –type soft –outer {10 10 10 10}

my_lib_macro
• Change the floorplan (macros placement, macro spacing and pin

orientation)
• Reordering the scan chains to reduce the congestion

❖ Checks after placement:
• Check legalization
• Check PG connections for all the cells.
• Check congestion, density screens & pin density maps all

▪ these should be under control
• Timing QOR, there should not be any high WNS violations.
• Minimum max Tran and max cap violations.
• Check whether all don’t touch cells & nets are preserved.
• Check the total utilization of design after placement.
❖ Some commands used in placement :

• add_buffer
• magnet_placement
• create_placement -congestion -effort_high
• legalize_placement
• check_legality
• place_opt
• connect_pg_net
• set_multi_vth
• check_global_route_congestion
• report_congestion
• report_constraints
• report_timing
• create_keepout_margin -type hard ……
• create_bound
❖ Goals of Placement :
• Timing Optimization: This ensures signals can propagate

between cells within the specified time constraints. Placement
tools aim to minimize the wire lengths between frequently
communicating cells, reducing signal delays.
• Power Optimization: Lowering overall power consumption is
crucial. Placement strategies try to group cells with similar
switching activity to minimize dynamic power. Additionally,
reducing wire lengths can also contribute to power savings.
• Area Optimization: Efficient utilization of the chip area is
desired. Placement algorithms try to pack the cells together tightly
while maintaining routability (discussed below). This reduces the
die size, leading to cost benefits and potentially allowing more
functionality on the chip.
• Routability: After placement, wires (nets) need to be routed
between cells to establish connections. Placement should minimize
congestion, which refers to the difficulty of routing nets due to
limited space between cells. Ideally, the placement should avoid
dense regions that would make routing challenging.
• Minimizing Violations: Placement should ensure cells adhere
to design rules (DRCs) set by the fabrication process. These rules
specify clearances between objects and other limitations to ensure
the chip can be manufactured correctly.
❖ Outputs of Placement :
• Placement def ( cell location , cell pg connections ect )

• Congestion report
• Timing report
• Utilization
- Venu kumar kare
https://www.linkedin.com/in/venu-kumar-
kare-
465265233?lipi=urn%3Ali%3Apage%3Ad_flagship3_p
rofile_view_base_contact_details%3BKWAHrv7zQUG
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PHYSIACL DESIGN

PLACEMENT : Placement is process of placing the std cells in

➢ Timing Driven Placement :

- Tool tries to place the standard cells along timing critical

➢ Congestion Driven Placement :

- Minimize the congestion in this stratage .

➢ Area Driven Placement:

➢ Power Driven Placement:

- In this stratage tool will try to reduce the lekage power by

- Global / Coarse placement

➢ Global / Coarse placement :

- During the coarse placement, the tool determines an

- Cell overlapping may occur .

- The tool moves the cells to legal locations on the placement

- Place_opt: This command performs coarse placement,

- In the place_opt command, the –congestion option

✓ Place_opt (synopsis) : perform 5 stages

v) Final_opt : (cmd : place_opt -to final_opt)

i) Initial path optimization: it incrementally moves registers

ii) Incremental placement: to reduce congestion and improve

iii) Incremental optimization: perform incremental timing,

iv) Final placement: final phase of path optimization to improve

v) Legalization: tool legalize the placement.

➢ High Fan-out Net Synthesis (HFNS):

In the placement stage we do this process. The process of buffering the

➢ Scan chain Re-Ordering :

If block contains scan chains by default create_placement, place_opt and

Tools used for Placement :

➢ Inputs and output of placement:

➢ Checks before placement :

- Netlist should be clean

- Proper pin placement

- Macros and preplace cells are fixed

- Power routes should be free of drc’s

❖ Different task during placement:

• Placement of standard cells

❖ Fixes for congestion and timing :

Placement constraints provide guidance during placement and placement

• Placement blockages for cell density

It is a constraint that controls the placement of groups of leaf cells and

1. Soft move bound

➢ Soft move bound:

➢ Hard move bound:

➢ Exclusive move bound:

Congestion = no. of required routing nets/ avalable routing

What are the reasons for congestion?

• High standard cell density in a small area

➢ How to control the congestion:

• Set_congestion_options –max_util 0.45 –coordinate {x1 y1 x2 y2}

• Place_opt –congestion_driven –effort high

Reduce the local cell density using partial placement blockages

If we have more pin density, which can be reduced by adding cell

• Create_keepout_margin –type soft –outer {10 10 10 10}

• Change the floorplan (macros placement, macro spacing and pin

• Reordering the scan chains to reduce the congestion

• Check PG connections for all the cells.

• Check congestion, density screens & pin density maps all

• Timing QOR, there should not be any high WNS violations.

• Minimum max Tran and max cap violations.