1.

Address bus/line: 20 bit address bus

An address line usually refers to a physical connection between a CPU and memory. It specifies
which address to access in the memory. For an 'n' bit address line, we can access 2 n memory
locations.

2. Data bus: 16 bit

Data bus is a computer subsystem that facilitates the exchange of information between
various components on a motherboard or system board or between separate computers. This
involves moving information to and from the system's RAM or the CPU.
The 8086 has a 16-bit data bus, so it can read data from or write data to memory and ports
either 16 bits or 8 bits at a time. The 8086 has multiplexed address and data bus which
reduces the number of pins needed, but does slow down the transfer of data (drawback).

[What is the control bus?

The control bus manages the communication between the computer's CPU and its other
components. It specializes in transferring control signals that coordinate and regulate the
hardware's actions. The signals ensure operations are carried out in the correct sequence and at
the right time
]
3. The 8086 is a 16-bit microprocessor:
The term “16-bit” means that its arithmetic logic unit, internal registers and most of its
instructions are designed to work with 16-bit binary words.
4. The 8086 provides fourteen 16-bit registers.
What is a register in microprocessor?
A processor register (CPU register) is one of a small set of data holding places that are part of
the computer processor. A register may hold an instruction, a storage address, or any kind of
data

5. The 8086 has multiplexed address and data bus which reduces the number of pins needed, but
does slow down the transfer of data (drawback).
6. The Features of 8086 Microprocessor is possible to perform bit, byte, and word in 8086. It
performs the arithmetic and logical operations on bit, byte, word and decimal numbers
including multiply and divide.
7. The Intel 8086 is designed to operate in two modes, namely the minimum mode and the
maximum mode. When only one 8086 CPU is to be used in a microcomputer system, the 8086
is used in the minimum mode of operation. In this mode the CPU issues the control signals
required by memory and I/O. In multiprocessor (more than one processor in the system) system
8086 operates in maximum mode. In maximum mode, control signals are generated with the
help of external bus controller (8288).
8. The Intel 8086 supports multiprogramming. In multiprogramming, the code for two or more
processes is in memory at the same time and is executed in a time-multiplexed fashion.
9. An interesting feature of the 8086 is that it fetches up to six instruction bytes (4 instruction
bytes for 8088) from memory and queue stores them in order to speed up instruction execution.
10. The Features of 8086 Microprocessor provides powerful instruction set[An instruction set is a group of
commands for a central processing unit (CPU) in machine language. ] with the following addressing modes:

Register, immediate, direct, indirect through an index or base, indirect through the sum of a
base and an index register, relative and implied

Pin diagram of 8086 microprocessor is as given below:

AD0-AD15: Address/Data bus.

They are multiplexed with data.
These are low order address bus.
When AD lines are used to transmit memory address the symbol A is used instead of AD, for
example A0-A15.
When data are transmitted over AD lines the symbol D is used in place of AD, for example D0-D7, D8-
D15 or D0-D15.
A16-A19: High order address bus.
These are multiplexed with status signals.

S2, S1, S0: Status pins. These pins are active during T4, T1 and T2 states and is returned to passive state 1,1,1 during
T3 or Tw (when ready is inactive). These are used by the 8288 bus controller for generating all the memory and I/O
operation) access control signals. Any change in S2, S1, S0 during T4 indicates the beginning of a bus cycle.
S2 S1 S0 Characteristics

0 0 0 Interrupt acknowledge

0 0 1 Read I/O port

0 1 0 Write I/O port

0 1 1 Halt

1 0 0 Code access

1 0 1 Read memory

1 1 0 Write memory

1 1 1 Passive state

A16/S3, A17/S4, A18/S5, A19/S6 : The specified address lines are multiplexed with corresponding status signals.

A17/S4 A16/S3 Function

0 0 Extra segment access

0 1 Stack segment access

1 0 Code segment access

1 1 Data segment access

BHE’/S7: Bus High Enable/Status. During T1 it is low. It is used to enable data onto the most significant half of data
bus, D8-D15. 8-bit device connected to upper half of the data bus use BHE (Active Low) signal. It is multiplexed with
status signal S7. S7 signal is available during T2, T3 and T4.

RD’: This is used for read operation. It is an output signal. It is active when low.

READY: This is the acknowledgement from the memory or slow device that they have completed the data transfer.
The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the
microprocessor. The signal is active high (1).

INTR : Interrupt Request. This is triggered input. This is sampled during the last clock cycles of each instruction for
determining the availability of the request. If any interrupt request is found pending, the processor enters the interrupt
acknowledge cycle. This signal is active high(1).
NMI : Non maskable interrupt. This is an edge triggered input which results in a type II interrupt. NMI is non-
maskable internally by software. A transition made from low(0) to high(1) initiates the interrupt at the end of the
current instruction. This input has been synchronized internally.

INTA : Interrupt acknowledge. It is active low(0).

MN/MX’ : Minimum/Maximum. This pin signal indicates what mode the processor will operate in.

RQ’/GT1′, RQ’/GT0′ : Request/Grant. These are bidirectional pins. These pins are used by local bus masters used
to force the microprocessor to release the local bus at the end of the microprocessor’s current bus cycle. RQ’/GT0′
have higher priority than RQ’/GT1′.

LOCK’: Its an active low pin. It indicates that other system bus masters have not been allowed to gain control of the
system bus while LOCK’ is active low (0). The LOCK signal will be active until the completion of the next
instruction.

TEST’ : This examined by a ‘WAIT’ instruction. If the TEST pin goes low(0), execution will continue, else the
processor remains in an idle state.

CLK : Clock Input. The clock input provides the basic timing for processing operation and bus control activity.

RESET : This pin requires the microprocessor to terminate its present activity immediately. The signal must be active
high(1) for at least four clock cycles.

Vcc : Power Supply( +5V D.C.)

GND : Ground

QS1,QS0 : Queue Status. These signals indicate the status of the internal 8086 instruction queue according to the table
shown below:
QS1 QS0 Status

0 0 No operation

0 1 First byte of op code from queue

1 0 Empty the queue

1 1 Subsequent byte from queue

M/IO’: This signal is used to distinguish between memory and I/O operations. The M Signal is Active high whereas
the IO’ Signal is Active Low. When this Pin is High, the memory operations take place. On the other hand, when the
Pin is low, the Input/output operations takes place.

DT/R: Data Transmit/Receive. This pin is required in minimum systems that want to use an 8286 or 8287 data bus
transceiver.( A transceiver is a bidirectional buffer ( is a region of a memory used to store data temporarily while
it is being moved from one place to another.). With a transceiver, a microprocessor can receive data from an I/O
device or can send data out to an I/O device over the same set of common lines (data bus).) The direction of data
flow is controlled through the transceiver.

DEN: Data enable. This pin is provided as an output enable for the 8286/8287 in a minimum system which uses
transceiver. DEN is active low(0) during each memory and input-output access and for INTA cycles.

HOLD/HLDA: HOLD indicates that another master has been requesting a local bus .This is an active high(1). The
microprocessor receiving the HOLD request will issue HLDA (high) as an acknowledgement in the middle of a T4 or
T1 clock cycle.

ALE : Address Latch Enable. (latch: flip-flop used to remember digital data. Used to interface the output of
microprocessor to other device )ALE is provided by the microprocessor to latch the address into the 8282 or 8283
address latch. It is an active high(1) pulse during T1 of any bus cycle. ALE signal is never floated, is always integer.

Architecture of 8086

Block Diagram of 8086

8086 CPU is divided into two parts:

1. Bus Interface Unit

2. Execution Unit

Dividing the work between these two units speeds up processing.

The 8086 microprocessor has a rich set of registers, including general-purpose registers, segment
registers, and special registers.

The general-purpose registers can be used to store data and perform arithmetic and logical
operations, while the segment registers are used to address memory segments.
The special registers include the flags register, which stores status information about the result of
the previous operation, and the instruction pointer (IP), which points to the next instruction to be
executed.

general-purpose registers =🡺 store data and perform arithmetic and logical operations
segment registers==🡺 address memory segments.
special registers =🡺 stores status information about the result of the previous operation
instruction pointer (IP) =🡺 points to the next instruction to be executed.
it has no memory or peripherals.
8086 does not have a RAM or ROM inside it.
However, it has internal registers for storing intermediate and final results and interfaces with
memory located outside it through the System Bus.
The main advantage of the 8086 microprocessor is that it supports Pipelining.
Memory segmentation:
● In order to increase execution speed and fetching speed, 8086 segments the memory.
● Its 20-bit address bus can address 1MB of memory;
● 8086 works only with four 64KB segments within the whole 1MB memory.
The internal architecture of Intel 8086 is divided into 2 units: The Bus Interface Unit (BIU),
and The Execution Unit (EU). These are explained as following below.

1. The Bus Interface Unit (BIU):

It provides the interface of 8086 to external memory and I/O devices via the System Bus (The system
bus can be viewed as an internal transportation system for the computer. The system bus carries address, data and control information. It is
). It performs various
comprised of three types of buses to do this function, the Address Bus, the Data Bus, and Control Bus.
machine cycles such as memory read, I/O read, etc. to transfer data between memory and I/O
devices.
BIU performs the following functions are as follows:
● It generates the 20-bit physical address for memory access.
● It fetches instructions from the memory.
● It transfers data to and from the memory and I/O.
● Maintains the 6-byte pre-fetch instruction queue (supports pipelining).
BIU mainly contains the 4 Segment registers, the Instruction Pointer, a pre-fetch queue, and
an Address Generation Circuit.
Instruction Pointer (IP):
● It is a 16-bit register. It holds offset of the next instructions in the Code Segment.
● IP is incremented after every instruction byte is fetched.
● IP gets a new value whenever a branch instruction occurs.
● CS is multiplied by 10H to give the 20-bit physical address of the Code Segment.
● The address of the next instruction is calculated by using the formula CS x 10H + IP

Code Segment register: (16 Bit register): CS holds the base address for the Code Segment. All
programs are stored in the Code Segment and accessed via the IP.
Data Segment register: (16 Bit register): DS holds the base address for the Data Segment.
Stack Segment register: (16 Bit register): SS holds the base address for the Stack Segment.
Extra Segment register: (16 Bit register): ES holds the base address for the Extra Segment.

6 Byte Pre-fetch Queue:

● It is a 6-byte queue (FIFO).
● Fetching the next instruction (by BIU from CS) while executing the current instruction is called
pipelining.
● Gets flushed whenever a branch instruction occurs.
● The pre-Fetch queue is of 6-Bytes only because the maximum size of instruction that can have
in 8086 is 6 bytes. Hence to cover up all operands and data fields of maximum size instruction
in 8086 Microprocessor there is a Pre-Fetch queue is 6 Bytes.
● The pre-Fetch queue is connected with the control unit which is responsible for decoding op-
code and operands and telling the execution unit what to do with the help of timing and control
signals.
● The pre-Fetch queue is responsible for pipelining and because of that 8086 microprocessor is
called fetch, decode, and execute type microprocessor. Since there are always instructions
present for decoding and execution in this queue the speed of execution in the microprocessor
is gradually increased.
● When there is a 2-byte space in the instruction pre-fetch queue then only the next instruction
will be pushed into the queue otherwise if only a 1-byte space is vacant then there will not be
any allocation in the queue. It will wait for a spacing of 2 bytes in subsequent queue decoding
operations.
● Instruction pre-fetch queue works in a sequential manner so if there is any branch condition
then in that situation pre-fetch queue fails. Hence to avoid chaos instruction queue is flushed
out when any branch or conditional jumps occur.

2. The Execution Unit (EU):

The main components of the EU are General purpose registers, the ALU, Special purpose registers,
the Instruction Register and Instruction Decoder, and the Flag/Status Register.
1. Fetches instructions from the Queue in BIU, decodes, and executes arithmetic and logic
operations using the ALU.
2. Sends control signals for internal data transfer operations within the microprocessor.(Control
Unit)
3. Sends request signals to the BIU to access the external module.
4. It operates with respect to T-states (clock cycles) and not machine cycles.

8086 has four 16-bit general purpose registers AX, BX, CX, and DX which store intermediate
values during execution. Each of these has two 8-bit parts (higher and lower).
● AX register: (Combination of AL and AH Registers)
It holds operands and results during multiplication and division operations. Also an
accumulator during String operations.

● BX register: (Combination of BL and BH Registers)

It holds the memory address (offset address) in indirect addressing modes.

● CX register: (Combination of CL and CH Registers)

It holds the count for instructions like a loop, rotates, shifts and string operations.

● DX register: (Combination of DL and DL Registers)

It is used with AX to hold 32-bit values during multiplication and division.

Arithmetic Logic Unit (16-bit): Performs 8 and 16-bit arithmetic and logic operations.

Special purpose registers (16-bit): Special purpose registers are called Offset registers also.
Which points to specific memory locations under each segment.
● Stack Pointer: Points to Stack top. Stack is in Stack Segment, used during instructions
like PUSH, POP, CALL, RET etc.
 ● Base Pointer: BP can hold the offset addresses of any location in the stack segment. It is
used to access random locations of the stack.
● Source Index: It holds offset address in Data Segment during string operations.
● Destination Index: It holds offset address in Extra Segment during string operations.

Flag/Status register (16 bits): It has 9 flags that help change or recognize the state of the
microprocessor.
6 Status flags:
1. Carry flag(CF)
2. Parity flag(PF)
3. Auxiliary carry flag(AF)
4. Zero flag(Z)
5. Sign flag(S)
6. Overflow flag (O)
Status flags are updated after every arithmetic and logic operation.
3 Control flags:
1. Trap flag(TF)
2. Interrupt flag(IF)
3. Direction flag(DF)
These flags can be set or reset using control instructions like CLC, STC, CLD, STD, CLI, STI,
etc. The Control flags are used to control certain operations.
Control unit :The Control Unit in the 8086 microprocessor is a component that manages the
overall operation of the microprocessor. The control unit is responsible for controlling the flow of
instructions through the microprocessor and coordinating the activities of the other components,
including the Decode Unit, Execution Unit, and Prefetch Unit.
The Control Unit acts as the central coordinator for the microprocessor, directing the flow of data
and instructions and ensuring that the microprocessor operates correctly. It also monitors the state
of the microprocessor, ensuring that the correct sequence of operations is followed.

Register organization in 8086

In the 8086 Microprocessor, the registers are categorized into mainly four types:

1. General Purpose Registers

2. Segment Registers
3. Pointers and Index Registers
4. Flag or Status Register

IP
CS
DS
SS
ES
AH 8 AL
BH 8 BL
 CH 8 CL
DH 8 DL
SP
BP
SI
DI
Flag

1) General Purpose Registers

The use of general-purpose registers is to store temporary data. While the instructions are executed in
the control unit, they may work on some numeric value or some operands. These need to be stored
somewhere so that the processor can operate on them easily. So, these registers are used in these
cases. There are 4 general-purpose registers of 16-bit length each. Each of them is further divided
into two subparts of 8-bit length each: one high, which stores the higher-order bits and another low
which stores the lower order bits.

i. AX = [AH:AL]
ii. BX = [BH:BL]
iii. CX = [CH:CL]
iv. DX = [DH:DL]

2) Segment Registers
There are 4 segment registers in 8086 Microprocessor and each of them is of 16 bit. The code and
instructions are stored inside these different segments.

1. Code Segment (CS) Register: is used for addressing memory location in the code
segment of the memory, where the executable program is stored.
The user cannot modify the content of these registers. Only the microprocessor's compiler
can do this.
2. Data Segment (DS) Register: points to the data segment of the memory where the data is
stored.
The user can modify the content of the data segment.
3. Stack Segment (SS) Registers: is used for addressing stack segment of the memory.
The SS is used to store the information about the memory segment. The operations of the SS
are mainly Push and Pop.
4. Extra Segment (ES) Register:
By default, the control of the compiler remains in the DS where the user can add and modify
the instructions. If there is less space in that segment, then ES is used. ES is also used for
copying purpose.
3) Pointers and Index Registers
The pointers will always store some address or memory location. In 8086 Microprocessor, they
usually store the offset through which the actual address is calculated.

1. Instruction Pointer (IP):

The instruction pointer usually stores the address of the next instruction that is to be
executed. Apart from this, it also acts as an offset for CS register.
2. Base Pointer (BP):
The Base pointer stores the base address of the memory. Also, it acts as an offset for Stack
Segment (SS).
3. Stack Pointer (SP):
The Stack Pointer Points at the current top value of the Stack. Like the BP, it also acts as an
offset to the Stack Segment (SS).
The indexes are used with the extra segment and they usually are used for copying the
contents of a particular block of memory to a new location.
4. Source Index (SI):
It stores the offset address of the source.
5. Destination Index (DI):
It stores the offset address of the Destination.

4) Flag or Status Register

The Flag or Status register is a 16-bit register which contains 9 flags, and the remaining 7 bits are
idle in this register. These flags tell about the status of the processor after any arithmetic or logical
operation. IF the flag value is 1, the flag is set, and if it is 0, it is said to be reset.

It contains : 6 – status flags and 3 – control flags

S.No Type Register width Name of the Registers

16-bit AX,BX,CX,DX
1 General purpose Registers(4)
8-bit AL,AH,BL,BH,CL,CH,DL,DH

Stack Pointer(SP)
2 Pointer Registers 16-bit
Base Pointer(BP)

3 Index Registers 16-bit Source Index(SI)

 Destination Index(DI)

Code Segment(CS)

Data Segment(DS)
4 Segment Registers
16-bit Stack Segment(SS)

Extra Segment(ES)

Flag register of 8086

Flag register of 8086 is a 16-bit register where status of the latest Arithmetic operation
performed.

Flag register of 8086

As it has 16-bits , it has 16 flags. These 16 flags are classified as

● 7 are don’t care flags.

● 3 are control flags ( accessible to programmers ).
● 6 are status flags ( not accessible to programmers ).

Status flags:
CF:
It stands for carry flag.
If CF = 1 ; it means carry is generated from the MSB.

If CF = 0 ; no carry is generated out of MSB.

PF:
It stands for parity flag.

If PF = 1 ; it means it is even parity in the result ( there are even numbers of 1’s ).

If PF = 0 ; it means it is odd parity.

In example 1, there are 4 ones’ which is even , in the second example there are 5 ones’ which is
odd in count.

AF:

AF stands for auxiliary flag. As 8-bits form a byte, similarly 4 bits form a nibble. So in 16 bit
operations there are 4 nibbles.

If AF = 1 ; there is a carry out from lower nibble.

If AF = 0 ;no carry out of lower nibble.

ZF:
This is zero flag. Whenever the output is 0 this flag is 1.
If ZF = 1 ; output is zero.

If ZF = 0 ; output is non zero.

OF:
OF stands for overflow flag.

The are two types of numbers

● Signed
● Unsigned
Unsigned:
This is a 8 bit positive number which ranges from 0 to 255. In hexadecimal it’s range is from 00
to FF. In the OF flag, it has nothing to do with unsigned numbers. Only signed numbers are
considered in the OF flag.
Signed:
This is also a 8-bit number( can be 16-bit too ) which is equally distributed among +ve and -ve
numbers. By considering MSB , it is decided whether it is a positive or negative number. If
MSB=1 , it is a negative number or else negative number.

Eg: 1011 0011 is -ve

0111 1001 is +ve

So it’s positive range is from 0 to 127 [ 00 to 7F (in hexadecimal ) ], it consists of 128 +ve
values.

It also has 128 negative numbers ranging from -1 to -128 [ -01 to -80 ( in hexadecimal ) ].
Whenever a negative number is saved, it is saved as it’s 2’s complement. To access the number
we have to make its 2’s complement again. A number is considered as negative whenever its
MSB is 1, and its 2’s complement is the actual negative number.

For eg: 1011 0011

It is a negative number and its 2’s complement is 0100 1101, which is equivalent

to 4D ( hexadecimal ) . so it is -4DH.
So there is a well defined limit for signed numbers ( 00 to 7F and -01 to 80 ). If the result or
operands exceeds the limit, it is known as overflow. If there is overflow, then the MSB would
show incorrect values, if there is overflow then

MSB = 1 , then it is +ve number

MSB = 0 , then it is -ve number. This is the reverse with the original case.

SF:
This stands for sign flag. In short it copies the value of MSB. It shows wrong notation in the case
of overflow.

CF, AF, PF, ZF, OF, SF , these were status flags, and these keep changing after every arithmetic
operation. And these flags are not controlled by the user, these are controlled by the ALU.

Control flag:
There are three types of control flags, and by default all are zero.

TF:
This stands for trap flag. Generally processors give output after the complete program, but when
TF = 1, output is given after every instruction.

This is useful to check logical errors, when the program is too long.

IF:
This is interrupt flag.
IF = 1, then enable interrupts

IF = 0, then interrupts are disabled. By default interrupts are disabled.

DF:
This stands for direction flag. In the case string operation, by default address keeps incrementing
for instruction execution. It means after execution of an instruction, whether the processor should
execute next instruction or previous instruction.

IfPipelining inis8086
DF = 0 ; address auto incrementing ( processor executes next instruction ).

If DF = 1 ; address is auto decrementing ( processor executes previous instruction ).

Pipelining is the feature of fetching the next instruction while executing the current instruction.

Instructions are stored in memory, therefore, it has to be fetched, decoded and then executed. Pipelining boost
performance as fetching and executing is done alongside at the same time.

fig. Pipelined vs Non Pipelined processor

In 8085, which has a non-pipelined processor for fetching and executing 5 instructions, 10-time cycles are
required. While in 8086, for fetching and executing 5 instructions 6 times cycle is required. You can see the
immense impact pipelining makes. In the pipeline, while one instruction is being executed side by side
next instruction is being fetched.

Pipelining has become possible because of 6 bytes pre-fetch queue. It is a 6 byte FIFO RAM used to
implement pipelining. BIU (Bus Interface Unit) fetches the 6 instruction byte from the code segment and stores
them into the queue. 8086 has a 16-bit data bus thus code is refilled in the queue when at least 2 bytes are
empty.
Drawbacks:

1. Data dependency- A situation where instruction depends on a result of a sequentially previous instruction
before it can complete execution.

2. Branching- Sometimes it may happen that the program is not executing sequentially because of loops and
conditional statements. But with the help of the pipeline, we have fetched the next instruction. In that case, we
discard that instruction and jump. It creates a waste of effort.

Advantages:

1. Pipelining boost performance.

2. Fetching and executing is done alongside at the same time.

3. Saves time.

Memory Segmentation
4. Fewer instruction cycles are required.

Segmentation involves logically dividing the computer’s main memory into distinct segments,
each with its own base address.

This technique aims to optimize the speed of computer system execution, enabling the processor
to efficiently retrieve and process data from memory. In the context of the Memory Segmentation
in 8086 Microprocessor, is a mechanism used to manage and organize the memory space.

The 8086 microprocessor employs a segmented memory model, where the entire 1 MB memory
space is divided into segments, and each segment is 64 KB in size. The combination of a segment
and an offset within that segment forms a physical address.

Memory Segmentation:
The Bus Interface Unit (BIU) contains four 16 bit special purpose registers (mentioned below)
called as Segment Registers.
● Code segment register (CS): is used for addressing memory location in the code segment of
the memory, where the executable program is stored.
● Data segment register (DS): points to the data segment of the memory where the data is stored.
● Extra Segment Register (ES): also refers to a segment in the memory which is another data
segment in the memory.
● Stack Segment Register (SS): is used for addressing stack segment of the memory. The stack
segment is that segment of memory which is used to store stack data.
The number of address lines in 8086 is 20, 8086 BIU will send 20bit address, so as to access one
of the 1MB memory locations. The four segment registers actually contain the upper 16 bits of the
starting addresses of the four memory segments of 64 KB each with which the 8086 is working at
that instant of time. A segment is a logical unit of memory that may be up to 64 kilobytes long.
Each segment is made up of contiguous memory locations. It is an independent, separately
addressable unit. Starting address will always be changing. It will not be fixed.
Note that the 8086 does not work the whole 1MB memory at any given time. However, it works
only with four 64KB segments within the whole 1MB memory.

Rules of Segmentation Segmentation process follows some rules as follows:

● The starting address of a segment should be such that it can be evenly divided by 16.
● Minimum size of a segment can be 16 bytes and the maximum can be 64 kB.

Advantages of the Segmentation

The main advantages of segmentation are as follows:
● It provides a powerful memory management mechanism.
● Data related or stack related operations can be performed in different segments.
● Code related operation can be done in separate code segments.
● It allows to processes to easily share data.
● It allows to extend the address ability of the processor, i.e. segmentation allows the use
of 16 bit registers to give an addressing capability of 1 Megabytes. Without
segmentation, it would require 20 bit registers.
Memory Address Generation
● It is possible to enhance the memory size of code data or stack segments beyond 64
KB by allotting more than one segment for each area.
Physical Address = Segment Address x 10H + Offset Address

A logical address:

is the address at which an item (memory cell, storage element) appears to reside from the perspective of an
executing application program. A logical address may be different from the physical address due to the operation of
an address translator or mapping function.

Effective Address or Offset Address: The offset for a memory operand is called the operand's effective address or
EA. It is an unassigned 16 bit number that expresses the operand's distance in bytes from the beginning of the
segment in which it resides. In 8086 we have base registers and index registers.

Generation of 20 bit physical address in 8086:-

1. Segment registers carry 16 bit data, which is also known as base address.

2. BIU appends four 0 bits to LSB of the base address. This address becomes 20-bit address.

3. Any base/pointer or index register carries 16 bit offset.

4. Offset address is added into 20-bit base address which finally forms 20 bit physical address of memory location

Problems on Physical Calculation:

 Physical Address = Segment Address x 10H + Offset Address

Decimal Hexadecimal
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 A
11 B
12 C
13 D
14 E
15 F
16 10
17 11
18 12
19 13
20 14
21 15
22 16
23 17
24 18

DS=345AH and SI=13DCH

Physical adress = DS*10H + SI

= 345AH * 10H + 13DCH

= 345A0+13DC

= 3597CH

Question 1
The value of Code Segment (CS) Register is 4042H and the value of different offsets is as follows:
BX: 2025H , IP: 0580H , DI: 4247H
Calculate the effective address of the memory location pointed by the CS register.

Question 2
Calculate the effective address for the following register:
SS: 3860H, SP: 1735H, BP: 4826H

Question 3
The value of the DS register is 3032H. And the BX register contains a 16 bit value which is equal to
3032H. 0008H is added to BX.
ADD BX, 0008H
The register AX contains some value which needs to be stored at a location as follows:
MOV [BX], AX
Calculate the address at which the value of the AX will be stored.

Question 4
You are provided the following values:
DS: 3056H, IP: 1023H, BP: 2322H and SP: 3029H
Can you calculate the effective address of the memory location as per the DS register?