If (Binary - Number1 & Binary - Number2) (Binary - Number1 Binary - Number1 )

1.
With suitable examples, explain how logical operators can be used to implement the
following applications.
(i) selective - complement (ii) selective-clear
Logical operators are commonly used in programming to implement various

applications and operations. Two common applications that can be implemented
using logical operators are selective complement and selective-clear.
(i) Selective-complement: This application involves inverting or complementing

specific bits in a binary number based on certain conditions. For example, consider a
scenario where you want to invert the bits in a binary number only when the
corresponding bits in another binary number are set to 1. This operation can be
implemented using logical AND and NOT operators as follows:
if (binary_number1 & binary_number2) {

binary_number1 = ~binary_number1;
}
In this code snippet, the logical AND operator (&) is used to check if the
corresponding bits in binary_number1 and binary_number2 are both set to 1. If this
condition is true, the NOT operator (~) is used to invert the bits in binary_number1.
(ii) Selective-clear: This application involves setting specific bits in a binary number to
0 based on certain conditions. For example, consider a scenario where you want to
clear the bits in a binary number only when the corresponding bits in another binary
number are set to 1. This operation can be implemented using logical AND operator
and complement as follows:
if (binary_number1 & binary_number2) {

binary_number1 = binary_number1 & ~binary_number2;
}
In this code snippet, the logical AND operator (&) is used to check if the corresponding bits
in binary_number1 and binary_number2 are both set to 1. If this condition is true, the
complement operator (~) is used to invert the bits in binary_number2, and then the AND
operator is used to set the corresponding bits in binary_number1 to 0.
2. Define and illustrate the following micro-operations with one example data.
(i) Logical Left Shift (ii) Circular Right Shift
1. Logical Shift:
It transfers the 0 zero through the serial input. We use the symbols ‘<<‘ for the logical left
shift and ‘>>‘ for the logical right shift.
Logical Left Shift:

In this shift, one position moves each bit to the left one by one. The Empty least significant
bit (LSB) is filled with zero (i.e, the serial input), and the most significant bit (MSB) is
rejected.
The left shift operator is denoted by the double left arrow key (<<). The general syntax for
the left shift is shift-expression << k.
Note: Every time we shift a number towards the left by 1 bit it multiplies that number by 2.
Circular Right Shift:

In this micro shift operation each bit in the register is shifted to the right one by one. After
shifting, the MSB becomes empty, so the value of the LSB is filled in there.
Each bit in the register is shifted to the right one by one in this shift micro-operation.
The least significant bit (LSB) is moved outside the register, and the place of the
most significant bit (MSB) is filled with 0.
For example, in the below data, there are 8 bits 00000101. When we perform a
logical shift right on these bits, all these bits will be shifted towards the right. The
LSB or the rightmost bit i.e. 1 will be moved outside, and at the leftmost place or
MSB, 0 will be inserted as shown below.
To implement the logical shift right micro-operation, we use the shr symbol.
For example, R1 -> shr R1.
This command means the 8 bits present in the R1 register will be logically shifted
right, and the result will be stored in register R1.
Logical right shift micro-operation generally denotes division by 2. The inputted bits
when converted into decimal form the number 5. And the outcome when converted
into decimal forms the number 2.
3. Define and illustrate the following micro-operations with one example data.
(i) Logical Right Shift (ii) Arithmetic Left Shift
Logical Right Shift
In this shift, each bit moves to the right one by one and the least significant bit(LSB) is
rejected and the empty MSB is filled with zero.
The right shift operator is denoted by the double right arrow key (>>). The general syntax for
the right shift is “shift-expression >> k”.
Note: Every time we shift a number towards the right by 1 bit it divides that
number by 2.
Arithmetic Left Shift:

In this shift, each bit is moved to the left one by one. The empty least significant bit (LSB) is
filled with zero and the most significant bit (MSB) is rejected. Same as the Left Logical Shift.
The arithmetic shift left micro-operation is the same as the logical shift left micro-operation.
Each bit in the register is shifted to the left one by one in this shift micro-operation. The most
significant bit (MSB) is moved outside the register, and the place of the least significant bit
(LSB) is filled with 0.
For example, in the below data, there are 8 bits 00100011. When we perform the arithmetic
shift left on these bits, all these bits will be shifted towards the left. The MSB or the leftmost
bit i.e. 0 will be moved outside, and at the rightmost place or LSB, 0 will be inserted as
shown below.
The given binary number (00100011) represents 35 in the decimal system. And the binary
number after logical shift left (01000110) represents 70 in a decimal system. Since 35 * 2 =
70. Therefore, we can say that the arithmetic shift left multiplies the number by 2.
To implement the arithmetic shift left micro-operation, we use the ashl symbol.
For example, R1 -> ashl R1.
This command means the 8 bits present in the R1 register will be arithmetic shifted left, and
the result will be stored in register R1.
4.Write detailed notes on the difference between single and multiple bus structures.
In computer architecture, buses are communication channels used to transfer data

and control signals between different components of a computer system. There are
two main types of bus structures: single bus and multiple bus structures.
Single Bus Structure: In a single bus structure, all components of the computer
system share a single bus, which is used to transfer data and control signals between
them. This means that multiple components are connected to the same bus and can
access it one at a time. The processor, memory, and I/O devices are all connected to
the single bus. This type of structure is simple and easy to design, but it can lead to
performance issues due to the limited bandwidth of the single bus. Also, as all
components share the same bus, access to it is serialized and can create contention
among different components.
Multiple Bus Structure: In a multiple bus structure, there are multiple buses used to
transfer data and control signals between different components of the computer
system. The different components of the system are connected to different buses,
which are used to transfer data and control signals between them. For example, the
processor is connected to the processor bus, while memory and I/O devices are
connected to the memory and I/O buses, respectively. This structure allows multiple
components to access their respective buses at the same time, which can lead to
increased performance and reduced contention among different components.
The primary difference between single and multiple bus structures is the number of
buses used to transfer data and control signals between the different components of
the computer system. In a single bus structure, all components are connected to a
single bus, while in a multiple bus structure, different components are connected to
different buses. The single bus structure is simpler to design, but can lead to
performance issues and contention among different components, while the multiple
bus structure allows for increased performance and reduced contention among
different components, but is more complex to design.
Overall, the choice of bus structure depends on the specific requirements and
constraints of the computer system being designed. Single bus structures are
suitable for simpler systems with lower performance requirements, while multiple bus
structures are more appropriate for complex systems that require high performance
and low contention among different components.
5.Define micro-operations and describe register transfer language and its different
notations with suitable Examples.
Micro-operations refer to basic operations that are performed on data stored in

registers within a computer system. These operations are used to manipulate data
and perform arithmetic or logical operations, such as addition, subtraction, shifting,
and masking.
Register transfer language (RTL) is a symbolic language used to describe the transfer
of data between registers in a computer system. RTL is used to describe the micro-
operations that are performed on the data in registers, as well as the control signals
that are used to control the flow of data between different parts of the system. RTL is
used to design the hardware implementation of computer systems, such as
processors and other digital circuits.
There are three different notations used in RTL:

1. Symbolic Notation: In symbolic notation, each micro-operation is represented
by a symbol or a combination of symbols. For example, the symbol "+" is used
to represent the addition operation, and the symbol "<<" is used to represent
a left shift operation.
2. Assembly Language Notation: Assembly language notation is similar to
symbolic notation but uses mnemonics instead of symbols to represent micro-
operations. For example, the mnemonic "ADD" is used to represent the
addition operation, and the mnemonic "SHL" is used to represent a left shift
operation.
3. Register Transfer Notation (RTN): RTN is a graphical notation that uses
symbols and arrows to represent the transfer of data between registers. For
example, an arrow pointing from one register to another represents the
transfer of data from one register to another.
Example: Let's consider an example of a micro-operation using RTL. Suppose we

want to perform an addition operation on two 8-bit binary numbers stored in
registers A and B, and store the result in register C. The RTL notation for this micro-
operation using symbolic notation would be:
C <- A + B
Using assembly language notation, this micro-operation can be written as:
ADD C, A, B
In RTN notation, the same micro-operation can be represented graphically as:
___________
| |
A ----> | |
| ADD | ----> C
B ----> |___________|
In this RTN diagram, an arrow pointing from register A to the ADD block represents the
transfer of data from register A to the input of the ADD block. Similarly, an arrow pointing
from register B to the ADD block represents the transfer of data from register B to the input
of the ADD block. Finally, an arrow pointing from the output of the ADD block to register C
represents the transfer of the result of the addition operation from the output of the ADD
block to register C.
6.Explain the design of an arithmetic unit of a computer supporting add, sub,

increment, decrement and transfer operations.
An arithmetic unit (ALU) is a digital circuit that performs arithmetic and logic
operations on binary numbers. The ALU is a crucial component of a computer
system, and its design must support various operations, such as addition,
subtraction, increment, decrement, and transfer.
The design of an ALU typically involves the use of combinational logic circuits that
perform arithmetic operations, such as addition and subtraction, and sequential
circuits that implement increment, decrement, and transfer operations.
Addition and Subtraction: The addition and subtraction operations can be

implemented using a combinational logic circuit, such as a full adder or a full
subtractor. The full adder takes three inputs: two operands (A and B) and a carry-in
(Cin), and produces two outputs: the sum (S) and a carry-out (Cout). Similarly, the full
subtractor takes three inputs: two operands (A and B) and a borrow-in (Bin), and
produces two outputs: the difference (D) and a borrow-out (Bout). These circuits can
be combined to create an ALU that supports both addition and subtraction
operations.
Increment and Decrement: The increment and decrement operations can be

implemented using sequential circuits, such as registers and counters. An increment
operation adds one to the value stored in a register or counter, while a decrement
operation subtracts one from the value stored in a register or counter. These
operations can be implemented using simple combinational logic circuits, such as an
adder or a subtractor, along with a clock signal and some flip-flops.
Transfer Operations: The transfer operations involve moving data between different
registers or memory locations. These operations can be implemented using
multiplexers and demultiplexers, which are combinational logic circuits that select
one of several input signals and route it to a single output signal. A multiplexer can
be used to select the input data to be transferred, while a demultiplexer can be used
to select the destination register or memory location.
In summary, the design of an ALU supporting add, sub, increment, decrement, and
transfer operations involves the use of combinational logic circuits for addition and
subtraction, sequential circuits for increment and decrement, and multiplexers and
demultiplexers for transfer operations. By combining these circuits, an ALU can be
designed to perform a wide range of arithmetic and logic operations necessary for a
computer system to function.
7. With suitable examples, explain how logical operators can be

used to implement the following applications.
(i) selective-set (ii) selective-clear
Selective-Set operation:
Logical operators are widely used in digital circuits to implement various operations.
Two such operations are selective-set and selective-clear, which can be implemented
using logical AND, OR, and NOT operations.
(i) Selective-Set: The selective-set operation sets (changes to 1) a specific bit in a

binary number while leaving all other bits unchanged. This operation is implemented
using a logical OR operation. Let's consider an example where we want to set the 3rd
bit of a binary number (in this case, a 4-bit number) to 1 while leaving all other bits
unchanged. The logic circuit for selective-set is shown below:
Input Output
A3 A2 A1 A0 B3 B2 B1 B0
---------------- ----------------
0 0 0 0 0 0 1 0
0 0 0 1 0 0 1 1
0 0 1 0 0 1 1 0
0 0 1 1 0 1 1 1
0 1 0 0 1 0 1 0
0 1 0 1 1 0 1 1
0 1 1 0 1 1 1 0
0 1 1 1 1 1 1 1
The output B3 will be 1 only when the 3rd input bit (A1) is 1. All other output bits will
be the same as their respective input bits.
(ii) Selective-Clear: The selective-clear operation clears (changes to 0) a specific bit in

a binary number while leaving all other bits unchanged. This operation is
implemented using a logical AND operation with the complement of the selected bit.
Let's consider an example where we want to clear the 2nd bit of a binary number (in
this case, a 4-bit number) to 0 while leaving all other bits unchanged. The logic circuit
for selective-clear is shown below:
Input Output
A3 A2 A1 A0 B3 B2 B1 B0
---------------- ----------------
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 0
0 0 1 1 0 0 1 1
0 1 0 0 0 1 0 0
0 1 0 1 0 1 0 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 1 1
The output B2 will be 0 only when the 2nd input bit (A2) is 1. All other output bits will be the
same as their respective
8. With suitable examples, explain how logical operators can be used to implement
the following applications.
(i) selective - clear (ii) Mask
Logical operators are widely used in digital circuits to implement various operations.
Two such operations are selective-clear and mask, which can be implemented using
logical AND, OR, and NOT operations.
(i) Selective-Clear: The selective-clear operation clears (changes to 0) a specific bit in

a binary number while leaving all other bits unchanged. This operation is
implemented using a logical AND operation with the complement of the selected bit.
Let's consider an example where we want to clear the 2nd bit of a binary number (in
this case, a 4-bit number) to 0 while leaving all other bits unchanged. The logic circuit
for selective-clear is shown below:
Input Output
A3 A2 A1 A0 B3 B2 B1 B0
---------------- ----------------
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 0
0 0 1 1 0 0 1 1
0 1 0 0 0 1 0 0
0 1 0 1 0 1 0 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 1 1
The output B2 will be 0 only when the 2nd input bit (A2) is 1. All other output bits will
be the same as their respective input bits.
(ii) Mask: The mask operation sets certain bits of a binary number to 0 and leaves all
other bits unchanged. This operation is implemented using a logical AND operation
with the selected bit positions set to 0. Let's consider an example where we want to
set the 3rd and 4th bits of a binary number (in this case, a 5-bit number) to 0 while
leaving all other bits unchanged. The logic circuit for mask is shown below:
Input Output
A4 A3 A2 A1 A0 B4 B3 B2 B1 B0
----------------- -----------------
0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 1
0 0 1 1 1 0 0 0 0 1
0 1 0 0 1 0 0 0 0 1
0 1 0 1 0 0 0 0 0 0
0 1 1 0 1 0 0 0 0 1
0 1 1 1
9.Describe the main functional units of a computer and their role in the functioning of
the computer.
A computer consists of several functional units that work together to perform various
tasks. The main functional units of a computer are:
1. Central Processing Unit (CPU): The CPU is the brain of the computer that
performs all the arithmetic, logic, and control functions of the computer. It
consists of three major components: the Arithmetic and Logic Unit (ALU), the
Control Unit (CU), and the Registers. The ALU performs arithmetic and logic
operations, the CU controls the flow of data between the CPU and other parts
of the computer, and the registers store data that the CPU is currently working
on.
2. Memory Unit: The memory unit stores data and instructions that are currently
being used by the CPU. It consists of two types of memory: Primary Memory
(RAM) and Secondary Memory (hard disk, CD/DVD drive, USB drive, etc.). RAM
is volatile memory that is used to store data and instructions temporarily while
the computer is running, while secondary memory is non-volatile memory that
is used for long-term storage.
3. Input Unit: The input unit is responsible for receiving data and instructions
from the user or external devices such as the keyboard, mouse, scanner,
microphone, etc. The input unit converts the input data into a form that can
be processed by the computer.
4. Output Unit: The output unit is responsible for displaying the results of the
processing to the user or external devices such as the printer, monitor,
speakers, etc. The output unit converts the processed data into a form that
can be understood by the user.
5. Control Unit: The control unit manages the flow of data and instructions
between the CPU, memory, input, and output devices. It interprets instructions
from the memory unit, decodes them, and sends the necessary signals to the
CPU, memory, input, and output devices to execute the instructions.
6. Secondary Storage Unit: The secondary storage unit is used to store data and
instructions that are not currently being used by the CPU. It consists of devices
such as hard disks, CD/DVD drives, USB drives, etc. that provide long-term
storage for data and instructions.
All of these functional units work together to process data and instructions and
perform various tasks. The CPU performs all the arithmetic and logic operations on
the data, while the memory unit stores the data and instructions that the CPU is
currently using. The input unit receives data and instructions from the user, and the
output unit displays the results of the processing to the user. The control unit
manages the flow of data and instructions between these units, while the secondary
storage unit provides long-term storage for data and instructions.
10.Explain about stored-program architecture with the help of a block diagram.

Stored-program architecture refers to the design of a computer system in which
instructions and data are stored in the same memory and treated as the same type of
information. The stored-program architecture is the basis for most modern
computers.
The stored-program architecture is implemented using a block diagram that consists

of several components, including:
on.
2. Memory Unit: The memory unit stores data and instructions that are currently
being used by the CPU. It consists of two types of memory: Primary Memory
(RAM) and Secondary Memory (hard disk, CD/DVD drive, USB drive, etc.). RAM
3. Input/Output Devices: Input/output devices such as the keyboard, mouse,
monitor, and printer are used to input data and instructions into the computer
and to output processed data.
4. System Bus: The system bus is a communication pathway that connects the
CPU, memory, and input/output devices.
5. Program Counter: The program counter is a register that stores the address of
the next instruction to be executed by the CPU.
6. Instruction Register: The instruction register is a register that holds the current
instruction being executed by the CPU.
7. Memory Address Register: The memory address register is a register that
holds the memory address of the data or instruction being accessed by the
CPU.
8. Memory Buffer Register: The memory buffer register is a register that holds
the data being transferred between the CPU and memory.
The stored-program architecture block diagram shows how the CPU, memory,
input/output devices, and system bus are interconnected. The program counter
holds the address of the next instruction to be executed, and the instruction register
holds the current instruction being executed. The memory address register holds the
memory address of the data or instruction being accessed, and the memory buffer
register holds the data being transferred between the CPU and memory.
Overall, the stored-program architecture allows for efficient and flexible
programming of computers, as the same memory can be used to store both data
and instructions. The use of a program counter and instruction register allows for the
CPU to execute instructions in a sequential and orderly manner.
11.Define a digital computer and describe in detail the different high level functional
units of a computer.
A digital computer is an electronic device that is capable of processing digital data

and performing various arithmetic and logical operations on that data. It is a general-
purpose machine that can be programmed to perform a wide variety of tasks.
The high-level functional units of a computer can be broadly classified into four main
categories:
1. Input/output (I/O) devices: These devices are used to input data and
instructions into the computer and to output processed data. Examples of
input devices include the keyboard, mouse, scanner, and microphone, while
examples of output devices include the monitor, printer, and speakers.
2. Memory: Memory is used to store data and instructions that are currently
being used by the computer. There are two types of memory: primary memory
(RAM) and secondary memory (hard disk, CD/DVD drive, USB drive, etc.). RAM
on.
4. System Bus: The system bus is a communication pathway that connects the
CPU, memory, and input/output devices. It allows data and instructions to be
transferred between these different functional units.
The functional units of a computer work together to perform various tasks. For
example, when a user types a letter on the keyboard, the input device sends the data
to the CPU, which stores the data in memory. The CPU then retrieves the data from
memory and sends it to the output device, which displays the letter on the monitor.
Overall, the high-level functional units of a digital computer are designed to work
together in a coordinated manner to process data and perform tasks. Each functional
unit has a specific role to play in the overall functioning of the computer.
12.List and describe any 3 common software tools you would normally find in any
computer.
Here are three common software tools you would normally find in any computer:
1. Operating System: An operating system (OS) is a software program that

manages computer hardware and software resources and provides common
services for computer programs. It provides a user interface to interact with
the computer and manages various tasks such as memory management, disk
management, process management, and security.
2. Web Browser: A web browser is a software application that allows users to
access and view web pages on the internet. It interprets HTML code, displays
the content of the web pages, and enables users to navigate through different
web pages by clicking on links.
3. Office Suite: An office suite is a collection of productivity software applications
that are commonly used in an office environment. It typically includes a word
processor, spreadsheet, presentation software, and email client. These tools
are used for creating, editing, and sharing documents, spreadsheets,
presentations, and emails. Some popular office suites include Microsoft Office,
Google Workspace, and LibreOffice.
Overall, these software tools are essential for any computer user to perform basic
tasks, browse the internet, and perform office work.
13.Classify the computers based on their size & portability and describe each of the
classes of computer.
Computers can be classified based on their size and portability into the following
categories:
1. Supercomputers: Supercomputers are the most powerful and expensive

computers that are used for complex scientific and engineering simulations,
weather forecasting, and research projects. They are typically housed in large
data centers and require special cooling systems. Supercomputers have
massive processing power, high-speed memory, and a large number of
processors, allowing them to perform calculations and simulations at
extremely high speeds.
2. Mainframe Computers: Mainframe computers are large computers that are
designed to handle large-scale computing tasks and manage massive
amounts of data for organizations. They are typically used by banks,
government agencies, and large corporations for mission-critical applications
such as transaction processing, database management, and enterprise
resource planning.
3. Mini Computers: Mini computers are smaller and less powerful than
mainframe computers, but still more powerful than personal computers. They
are typically used by small to medium-sized businesses for running software
applications, managing databases, and performing other computing tasks.
Mini computers are less expensive than mainframes and are designed to
handle multiple users simultaneously.
4. Personal Computers (PCs): Personal computers, also known as desktop
computers or laptops, are the most common type of computer used by
individuals and small businesses. They are designed to be affordable and
provide computing power for general-purpose tasks such as word processing,
browsing the internet, and running software applications.
5. Tablet Computers: Tablet computers are portable computing devices that are
designed for easy mobility and use with a touchscreen interface. They are
typically smaller and lighter than laptops and are used for tasks such as
browsing the internet, reading e-books, and watching videos.
6. Smartphones: Smartphones are handheld computing devices that are
designed for communication and entertainment. They have advanced
computing capabilities and are used for tasks such as making phone calls,
sending text messages, browsing the internet, and running mobile
applications.
Overall, computers can be classified based on their size and portability into several
categories, each with their own unique features and applications.
14.Explain Von-Neumann (Stored-program) architecture with the help of a block

diagram.
Von-Neumann architecture, also known as the stored-program architecture, is a

computer architecture model that is based on the concept of storing program
instructions and data in the same memory. This architecture was proposed by
mathematician and computer scientist John von Neumann in 1945.
The block diagram of Von-Neumann architecture consists of the following

components:
1. CPU (Central Processing Unit): It is the brain of the computer that performs all
the processing tasks. The CPU consists of two main parts: the Arithmetic Logic
Unit (ALU) and the Control Unit (CU).
2. Memory: It is used to store data and program instructions. Memory is divided
into two types: Primary Memory (RAM) and Secondary Memory (hard disks,
CDs, DVDs, etc.). The CPU fetches instructions and data from memory and
stores the results back into memory.
3. Input/Output Devices: These devices are used to communicate with the
outside world. Examples include keyboards, mice, monitors, printers, and
speakers.
4. System Bus: It is a communication pathway that connects all the components
of the computer, allowing them to exchange data and instructions. The system
bus is divided into three parts: the data bus, the address bus, and the control
bus.
The Von-Neumann architecture operates using a stored-program concept, where

instructions and data are stored in the same memory and are treated the same way.
The CPU fetches an instruction from memory, decodes it to determine what
operation needs to be performed, and then executes it. The results of the operation
are stored back into memory.
The block diagram of Von-Neumann architecture is shown below:
+---------------------+
| Input/Output |
| Devices |
+---------------------+
+---------------------+
| Memory |
+---------------------+
+---------------------+
| CPU |
+---------------------+
+---------------------+
| System Bus |
+---------------------+
Overall, Von-Neumann architecture is a widely used computer architecture that provides a

simple and efficient way of executing programs and performing data processing tasks.
15.Design & describe an arithmetic unit for a computer that would perform add, sub,
increment, decrement and transfer operations depending on the selection given using
selection lines.
An arithmetic unit is a key component of a computer that performs arithmetic operations
such as addition, subtraction, increment, decrement, and transfer. The following is a design
for an arithmetic unit that can perform these operations based on selection lines:
+---------------------+
| Input Lines |
+---------------------+
|
+---------------------+
| Arithmetic |
| Unit |
+---------------------+
|
+---------------------+
| Selection Lines |
+---------------------+
The input lines of the arithmetic unit would consist of the two operands (A and B)
and a carry-in bit (CIN) for addition and subtraction operations. The output lines
would consist of the result (R) and a carry-out bit (COUT) for addition and
subtraction operations.
The selection lines would be used to select the desired operation to be performed.
The following selection lines could be used:
 ADD: When this line is high, the arithmetic unit performs an addition
operation. The output lines would contain the sum of A and B.
 SUB: When this line is high, the arithmetic unit performs a subtraction
operation. The output lines would contain the difference of A and B.
 INC: When this line is high, the arithmetic unit performs an increment
operation. The output lines would contain the value of A + 1.
 DEC: When this line is high, the arithmetic unit performs a decrement
operation. The output lines would contain the value of A - 1.
 TRANSFER: When this line is high, the arithmetic unit performs a transfer
operation. The output lines would contain the value of A.
The arithmetic unit can be designed using combinational logic circuits. The following
is an example of how the combinational logic circuits can be designed for the
arithmetic unit:
1. ADD operation:
COUT = A + B + CIN > 1
R = A + B + CIN
2. SUB operation:
COUT = A - B - CIN < 0
R = A - B – CIN
3. INC operation:
COUT = A + 1 > MAX_VALUE
R =A+ 1
4. DEC operation:
COUT = A - 1 < 0
R =A–1
5. TRANSFER operation:
COUT = 0
R =A
Overall, this arithmetic unit can perform various arithmetic operations based on the selection
lines provided, making it a versatile and useful component of a computer.
16.Explain about the various shift micro-operations with a neat circuit diagram.
Shift micro-operations are fundamental operations in digital circuits that shift the bits of a binary
number to the left or right by a specified number of positions. The following are the main types
of shift micro-operations:
1. Logical Left Shift

2. Logical Right Shift
3. Arithmetic Left Shift
4. Arithmetic Right Shift
5. Circular Left Shift
6. Circular Right Shift
The circuit diagram for each type of shift micro-operation is shown below:
1. Logical Left Shift: A logical left shift moves all the bits in a binary number to the left by a
specified number of positions. The vacant bit positions are filled with 0s.
2. Logical Right Shift: A logical right shift moves all the bits in a binary number to the right
by a specified number of positions. The vacant bit positions are filled with 0s.
3. Arithmetic Left Shift: An arithmetic left shift moves all the bits in a binary number to the
left by a specified number of positions. The vacant bit positions are filled with 0s
4. Arithmetic Right Shift: An arithmetic right shift moves all the bits in a binary number to
the right by a specified number of positions. The vacant bit positions are filled with the
sign bit (the most significant bit) of the original number.
5. Circular Left Shift: A circular left shift moves all the bits in a binary number to the left by a
specified number of positions. The most significant bit is shifted to the least significant bit
position.
UNIT 2
1.
START -> Fetch Instruction -> Decode Instruction ->
Execute Instruction -> Store Result -> Repeat
1. Fetch Instruction: In this phase, the CPU fetches the next instruction from
memory using the program counter (PC) register. The PC points to the
memory location of the next instruction to be executed.
2. Decode Instruction: In this phase, the CPU decodes the instruction fetched in
the previous phase to determine the operation that needs to be performed
and the operands involved. This phase involves identifying the opcode and
any operands that follow it.
3. Execute Instruction: In this phase, the CPU executes the instruction according
to the operation identified in the previous phase. This could involve arithmetic
or logical operations, data transfers, or jumps to other instructions in the
program.
4. Store Result: In this phase, the CPU stores the result of the instruction
execution, if any, in the appropriate location in memory or a register.
5. Repeat: The cycle then repeats, with the program counter incrementing to the
next instruction address, and the process starting again with the fetch phase.
2. Explain the concept of Timing and Control with suitable
block diagram.
o Timing and control are two essential concepts in the design and operation of
digital systems. The timing and control block diagram helps to illustrate how
these concepts work together to ensure the correct and efficient operation of
a digital system.
o Here is a block diagram showing the relationship between timing and control
in a digital system:
+-------------------+
| Clock |
+-------------------+
+-------------------+
| Timing |
+-------------------+
+-------------------+
| Control |
+-------------------+
+-------------------+
| Digital Logic |
+-------------------+
Clock: The clock is an external signal that provides a regular timing reference to the
digital system. It is typically a square wave that oscillates between two voltage levels.
The frequency and duty cycle of the clock determine the timing characteristics of the
system.
Timing: The timing block generates various signals that define the timing
relationships between different parts of the digital system. This includes signals such
as clock enables, strobes, and delays. These signals help to ensure that signals are
stable and valid before they are processed by the digital logic.
Control: The control block generates control signals that manage the operation of
the digital system. This includes signals such as enable, reset, and interrupt signals.
The control signals ensure that the digital logic performs the desired operation in the
correct sequence and with the appropriate timing.
Digital Logic: The digital logic block contains the actual logic gates, flip-flops, and
other digital components that perform the processing and computation of the
system. The digital logic responds to the timing and control signals to perform the
desired operation.
Together, the timing and control signals ensure that the digital system operates
correctly and efficiently. The timing signals ensure that data is stable and valid before
processing, and the control signals ensure that the digital logic operates in the
correct sequence and timing to perform the desired operation.
3.Explain about the memory reference instructions with the help of

various memory reference instructions on basic computer.
Memory reference instructions are a type of instruction in computer architecture that
allow a program to access data stored in memory. The Basic Computer (also known
as the SAP-1) is a simple computer architecture that provides a good example of how
memory reference instructions work. Let's take a look at some of the memory
reference instructions on the Basic Computer:
1. LOAD: The LOAD instruction loads a value from a memory location into the
accumulator. The memory address is specified as an operand of the
instruction. For example, the instruction LDA 100 would load the value stored in
memory location 100 into the accumulator.
2. STORE: The STORE instruction stores a value from the accumulator into a
memory location. The memory address is specified as an operand of the
instruction. For example, the instruction STA 200 would store the value in the
accumulator into memory location 200.
3. ADD: The ADD instruction adds a value from a memory location to the value
in the accumulator and stores the result back in the accumulator. The memory
address is specified as an operand of the instruction. For example, the
instruction ADD 300 would add the value stored in memory location 300 to the
value in the accumulator.
4. SUB: The SUB instruction subtracts a value from a memory location from the
value in the accumulator and stores the result back in the accumulator. The
memory address is specified as an operand of the instruction. For example,
the instruction SUB 400 would subtract the value stored in memory location
400 from the value in the accumulator.
5. LOAD IMMEDIATE: The LOAD IMMEDIATE instruction loads a value directly
into the accumulator without accessing memory. The value is specified as an
operand of the instruction. For example, the instruction LXI 10 would load the
value 10 into the accumulator.
These instructions illustrate how a program can access and manipulate data stored in
memory. The LOAD and STORE instructions allow a program to move data between
memory and the accumulator, while the ADD and SUB instructions allow a program
to perform arithmetic operations on data stored in memory. The LOAD IMMEDIATE
instruction provides a way to load a constant value into the accumulator without
accessing memory.
Overall, memory reference instructions are an essential part of computer architecture,

providing a way for programs to store, retrieve, and manipulate data stored in
memory.
4.Explain about the register reference instructions with the help

of various register reference instructions on basic computer.
Register reference instructions are a type of instruction in computer architecture that
allow a program to access and manipulate data stored in registers. The Basic
Computer (also known as the SAP-1) is a simple computer architecture that provides
a good example of how register reference instructions work. Let's take a look at
some of the register reference instructions on the Basic Computer:
1. MOVE: The MOVE instruction moves a value from one register to another
register. The source register and the destination register are specified as
operands of the instruction. For example, the instruction MOV B, A would move
the value in register A to register B.
2. LOAD: The LOAD instruction loads a value from memory into a register. The
memory address and the register to be loaded are specified as operands of
the instruction. For example, the instruction LDA 100 would load the value
stored in memory location 100 into register A.
3. STORE: The STORE instruction stores a value from a register into memory. The
memory address and the register to be stored are specified as operands of the
instruction. For example, the instruction STA 200 would store the value in
register A into memory location 200.
4. ADD: The ADD instruction adds a value from a register to the value in the
accumulator and stores the result back in the accumulator. The register to be
added is specified as an operand of the instruction. For example, the
instruction ADD B would add the value in register B to the value in the
accumulator.
5. SUB: The SUB instruction subtracts a value from a register from the value in
the accumulator and stores the result back in the accumulator. The register to
be subtracted is specified as an operand of the instruction. For example, the
instruction SUB C would subtract the value in register C from the value in the
accumulator.
These instructions illustrate how a program can access and manipulate data stored in
registers. The MOVE instruction allows a program to move data between registers,
while the LOAD and STORE instructions allow a program to move data between
memory and registers. The ADD and SUB instructions allow a program to perform
arithmetic operations on data stored in registers.
Overall, register reference instructions are an essential part of computer architecture,

providing a fast and efficient way for programs to access and manipulate data stored
in registers.
5. Explain in detail a simple I/0 configuration and computer

using FGI and FGO and how input output instructions can be
used to read input and send output.
In computer architecture, input/output (I/O) operations are essential for a computer
system to interact with the outside world. The Basic Computer (also known as the
SAP-1) is a simple computer architecture that provides a good example of how I/O
operations can be implemented using a simple configuration of input and output
devices and the FGI (Flip-Flop Input) and FGO (Flip-Flop Output) signals.
The basic I/O configuration of the Basic Computer consists of two input devices (IN1
and IN2) and two output devices (OUT1 and OUT2). These devices are connected to
the computer system through a set of input and output ports, as shown in the
following diagram:
+--------+ +--------+
| | | |
| IN1 | | OUT1 |
| | | |
+--------+ +--------+
| |
+---------------+
Input/Output
Ports
+---------------+
| |
+--------+ +--------+
| | | |
| IN2 | | OUT2 |
| | | |
+--------+ +--------+
To perform input and output operations, the Basic Computer uses two flip-flops: the
FGI (Flip-Flop Input) and the FGO (Flip-Flop Output). The FGI is used to signal when
an input device is ready to provide data to the computer system, while the FGO is
used to signal when an output device is ready to receive data from the computer
system.
When an input device is ready to provide data, it sets the FGI signal to 1. The
computer system can then use an input instruction (such as the IN instruction) to
read the data from the input port and store it in a register. The computer system can
also use an output instruction (such as the OUT instruction) to send data to an
output device. When the output device is ready to receive data, it sets the FGO signal
to 1.
Here is an example of how input and output instructions can be used to read input
and send output:
1. Assume that input device IN1 is ready to provide data and has set the FGI
signal to 1.
2. The computer system can use the IN instruction to read the data from the
input port and store it in a register. For example, the instruction IN 1 would
read data from input device IN1 and store it in register 1.
3. The computer system can then perform some operation on the data in
register 1 (such as adding or subtracting) and store the result in another
register.
4. The computer system can use the OUT instruction to send the result to an
output device. For example, the instruction OUT 2 would send the contents of
register 2 to output device OUT2.
5. When output device OUT2 is ready to receive data, it sets the FGO signal to 1.
The computer system can then use the OUT instruction again to send more
data, if necessary.
Overall, the use of input and output instructions and the FGI and FGO signals
provides a simple and effective way for a computer system to interact with input and
output devices.
6. Describe in brief with a flow chart the interrupt cycle of a computer.

The interrupt cycle is an important part of a computer's operation, allowing it to handle
external events that may require immediate attention. The following is a brief description of
the interrupt cycle, along with a flow chart to illustrate the process.
1. Interrupt Request (IRQ) Occurs: An external device sends an interrupt request signal
to the computer.
2. CPU Interrupt: The CPU responds to the interrupt request by stopping its current
operation and saving the current state of the system.
3. Interrupt Acknowledge: The CPU sends an acknowledge signal to the device that
requested the interrupt to indicate that it has been received.
4. Interrupt Service Routine (ISR) Execution: The CPU executes the ISR, which is a
specific set of instructions designed to handle the interrupt request. The ISR may
involve reading or writing data, changing system settings, or performing other tasks as
needed.
5. Return from Interrupt (RTI): Once the ISR is complete, the CPU returns to the
previous state of the system and resumes its normal operation.
Here is a flow chart illustrating the interrupt cycle:
+-----------------+
| |
| External Device | 1. Interrupt Request (IRQ) Occurs
| |
+-----------------+
|
|
V
+--------------+
| |
| CPU | 2. CPU Interrupt
| |
+--------------+
|
|
V
+--------------+
| |
| CPU | 3. Interrupt Acknowledge
| |
+--------------+
|
|
V
+---------------+
| |
| ISR | 4. ISR Execution
| |
+---------------+
|
|
V
+--------------+
| |
| CPU | 5. Return from Interrupt (RTI)
| |
+--------------+
Overall, the interrupt cycle allows a computer to quickly and efficiently handle
external events that may require immediate attention, helping to improve the overall
performance and functionality of the system.
7. Show how the operation X= (A*B}+(C*D) can be implemented using

Zero Address instructions and one address instructions.
Zero Address Instructions: In zero address instructions, the operand is implied and is
present in the top of the stack. The result of the operation is also left on the top of
the stack.
Assuming that the values of A, B, C, and D are already present in the stack, the
following zero address instructions can be used to perform the operation
X=(AB)+(CD):
mul ; Multiply the top two values in the stack (B*A)

swap ; Swap the top two values in the stack (A*B)
mul ; Multiply the top two values in the stack (D*C)
add ; Add the top two values in the stack (C*D)
add ; Add the top two values in the stack ((A*B)+(C*D))
One Address Instructions: In one address instructions, the operand is present in the
accumulator register. The result of the operation is also stored in the accumulator
register.
Assuming that the values of A, B, C, and D are already present in the accumulator
register, the following one address instructions can be used to perform the operation
X=(AB)+(CD):
mul B ; Multiply the accumulator register by B (A*B)

mov D ; Move the value of D to the accumulator register (D)
mul ; Multiply the accumulator register by the value in D (C*D)
add ; Add the accumulator register to the result of (A*B)
((A*B)+(C*D))
Overall, both zero address and one address instructions can be used to perform the
given operation. However, the choice between the two may depend on the specific
hardware architecture and instruction set of the computer system being used.
8. Describe in brief about register stack and memory stack in a stack

organized computer.
In a stack-organized computer architecture, a stack is a data structure that is used to
store and retrieve data. The stack is implemented in either registers or memory, and
there are two types of stacks: register stack and memory stack.
1. Register Stack: A register stack is a type of stack where the data is stored in a
set of registers. The top of the stack is identified by a pointer called the stack
pointer (SP), which points to the last item pushed onto the stack. The register
stack is used to store frequently used data, such as function arguments, return
addresses, and intermediate results. The advantage of a register stack is that it
allows for fast access to the top of the stack since it is located in registers,
which have a shorter access time compared to memory. However, the size of
the register stack is limited by the number of available registers in the system.
2. Memory Stack: A memory stack is a type of stack where the data is stored in
the main memory of the computer. The top of the stack is identified by a
pointer called the stack pointer (SP), which points to the last item pushed onto
the stack. The memory stack is used to store data that is not frequently used
or does not fit into the limited number of registers available in the system. The
advantage of a memory stack is that it can store a large amount of data, but
the disadvantage is that accessing the data in memory is slower compared to
accessing data in registers.
In summary, a stack-organized computer architecture can use either a register stack

or a memory stack to implement a stack data structure. The choice between the two
types of stacks depends on the specific requirements of the system, including the
size and frequency of data access.
9. List and explain the flags Sign Flag, Overflow Flag, Zero Flag, and
Carry Flag and how they are used.
In computer architecture, flags are special bits that are set or reset by the CPU to
indicate the outcome of an arithmetic or logical operation. Flags are typically stored
in a register called the flags register or the status register. There are several flags
used in computer architecture, including the Sign Flag, Overflow Flag, Zero Flag, and
Carry Flag.
1. Sign Flag (SF): The Sign Flag is set when the result of an arithmetic or logical
operation is negative. Specifically, the Sign Flag is set to 1 when the most
significant bit of the result is 1, indicating that the result is negative. The Sign
Flag is used for signed arithmetic operations and is often used in conditional
jump instructions.
2. Overflow Flag (OF): The Overflow Flag is set when the result of an arithmetic
operation exceeds the range that can be represented by the data type being
used. Specifically, the Overflow Flag is set to 1 when the result of a signed
arithmetic operation is outside the range of the data type being used. The
Overflow Flag is used to detect errors in arithmetic operations and is often
used in conditional jump instructions.
3. Zero Flag (ZF): The Zero Flag is set when the result of an arithmetic or logical
operation is zero. Specifically, the Zero Flag is set to 1 when the result of an
operation is equal to zero. The Zero Flag is used in conditional jump
instructions to test whether the result of an operation is zero.
4. Carry Flag (CF): The Carry Flag is set when the result of an arithmetic operation
generates a carry-out. Specifically, the Carry Flag is set to 1 when an addition
operation generates a carry-out or when a subtraction operation requires a
borrow. The Carry Flag is used for unsigned arithmetic operations and is often
used in conditional jump instructions.
In summary, the Sign Flag, Overflow Flag, Zero Flag, and Carry Flag are used to
indicate the outcome of arithmetic or logical operations in computer architecture.
These flags are set or reset by the CPU and are often used in conditional jump
instructions to make decisions based on the outcome of previous operations.
10. Write short notes on the following instructions with their micro-
operations.
(i) Branch Unconditionally to a given Address (BUN X)
(ii) Branch and Save Address (BSA X)
(i) Branch Unconditionally to a given Address (BUN X): The BUN instruction is used to
transfer control to a specific memory location unconditionally. The instruction takes
an operand X, which specifies the memory address to which the control should be
transferred. The micro-operations performed by the BUN instruction are:
1. Copy the contents of operand X to the program counter (PC).

2. Fetch the instruction at the memory location specified by the new value of the
PC.
3. Increment the PC to point to the next instruction.
(ii) Branch and Save Address (BSA X): The BSA instruction is used to transfer control
to a specific memory location and save the return address. The instruction takes an
operand X, which specifies the memory address to which the control should be
transferred. The micro-operations performed by the BSA instruction are:
1. Decrement the stack pointer (SP) by 1.

2. Copy the current value of the program counter (PC) to the memory location
pointed to by the new value of the SP.
3. Copy the contents of operand X to the PC.
4. Fetch the instruction at the memory location specified by the new value of the
PC.
5. Increment the PC to point to the next instruction.
The BSA instruction saves the return address on the stack before transferring control
to the specified memory location. When the called subroutine is finished executing, it
uses the return instruction (RET) to transfer control back to the instruction following
the BSA instruction. The RET instruction pops the return address from the stack and
copies it to the PC.
11. Write short notes on RISC characteristics.

RISC (Reduced Instruction Set Computing) is a type of computer architecture that
emphasizes simplicity and efficiency. RISC processors typically have a smaller set of
simple and fast instructions that are designed to execute quickly, with minimal cycles
per instruction. Here are some of the key characteristics of RISC architecture:
1. Simple instructions: RISC processors have a smaller set of simple instructions

that perform basic operations. These instructions are typically fixed in length
and execute in a single cycle, which makes them faster.
2. Load-store architecture: In RISC architecture, memory access is performed
only through load and store instructions. This means that data must be loaded
into registers before it can be operated on, and the results must be stored
back to memory after the operation.
3. Large number of registers: RISC processors typically have a larger number of
registers compared to CISC (Complex Instruction Set Computing) processors.
This reduces the number of memory accesses required, which improves
performance.
4. Pipelining: RISC processors use pipelining to execute multiple instructions
simultaneously. This means that while one instruction is being executed, the
next instruction is being fetched, and the instruction after that is being
decoded.
5. Reduced number of addressing modes: RISC processors typically have a
smaller number of addressing modes, which simplifies the instruction set and
reduces the complexity of the processor.
6. Hardwired control: RISC processors use hardwired control instead of
microcode, which simplifies the design and improves performance.
In summary, RISC architecture emphasizes simplicity, efficiency, and speed. The use
of simple instructions, load-store architecture, a large number of registers, pipelining,
and hardwired control are some of the key characteristics of RISC processors.
12. Write short notes on CISC characteristics.

CISC (Complex Instruction Set Computing) is a type of computer architecture that
emphasizes complex and powerful instructions that can perform multiple operations
in a single instruction. Here are some of the key characteristics of CISC architecture:
1. Large instruction set: CISC processors have a larger and more complex
instruction set compared to RISC (Reduced Instruction Set Computing)
processors. This means that the instructions can perform multiple operations
in a single instruction.
2. Memory access through instructions: CISC processors allow memory access
through instructions, which means that the instructions themselves can
perform load and store operations.
3. Variable length instructions: CISC instructions are typically variable in length,
which means that some instructions may take longer to execute than others.
4. Multiple addressing modes: CISC processors support multiple addressing
modes, which allows the instructions to access memory in a variety of ways.
5. Microcode control: CISC processors use microcode to control the execution of
instructions. Microcode is a layer of software that translates complex
instructions into simpler micro-operations that can be executed by the
hardware.
6. Emphasis on hardware-based optimization: CISC processors use hardware-
based optimization techniques such as pipelining, caching, and out-of-order
execution to improve performance.
In summary, CISC architecture emphasizes complex and powerful instructions that

can perform multiple operations in a single instruction. The use of a large instruction
set, memory access through instructions, variable length instructions, multiple
addressing modes, microcode control, and hardware-based optimization are some of
the key characteristics of CISC processors.
13. Distinguish between hardwired control unit and micro-programmed

control unit.
The control unit is responsible for directing the operations of a computer's processor.
There are two main types of control units: hardwired control unit and micro-
programmed control unit. Here are the key differences between the two:
1. Implementation: A hardwired control unit is implemented using combinational

logic gates and flip-flops, while a micro-programmed control unit is
implemented using a control store that contains microcode.
2. Flexibility: A micro-programmed control unit is more flexible than a hardwired
control unit. It can be easily reprogrammed by changing the microcode stored
in the control store, whereas a hardwired control unit requires changes to the
underlying hardware.
3. Complexity: A micro-programmed control unit is more complex than a
hardwired control unit, as it requires additional memory to store the
microcode.
4. Debugging: Debugging a hardwired control unit can be difficult, as errors in
the logic gates or flip-flops can be hard to diagnose. In contrast, a micro-
programmed control unit can be debugged by examining the microcode
stored in the control store.
5. Execution speed: A hardwired control unit can execute instructions faster than
a micro-programmed control unit, as it does not require the additional time
needed to fetch and execute microcode.
In summary, a hardwired control unit is implemented using combinational logic

gates and flip-flops, and is faster but less flexible than a micro-programmed control
unit. A micro-programmed control unit is implemented using a control store that
contains microcode, and is more flexible but slower than a hardwired control unit.
14. Explain the concept of address sequencing in a micro-programmed

control unit design and elaborate the different possibilities for next
address.
In a micro-programmed control unit, the control logic that directs the operations of
the processor is implemented using microcode stored in a control store. The
microcode is a set of instructions that specify the operations to be performed by the
processor, and each instruction is represented by a unique address in the control
store.
Address sequencing refers to the process of determining the next microcode address
to be fetched and executed. The micro-programmed control unit can use different
methods for address sequencing, depending on the design and requirements. Some
of the possibilities for next address are:
1. Sequential Addressing: In this method, the next microcode address is simply

the next address in sequence after the current address. This is the simplest
method of address sequencing and is used when the microcode is organized
in a linear fashion.
2. Conditional Jump: In this method, the next address is determined based on
the outcome of a conditional test. For example, if a comparison operation
results in a true condition, the next address may be set to a specific address in
the control store to perform a certain operation.
3. Unconditional Jump: In this method, the next address is determined by a jump
instruction that specifies a particular address to be executed next. This method
is useful for implementing subroutines or loops in the microcode.
4. Indexed Addressing: In this method, the next address is determined by adding
an index value to the current address. This method allows the microcode to
access different portions of the control store based on the value of an index
register.
5. Return Address: In this method, the next address is determined by a return
instruction that specifies the address to be executed after a subroutine call is
completed. This method is used to implement subroutines and is similar to the
unconditional jump method.
In summary, address sequencing is the process of determining the next microcode

address to be executed in a micro-programmed control unit. The next address can
be determined using various methods such as sequential addressing, conditional and
unconditional jumps, indexed addressing, and return addresses. The choice of
address sequencing method depends on the specific requirements of the microcode
design.
15. Explain about the microprogram sequencer for a control memory

with a neat sketch.
The microprogram sequencer is a component of the control unit in a computer
system that is responsible for generating the next microinstruction address to be
executed. It is also known as the control memory address register or the control
address register. The microprogram sequencer takes inputs from the instruction
register, status registers, and other control signals to determine the next
microinstruction to be executed.
Here is a brief explanation of the microprogram sequencer with a neat sketch:
1. Input Registers: The microprogram sequencer receives inputs from various

registers in the control unit. These inputs include the instruction register (IR),
status registers (SR), and other control signals.
2. Control Memory: The control memory contains the microinstructions that are
executed by the processor. Each microinstruction is stored at a unique address
in the control memory.
3. Address Register: The microprogram sequencer has an address register that
holds the address of the next microinstruction to be executed.
4. Next Address Calculation: The microprogram sequencer calculates the next
address based on the inputs received from the input registers. The next
address is calculated using various methods such as sequential addressing,
conditional and unconditional jumps, indexed addressing, and return
addresses.
5. Address Selection: The microprogram sequencer selects the next address
based on the next address calculation.
6. Output Register: The microprogram sequencer has an output register that
stores the next address to be executed.
7. Control Signals: The output register sends control signals to other
components of the control unit, indicating the next microinstruction to be
executed.
In summary, the microprogram sequencer is a crucial component of the control unit
in a computer system. It calculates the next microinstruction address to be executed
based on inputs received from various registers in the control unit. The
microprogram sequencer selects the next address based on the next address
calculation and sends control signals to other components of the control unit. The
microprogram sequencer plays a vital role in ensuring that the processor executes
the correct set of microinstructions in the right order.
16. Explain about design of microprogrammed control unit with a

diagram showing how decoding of microoperation fields is done.
A microprogrammed control unit is a type of control unit that uses microcode to
control the operations of a computer's processor. The microcode consists of a
sequence of microinstructions that specify the operations to be performed by the
processor. The microinstructions are stored in a control memory, and the
microprogrammed control unit fetches and executes them in the correct sequence.
The design of a microprogrammed control unit typically involves three major

components: the control memory, the microinstruction register, and the
microinstruction decoder. The control memory stores the microinstructions, the
microinstruction register holds the current microinstruction being executed, and the
microinstruction decoder decodes the microinstruction and generates the control
signals that control the operations of the processor.
Here is a diagram showing the design of a microprogrammed control unit, along

with the decoding of microoperation fields:
+-----------------+
| Control Memory |
| (Microcode ROM) |
+-----------------+
|
| Address Bus
|
v
+-----------------+
| Microinstruction|
| Register |
+-----------------+
|
| Control Signals
|
v
+----------------------------------------------------+
| Microinstruction Decoder and Control |
| Signal Generator (Decoding Microoperations) |
+----------------------------------------------------+
The microinstruction consists of several fields, including the microoperation fields

that specify the operations to be performed by the processor. The microinstruction
decoder decodes these fields and generates the control signals that control the
operations of the processor.
The decoding of microoperation fields is typically done using a combination of logic
gates and multiplexers. The microoperation fields are decoded one at a time, and the
resulting control signals are combined to generate the overall control signal for the
microinstruction. The microoperation decoder may also include additional logic to
handle conditional branching and other control flow operations.
Overall, the design of a microprogrammed control unit involves a careful balance

between the size and complexity of the microcode, the speed and efficiency of the
microinstruction decoder, and the flexibility and ease of use of the overall system. By
carefully designing and optimizing these components, a microprogrammed control
unit can provide a flexible and powerful way to control the operations of a
computer's processor.
UNIT 3
1. Describe the division algorithm for signed binary numbers represented in

sighed magnitude form.
In signed magnitude representation, the most significant bit represents the sign of
the number, with 0 indicating a positive number and 1 indicating a negative number.
To perform division in signed magnitude representation, we can use the following
algorithm:
1. Determine the sign of the quotient by XORing the signs of the dividend and
divisor. If they are the same, the quotient is positive, and if they are different,
the quotient is negative.
2. Convert both the dividend and divisor to their absolute values, ignoring their
signs.
3. Align the most significant bit of the divisor with the most significant bit of the
dividend.
4. Shift the divisor to the right until it is less than or equal to the dividend.
5. Subtract the shifted divisor from the dividend, and place a 1 in the
corresponding bit position of the quotient.
6. Repeat steps 4 and 5 until the entire dividend has been processed.
7. If the quotient is negative, take the two's complement of the resulting binary
number to get the correct negative value.
Here is an example of the division algorithm for signed binary numbers in signed
magnitude form:
Divide -1011 (-11) by 110 (6) in signed magnitude form.
1. Determine the sign of the quotient: the signs of the dividend and divisor are
different, so the quotient will be negative.
2. Convert the absolute values: 1011 (11) divided by 110 (6).
3. Align the most significant bit of the divisor (1) with the most significant bit of
the dividend (1).
-1011 -110
4. Shift the divisor to the right until it is less than or equal to the dividend:
-1011
 1100
5. Subtract the shifted divisor from the dividend, and place a 1 in the
corresponding bit position of the quotient:
-1011
 1100
1110 (quotient bit is 1)

6. Repeat steps 4 and 5 until the entire dividend has been processed:
-1011
 1100
1110 (1) 1010 (0) 110 (1) 100 (1)

11010 (-1)
7. If the quotient is negative, take the two's complement of the resulting binary
number to get the correct negative value:
-1011 / 110 = -11010 (in signed magnitude representation)
To get the correct negative value, we take the two's complement of 11010:
11010
 1
11011
Therefore, -1011 / 110 = -11/6 in signed magnitude representation.
2. Write short notes on Division Overflow.

Division overflow occurs when the result of a division operation is too large to be
represented by the number of bits allocated for the quotient. This can occur in both
integer and floating-point division.
In integer division, overflow occurs when the quotient is too large to fit into the
allocated number of bits. For example, if we divide the largest positive integer by 1,
the result will be larger than the maximum integer value and overflow will occur.
Similarly, if we divide the smallest negative integer by -1, the result will be larger than
the maximum integer value and overflow will occur.
In floating-point division, overflow can occur when the result is too large to be
represented by the range of the floating-point format. For example, if we divide a
very large number by a very small number, the result can be too large to be
represented accurately in a floating-point format, and overflow will occur.
Division overflow can be detected by checking the sign of the quotient and
comparing it to the signs of the dividend and divisor. If the signs are the same but
the quotient is negative, or if the signs are different but the quotient is positive,
overflow has occurred.
To prevent division overflow, we can increase the number of bits allocated for the
quotient or use a larger floating-point format with a wider range of representable
values. In some cases, we can also use scaling or normalization techniques to reduce
the range of the operands before performing the division operation.
3. Explain about Booth's multiplication algorithm.

Booth's multiplication algorithm is a multiplication algorithm for signed binary
numbers that is more efficient than the standard shift-and-add multiplication
algorithm. The algorithm was invented by Andrew Booth in 1951.
The basic idea of Booth's algorithm is to replace consecutive groups of 1s or 0s in

the multiplier with a single bit and a sign bit, depending on the value of the previous
bit. This reduces the number of additions and shifts required in the multiplication
process.
The steps involved in Booth's algorithm are as follows:
1. Initialize the product P to 0 and the multiplier Q to the multiplicand M.

2. Add a 0 bit to the right of Q to make it an even number of bits.
3. Repeat the following steps until the multiplier Q becomes 0:
a. If the last two bits of Q are 01, subtract M from P and shift Q right by 1 bit.
b. If the last two bits of Q are 10, add M to P and shift Q right by 1 bit.
c. Otherwise, shift Q right by 1 bit.
4. If the sign bit of P is 1, the result is negative. Otherwise, the result is positive.
Booth's algorithm is more efficient than the standard shift-and-add multiplication

algorithm because it reduces the number of additions required in the multiplication
process. The algorithm is particularly useful for multiplying large numbers with a lot
of leading zeros or ones.
4. Trace the addition algorithm for adding 2 floating point numbers.

The addition algorithm for adding two floating-point numbers involves several steps.
Here is a brief outline of the process:
1. Check the exponents of the two numbers and align the numbers so that they
have the same exponent. This is done by shifting the mantissa and adjusting
the exponent accordingly.
2. Add the mantissas of the two numbers. If the signs of the mantissas are
different, subtract the smaller mantissa from the larger mantissa.
3. Normalize the result by shifting the mantissa to the right until the most
significant bit is 1. Adjust the exponent accordingly.
4. Check for overflow or underflow. If the exponent is too large or too small to
be represented, an overflow or underflow has occurred, respectively.
5. Round the result if necessary. If the precision of the result is greater than the
precision of the operands, the result may need to be rounded to the nearest
representable value.
6. Pack the result into the floating-point format and return it.
Here is a detailed example of the addition algorithm for adding two floating-point
numbers:
Suppose we want to add the following two floating-point numbers:
Number 1: -0.101001 x 2^6 Number 2: 0.110101 x 2^4
1. Align the exponents by shifting the mantissa of number 2 two places to the
right:
Number 1: -0.101001 x 2^6 Number 2: 0.00110101 x 2^6
2. Add the mantissas:
-0.101001 + 0.00110101 = -0.099899
Since the signs of the mantissas are different, we take the absolute value of the
smaller mantissa and subtract it from the larger mantissa:
|-0.101001| = 0.101001 0.101001 - 0.00110101 = 0.099899
3. Normalize the result by shifting the mantissa one place to the right:
-0.099899 x 2^6 = -1.2740864 x 2^4
4. Check for overflow or underflow. In this case, the exponent is within the range
of representable values, so no overflow or underflow has occurred.
5. Round the result if necessary. Since the precision of the result is the same as
the precision of the operands, rounding is not necessary.
6. Pack the result into the floating-point format:
Sign bit: 1 (since the result is negative) Exponent: 100110 (corresponding to 4 in

decimal) Mantissa: 01001100100000000000000
The final result is:
-1.2740864 x 2^4
5. Explain the different parts of algorithm for adding/subtracting floating

point numbers.
The algorithm for adding/subtracting floating point numbers involves the following
steps:
1. Check the signs of the two numbers. If they have different signs, then perform
subtraction instead of addition.
2. Align the decimal points of the two numbers by shifting the mantissa of the
smaller number to the right or the left.
3. Add or subtract the mantissas, depending on the sign of the result.
4. Normalize the result by adjusting the exponent and mantissa to represent the
smallest possible number with the same value.
5. Check for overflow and underflow conditions. If the result is too large or too
small to be represented in the given number of bits, then report an overflow
or underflow error.
6. Round the result to the nearest representable value, if necessary.
7. Return the final result, which consists of the sign, exponent, and mantissa.
The above algorithm assumes that the two numbers being added or subtracted have
the same exponent. If the exponents are different, then the numbers must be first
scaled to the same exponent before performing the operation. This involves
adjusting the exponent and mantissa of one or both numbers so that they have the
same power of 2. This can be done by shifting the mantissa and adjusting the
exponent accordingly.
6. Explain the different parts of algorithm for multiplication of floating point

numbers.
The algorithm for multiplication of floating point numbers involves the following
steps:
1. Multiply the mantissas of the two numbers.

2. Add the exponents of the two numbers.
3. Normalize the result by adjusting the exponent and mantissa to represent the
smallest possible number with the same value.
or underflow error.
5. Round the result to the nearest representable value, if necessary.
6. Return the final result, which consists of the sign, exponent, and mantissa.
The above algorithm assumes that the two numbers being multiplied have
normalized mantissas. If one or both of the numbers have unnormalized mantissas,
then they must be first normalized before performing the multiplication. This
involves adjusting the mantissa and exponent of the number so that the mantissa
has a single nonzero digit to the left of the decimal point.
Another important consideration in floating point multiplication is the precision of

the result. If the mantissas of the two numbers have n bits each, then the product
may require up to 2n bits to represent the exact result. However, most floating point
formats only provide a fixed number of bits for the mantissa, which means that the
result must be rounded to fit into the available bits. This can introduce a loss of
precision in the result, which can accumulate over multiple operations and lead to
errors in the final result. To mitigate this issue, some floating point formats provide
extra bits for intermediate calculations, or support higher precision arithmetic
operations.
7. Describe the Addition/Subtraction algorithm for signed binary numbers

represented in signed magnitude form.
The algorithm for adding or subtracting signed binary numbers represented in
signed magnitude form involves the following steps:
1. Determine the signs of the two numbers being added or subtracted.

2. If the signs are different, then perform subtraction by taking the absolute
value of each number and subtracting the smaller absolute value from the
larger absolute value. The sign of the result is the same as the sign of the
number with the larger absolute value.
3. If the signs are the same, then perform addition by adding the two absolute
values. The sign of the result is the same as the sign of the numbers being
added.
or underflow error.
5. Return the final result, which consists of the sign and magnitude.
Note that when performing subtraction, the larger absolute value is always
subtracted from the smaller absolute value to ensure that the result is positive. Also,
when checking for overflow and underflow, it is important to consider the sign of the
result. For example, if adding two negative numbers produces a result that is too
negative to be represented, then this is an underflow condition and should be
reported as such.
In practice, the addition and subtraction of signed binary numbers can be performed
using the same circuitry, with the only difference being in the sign of the second
operand when performing subtraction.
8. Describe the Addition/Subtraction algorithm for signed binary numbers

represented in signed 2's complement form.
The algorithm for adding or subtracting signed binary numbers represented in 2's
complement form involves the following steps:
1. Align the two numbers by placing the least significant bit (LSB) of each
number in the same column.
2. Add the two LSBs and record the result as the LSB of the final sum. If a carry is
generated, carry it over to the next column.
3. Repeat step 2 for each subsequent column, adding the two bits in each
column and any carry generated from the previous column. Record the result
as the next bit in the final sum.
4. If performing subtraction, invert all bits of the second operand (i.e., the
subtrahend) and add 1 to obtain its 2's complement representation.
5. Check for overflow and underflow conditions. If the result has a carry out of
the most significant bit (MSB), then an overflow has occurred. If the result is
negative and has a 1 in the MSB, then an underflow has occurred.
6. If performing subtraction, discard the carry out of the MSB of the final sum
and adjust the sign of the result as necessary.
7. Return the final result, which consists of the sign and magnitude.
Note that the addition and subtraction of signed binary numbers represented in 2's
complement form can be performed using the same circuitry, with the only
difference being in the sign of the second operand and the handling of the carry out
of the MSB when performing subtraction.
Also, it is important to note that 2's complement representation allows for the use of
the same addition and subtraction algorithms regardless of the sign of the numbers
being operated on, as long as the operands are represented in 2's complement form.
9. Describe the circuit for computing 9's complement of a BCD digit.

The 9's complement of a BCD digit is simply the result of subtracting each digit from
9. For example, the 9's complement of 5 is 4, the 9's complement of 3 is 6, and so on.
To compute the 9's complement of a BCD digit using digital logic, we can use a
circuit that consists of a BCD subtractor and a fixed input of 9. The circuit diagram for
computing the 9's complement of a BCD digit is shown below:
+-------+
BCD | |9
Digit -| SUB |-
+-------+
9's Complement
The BCD digit to be complemented is input to the subtractor along with the fixed
value of 9. The subtractor circuit subtracts the BCD digit from 9, resulting in the 9's
complement of the input digit.
For example, if the BCD digit input is 5, the subtractor will subtract 5 from 9 to obtain
a result of 4, which is the 9's complement of 5.
Note that the circuit for computing the 9's complement of a BCD digit can also be
implemented using combinational logic, which is simpler than using a BCD
subtractor. The combinational circuit for computing the 9's complement of a BCD
digit is essentially a simple XOR gate for each BCD digit. The XOR gate takes the
input BCD digit and the fixed value of 9 and outputs the corresponding 9's
complement digit.
10. Describe the multiplication algorithm for BCD numbers.

The multiplication algorithm for BCD (Binary Coded Decimal) numbers is similar to
the long multiplication algorithm used for decimal numbers. The algorithm works by
multiplying each digit of one BCD number with each digit of the other BCD number,
starting from the rightmost digit and working towards the left. The partial products
are then added together to get the final result.
Here are the steps for the multiplication algorithm for BCD numbers:
1. Write the two BCD numbers to be multiplied one below the other, aligned on
the right. Let's call them A and B.
2. Starting from the rightmost digit of B, multiply it with each digit of A and write
the partial products below each digit of B, shifting each product one digit to
the left for each successive digit of B. For example, if the rightmost digit of B is
6 and the corresponding digit of A is 2, then the partial product is 12. Write 12
below the 6, shifted one digit to the left.
3. Repeat step 2 for each digit of B, adding the partial products together as you
go along.
4. The final result is the sum of the partial products obtained in step 3.
Here's an example to illustrate the multiplication algorithm for BCD numbers:
1 2 3 4 <-- A
x 5 6 <-- B
----------------
7 4 1 6 <-- partial product for 4 in B
6 1 7 0 <-- partial product for 3 in B
----------------
6 9 5 0 <-- final result
In this example, we're multiplying the BCD number 1234 with the BCD number 56.
Starting from the rightmost digit of 56, we multiply it with each digit of 1234 and
write the partial products below each digit of 56. Then we add the partial products
together to get the final result, which is 6950.
Note that the multiplication algorithm for BCD numbers can be implemented using
combinational logic, which is simpler than using a multiplier circuit. The
combinational circuit for multiplying two BCD digits is essentially a 4-bit by 4-bit
multiplier, with additional logic to handle the BCD encoding.
11. Describe the division algorithm for BCD numbers.

The division algorithm for BCD numbers is similar to the division algorithm for
decimal numbers. It involves the following steps:
Step 1: Set the quotient and remainder to zero.
Step 2: Take the first digit of the dividend and divide it by the divisor. If the divisor is
greater than the dividend, set the quotient digit to zero and move to the next digit of
the dividend.
Step 3: Multiply the divisor by the quotient digit and subtract it from the dividend.
Step 4: If the result of the subtraction is negative, add the divisor back to the
dividend and decrease the quotient digit by one.
Step 5: Move to the next digit of the dividend and repeat steps 2-4 until all digits of
the dividend have been processed.
Step 6: The final quotient and remainder are the result of the division.
The circuit for implementing this algorithm involves BCD arithmetic operations like
addition, subtraction, and multiplication. The circuit also includes BCD-to-binary and
binary-to-BCD conversion circuits to convert between BCD and binary
representations of the numbers.
12. Describe the multiplication algorithm for signed binary numbers

represented in signed
magnitude form.
The multiplication algorithm for signed binary numbers represented in signed
magnitude form involves the following steps:
Step 1: Convert the signed binary numbers into unsigned binary numbers by
ignoring the sign bit.
Step 2: Multiply the two unsigned binary numbers using the standard multiplication
algorithm.
Step 3: Determine the sign of the product by examining the sign bits of the
multiplicand and multiplier. If the signs are the same, the product is positive,
otherwise, it is negative.
Step 4: Convert the unsigned binary product back to signed binary format by
restoring the sign bit.
For example, consider the multiplication of -5 and +3 in signed magnitude form:
Step 1: Convert -5 and +3 to unsigned binary as follows: -5 = 1011 +3 = 0011
Step 2: Multiply 1011 and 0011 using the standard multiplication algorithm:
1011
x 0011
------
1011
0000
1011
+----
11101
Step 3: Determine the sign of the product by examining the signs of the operands:
The signs of -5 and +3 are different, so the product is negative.
Step 4: Convert the unsigned binary product back to signed binary format by
restoring the sign bit: 11101 = -3
Therefore, the product of -5 and +3 in signed magnitude form is -3.

13. Explain multiplication algorithm for signed binary numbers represented in
signed magnitude form.
The multiplication algorithm for signed binary numbers represented in signed
magnitude form is similar to the multiplication algorithm for unsigned binary
numbers. However, additional steps are required to handle the sign of the product.
The algorithm involves the following steps:
Step 1: Separate the sign bit and the magnitude of each operand.
Step 2: Multiply the magnitudes of the two operands using the standard
multiplication algorithm.
operands. If the signs are the same, the product is positive, otherwise, it is negative.
Step 4: Restore the sign of the product by attaching the sign bit.
For example, let's consider the multiplication of -3 and +4 in signed magnitude form:
Step 1: Separate the sign bit and the magnitude of each operand as follows:
-3 = 1 011
+4 = 0 100
Step 2: Multiply the magnitudes of the two operands using the standard
multiplication algorithm:
1011
x 0100
------
1011
0000
1011
+-----
110110
operands: The signs of -3 and +4 are different, so the product is negative.
Step 4: Restore the sign of the product by attaching the sign bit: 110110 = -6
Therefore, the product of -3 and +4 in signed magnitude form is -6.
14. Demonstrate the working of Booth's multiplication algorithm.

Booth's multiplication algorithm is a widely used algorithm for multiplying two
signed binary numbers represented in 2's complement form. It reduces the number
of partial products needed to be added together, which results in faster
multiplication. The steps involved in Booth's multiplication algorithm are as follows:
1. Represent the two numbers, multiplicand (M) and multiplier (Q), in signed
binary 2's complement form.
2. Extend the length of the multiplier to be one bit more than the original length
of the multiplicand, adding a 0 to the leftmost bit to keep the sign bit intact.
3. Initialize the product (P) to be zero.
4. For i from 0 to n-1, where n is the length of the original multiplicand: a. If the
last two bits of Q are "01", add M to P. b. If the last two bits of Q are "10",
subtract M from P. c. Shift Q right by 1 bit.
5. The result is the n-bit product P.
Let's demonstrate this algorithm with an example. Let's say we want to multiply -5
(1011 in 2's complement) and 6 (0110 in 2's complement).
1. M = 1011, Q = 0110
2. Extend Q to 6 bits by adding a 0 to the leftmost bit: 00110
3. P = 000000
4. We need to perform 4 iterations since n=4: a. Last two bits of Q are "10",
subtract M from P: P = 01011 b. Last two bits of Q are "11", do nothing: P =
01011 c. Last two bits of Q are "01", add M to P: P = 00001 d. Last two bits of
Q are "10", subtract M from P: P = 11010
5. The result is the 4-bit product P = 11010, which is -30 in decimal (11010 in 2's
complement).
Therefore, -5 x 6 = -30, which is the correct result.
15. Explain the different parts of algorithm for division of floating point
numbers.
The algorithm for division of floating point numbers involves several steps:
1. Determine the sign of the result by checking the signs of the dividend and
divisor. If they have the same sign, the result will be positive; if they have
opposite signs, the result will be negative.
2. Normalize the divisor by shifting it left until its most significant bit is a 1. Keep
track of the number of shifts.
3. Normalize the dividend by shifting it left the same number of times as the
divisor. Keep track of the number of shifts.
4. Set the quotient to zero and the remainder to the dividend.
5. For each bit position in the quotient, starting from the leftmost position:
a. Shift the remainder left one bit and set the least significant bit to the next
bit of the dividend.
b. If the remainder is greater than or equal to the divisor, subtract the divisor
from the remainder and set the current bit of the quotient to 1. Otherwise, set
the current bit of the quotient to 0.
6. If the dividend was originally negative, negate the quotient.
7. If the divisor was originally negative, negate the quotient and the remainder.
8. Denormalize the quotient and remainder by shifting them right the same
number of times as the original normalization.
9. Round the quotient to the desired number of decimal places.
Overall, the algorithm involves normalizing both the divisor and dividend, performing
the division itself bit by bit, and then denormalizing the result.
16. Describe the Addition/Subtraction algorithm for BCD numbers.

The addition and subtraction of Binary Coded Decimal (BCD) numbers involve the
same basic algorithm as that of normal binary numbers. The only difference is that
BCD numbers use four bits to represent each decimal digit, which is a more compact
representation. The addition and subtraction algorithm for BCD numbers is described
below:
Addition algorithm for BCD numbers:
1. Add the two BCD digits, and if the sum is less than or equal to 9, the result is
correct.
2. If the sum is greater than 9, add 6 to the sum.
3. If there is a carry from the lower digit, add 1 to the sum of the next two digits.
4. Repeat the above steps until all digits have been added.
Subtraction algorithm for BCD numbers:
1. Subtract the second BCD digit from the first BCD digit, and if the result is
positive or zero, the result is correct.
2. If the result is negative, add 10 to the result and subtract 1 from the higher-
order digit.
3. Repeat the above steps until all digits have been subtracted.
For example, let us consider the addition of two BCD numbers 23 and 35:
2 3 BCD representation of 23
 3 5 BCD representation of 35
Here, we first add the two lower-order digits 3 and 5, which gives 8. Since the sum is
less than or equal to 9, we write down 8. Next, we add the two higher-order digits 2
and 3, which gives 5. However, there is a carry from the lower-order digit, so we add
1 to the sum of the next two digits (which is 5), giving 6. Finally, we get the result 58
by combining the two digits.
Similarly, let us consider the subtraction of two BCD numbers 35 and 23:
 2 3 BCD representation of 23
Here, we first subtract the lower-order digit 3 from the higher-order digit 5, which
gives 2. Since the result is positive, we write down 2. Next, we subtract the lower-
order digit 3 from the lower-order digit 5, which gives 2. Since the result is also
positive, we write down 2. Finally, we get the result 12 by combining the two digits.

If (Binary - Number1 & Binary - Number2) (Binary - Number1 Binary - Number1 )

Uploaded by

Copyright:

Available Formats

If (Binary - Number1 & Binary - Number2) (Binary - Number1 Binary - Number1 )

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

If (Binary - Number1 & Binary - Number2) (Binary - Number1 Binary - Number1 )

Uploaded by

Copyright:

Available Formats

1.

Logical operators are commonly used in programming to implement various

(i) Selective-complement: This application involves inverting or complementing

if (binary_number1 & binary_number2) {

if (binary_number1 & binary_number2) {

Logical Left Shift:

Circular Right Shift:

Arithmetic Left Shift:

In computer architecture, buses are communication channels used to transfer data

Micro-operations refer to basic operations that are performed on data stored in

There are three different notations used in RTL:

Example: Let's consider an example of a micro-operation using RTL. Suppose we

Using assembly language notation, this micro-operation can be written as:

In RTN notation, the same micro-operation can be represented graphically as:

6.Explain the design of an arithmetic unit of a computer supporting add, sub,

Addition and Subtraction: The addition and subtraction operations can be

Increment and Decrement: The increment and decrement operations can be

7. With suitable examples, explain how logical operators can be

(i) Selective-Set: The selective-set operation sets (changes to 1) a specific bit in a

(ii) Selective-Clear: The selective-clear operation clears (changes to 0) a specific bit in

(i) Selective-Clear: The selective-clear operation clears (changes to 0) a specific bit in

10.Explain about stored-program architecture with the help of a block diagram.

The stored-program architecture is implemented using a block diagram that consists

A digital computer is an electronic device that is capable of processing digital data

1. Operating System: An operating system (OS) is a software program that

1. Supercomputers: Supercomputers are the most powerful and expensive

14.Explain Von-Neumann (Stored-program) architecture with the help of a block

Von-Neumann architecture, also known as the stored-program architecture, is a

The block diagram of Von-Neumann architecture consists of the following

The Von-Neumann architecture operates using a stored-program concept, where

The block diagram of Von-Neumann architecture is shown below:

Overall, Von-Neumann architecture is a widely used computer architecture that provides a

1. Logical Left Shift

3.Explain about the memory reference instructions with the help of

Overall, memory reference instructions are an essential part of computer architecture,

4.Explain about the register reference instructions with the help

Overall, register reference instructions are an essential part of computer architecture,

5. Explain in detail a simple I/0 configuration and computer

6. Describe in brief with a flow chart the interrupt cycle of a computer.

Here is a flow chart illustrating the interrupt cycle:

7. Show how the operation X= (A*B}+(C*D) can be implemented using

mul ; Multiply the top two values in the stack (B*A)

mul B ; Multiply the accumulator register by B (A*B)

8. Describe in brief about register stack and memory stack in a stack

In summary, a stack-organized computer architecture can use either a register stack

1. Copy the contents of operand X to the program counter (PC).

1. Decrement the stack pointer (SP) by 1.

11. Write short notes on RISC characteristics.

1. Simple instructions: RISC processors have a smaller set of simple instructions

12. Write short notes on CISC characteristics.

In summary, CISC architecture emphasizes complex and powerful instructions that

13. Distinguish between hardwired control unit and micro-programmed

1. Implementation: A hardwired control unit is implemented using combinational

In summary, a hardwired control unit is implemented using combinational logic

14. Explain the concept of address sequencing in a micro-programmed

1. Sequential Addressing: In this method, the next microcode address is simply

In summary, address sequencing is the process of determining the next microcode

15. Explain about the microprogram sequencer for a control memory

Here is a brief explanation of the microprogram sequencer with a neat sketch:

7. Show how the operation X= (AB}+(CD) can be implemented using