Computer Architecture

2nd Year- IIIrd semester

Unit-1
Part 1:- Register Transfer & Micro-operations
Register Transfer Language
The symbolic notation used to describe the micro-operation transfers
amongst registers is called Register transfer language.
The term register transfer means the availability of hardware logic
circuits that can perform a stated micro-operation and transfer the result
of the operation to the same or another register.
The word language is borrowed from programmers who apply this term
to programming languages. This programming language is a procedure
for writing symbols to specify a given computational process.
Following are some commonly used registers:

1. Accumulator: This is the most common register, used to store data

taken out from the memory.
2. General Purpose Registers: This is used to store data intermediate
results during program execution. It can be accessed via assembly
programming.
3. Special Purpose Registers: Users do not access these registers.
These registers are for Computer system,
o MAR: Memory Address Register are those registers that holds the
address for memory unit.
Size= 12 bits
o MBR: Memory Buffer Register stores instruction and data received from
the memory and sent from the memory.
o PC: Program Counter points to the next instruction to be executed.
Size=12 bits.
o IR: Instruction Register holds the instruction to be executed. Holds
instruction code.
Size=16 bits.
 Register Transfer
Information transferred from one register to another is designated in
symbolic form by means of replacement operator.
R2 ← R1
It denotes the transfer of the data from register R1 into R2.
Normally we want the transfer to occur only in predetermined control
condition. This can be shown by following if-then statement: if (P=1)
then (R2 ← R1)

Bus and Memory Transfers

A digital system composed of many registers, and paths must be
provided to transfer information from one register to another. The
number of wires connecting all of the registers will be excessive if
separate lines are used between each register and all other registers in
the system.

A bus structure, on the other hand, is more efficient for transferring

information between registers in a multi-register configuration system.
A bus consists of a set of common lines, one for each bit of register,
through which binary information is transferred one at a time. Control
signals determine which register is selected by the bus during a
particular register transfer.

The following block diagram shows a Bus system for four registers. It is
constructed with the help of four 4 * 1 Multiplexers each having four data
inputs (0 through 3) and two selection inputs (S1 and S2).

We have used labels to make it more convenient for you to understand

the input-output configuration of a Bus system for four registers. For
instance, output 1 of register A is connected to input 0 of MUX1.

The two selection lines S1 and S2 are connected to the selection inputs
of all four multiplexers. The selection lines choose the four bits of one
register and transfer them into the four-line common bus.
The two selection lines S1 and S2 are connected to the selection inputs
of all four multiplexers. The selection lines choose the four bits of one
register and transfer them into the four-line common bus.

When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data
inputs of all four multiplexers are selected and applied to the outputs that
forms the bus. This, in turn, causes the bus lines to receive the content
of register A since the outputs of this register are connected to the 0
data inputs of the multiplexers.

Similarly, when S1S0 = 01, register B is selected, and the bus lines will
receive the content provided by register B.
The following function table shows the register that is selected by the
bus for each of the four possible binary values of the Selection lines.
 Arithmetic Micro-Operations
Some of the basic micro-operations are addition, subtraction, increment
and decrement.
1.Add Micro-Operation
It is defined by the following statement:
R3 → R1 + R2
The above statement instructs the data or contents of register R1 to be
added to data or content of register R2 and the sum should be
transferred to register R3.
2.Subtract Micro-Operation
Let us again take an example:
R3 → R1 + R2' + 1
In subtract micro-operation, instead of using minus operator we take 1's
compliment and add 1 to the register which gets subtracted, i.e R1 -
R2 is equivalent to R3 → R1 + R2' + 1
3.Increment/Decrement Micro-Operation
Increment and decrement micro-operations are generally performed by
adding and subtracting 1 to and from the register respectively
R1 → R1 + 1
R1 → R1 – 1
Symbolic Designation Description
R3 ← R1 + R2 Contents of R1+R2 transferred to R3.
R3 ← R1 - R2 Contents of R1-R2 transferred to R3.
R2 ← (R2)' Compliment the contents of R2.
R2 ← (R2)' + 1 2's compliment the contents of R2.
R3 ← R1 + (R2)' + 1 R1 + the 2's compliment of R2 (subtraction).
R1 ← R1 + 1 Increment the contents of R1 by 1.
 R1 ← R1 - 1 Decrement the contents of R1 by 1.

Logic Micro-Operations
These are binary micro-operations performed on the bits stored in the
registers. These operations consider each bit separately and treat them
as binary variables.
Let us consider the X-OR micro-operation with the contents of two
registers R1 and R2.
P: R1 ← R1 X-OR R2
In the above statement we have also included a Control Function.
Assume that each register has 3 bits. Let the content of R1 be 010 and
R2 be 100. The X-OR micro-operation will be:

Shift Micro-Operations
These are used for serial transfer of data. That means we can shift the
contents of the register to the left or right. In the shift left operation the
serial input transfers a bit to the right most position and in shift
right operation the serial input transfers a bit to the left most position.
There are three types of shifts as follows:
a) Logical Shift
It transfers 0 through the serial input. The symbol "shl" is used for
logical shift left and "shr" is used for logical shift right.
R1 ← she R1
R1 ← she R1
The register symbol must be same on both sides of arrows.
b) Circular Shift
This circulates or rotates the bits of register around the two ends without
any loss of data or contents. In this, the serial output of the shift register
is connected to its serial input. "cil" and "cir" is used for circular shift
left and right respectively.
c) Arithmetic Shift
This shifts a signed binary number to left or right. An arithmetic shift
left multiplies a signed binary number by 2 and shift left divides the
number by 2. Arithmetic shift micro-operation leaves the sign bit
unchanged because the signed number remains same when it is
multiplied or divided by 2.

Arithmetic Logical Unit

Instead of having individual registers performing the micro-operations,
computer system provides a number of registers connected to a
common unit called as Arithmetic Logical Unit (ALU). ALU is the main
and one of the most important unit inisde CPU of computer. All the
logical and mathematical operations of computer are performed here.
The contents of specific register is placed in the in the input of ALU. ALU
performs the given operation and then transfer it to the destination
register.

Part 2:- Basic Computer Organization And Design

Instruction Codes
While a Program, as we all know, is, A set of instructions that specify
the operations, operands, and the sequence by which processing has to
occur. An instruction code is a group of bits that tells the computer to
perform a specific operation part.
Instruction Code: Operation Code
The operation code of an instruction is a group of bits that define
operations such as add, subtract, multiply, shift and compliment. The
number of bits required for the operation code depends upon the total
number of operations available on the computer. The operation code
must consist of at least n bits for a given 2^n operations. The operation
part of an instruction code specifies the operation to be performed.

Instruction Code: Register Part

The operation must be performed on the data stored in registers. An
instruction code therefore specifies not only operations to be performed
but also the registers where the operands(data) will be found as well as
the registers where the result has to be stored.

Stored Program Organisation

The simplest way to organize a computer is to have Processor
Register and instruction code with two parts. The first part specifies the
operation to be performed and second specifies an address. The
memory address tells where the operand in memory will be found.
Instructions are stored in one section of memory and data in another.

Computers with a single processor register is known as Accumulator

(AC). The operation is performed with the memory operand and the
content of AC.
 Computer Instructions
The basic computer has three instruction code formats. The Operation
code (opcode) part of the instruction contains 3 bits and remaining 13
bits depends upon the operation code encountered. An instruction
comprises of groups called fields. These fields include:
o The Operation code (Opcode) field which specifies the operation to
be performed.
o The Address field which contains the location of the operand, i.e.,
register or memory location.
o The Mode field which specifies how the operand will be located.

There are three types of formats:

1. Memory Reference Instruction
It uses 12 bits to specify the address and 1 bit to specify the addressing
mode (I). I is equal to 0 for direct address and 1 for indirect address.

2. Register Reference Instruction

These instructions are recognized by the opcode 111 with a 0 in the left
most bit of instruction. The other 12 bits specify the operation to be
executed.

3. Input-Output Instruction
These instructions are recognized by the operation code 111 with a 1 in
the left most bit of instruction. The remaining 12 bits are used to specify
the input-output operation.
 Format of Instruction
The format of an instruction is depicted in a rectangular box symbolizing
the bits of an instruction. Basic fields of an instruction format are given
below:

1. An operation code field that specifies the operation to be

performed.
2. An address field that designates the memory address or register.
3. A mode field that specifies the way the operand of effective
address is determined.

Computers may have instructions of different lengths containing varying

number of addresses. The number of address field in the instruction
format depends upon the internal organization of its registers.

Instruction Cycle
An instruction cycle, also known as fetch-decode-execute cycle is the
basic operational process of a computer. This process is repeated
continuously by CPU from boot up to shut down of computer.
Following are the steps that occur during an instruction cycle:

1. Fetch the Instruction

The instruction is fetched from memory address that is stored in
PC(Program Counter) and stored in the instruction register IR. At the
end of the fetch operation, PC is incremented by 1 and it then points to
the next instruction to be executed.

2. Decode the Instruction

The instruction in the IR is executed by the decoder.
3. Read the Effective Address
If the instruction has an indirect address, the effective address is read
from the memory. Otherwise operands are directly read in case of
immediate operand instruction.

4. Execute the Instruction

The Control Unit passes the information in the form of control signals to
the functional unit of CPU. The result generated is stored in main
memory or sent to an output device.
The cycle is then repeated by fetching the next instruction. Thus in this
way the instruction cycle is repeated continuously.
 Design of Accumulator Logic
The adder and logic circuit has three sets of inputs. One set of 16 inputs
comes from the outputs of AC. Another set of 16 inputs comes from the
data register DR. A third set of eight inputs comes from the input register
INPR. The output of the adder and logic circuit provide the data inputs
for the register. In addition, it is necessary to include logic gates for
controlling the LD, INR and CLR in the register and for controlling the
operation of the adder and logic circuit.

In order to design the logic associated with AC, it is necessary to go over

the register transfer statements.
From the list we can drive the control logic gates and the adder and logic
circuit.
 UNIT- 2
Part-1 Central Processing Unit
General Register Organization
Generally CPU has seven general registers. Register organization
show how registers are selected and how data flow between register
and ALU. A decoder is used to select a particular register.The output of
each register is connected to two multiplexers to form the two buses A
and B. The selection lines in each multiplexer select the input data for
the particular bus.
The A and B buses form the two inputs of an ALU.The operation select
lines decide the micro operation to be performed by ALU. The result of
the micro operation is available at the output bus. The output bus
connected to the inputs of all registers, thus by selecting a destination
register it is possible to store the result in it.
A bus organization for seven CPU register
EXAMPLE:
• To perform the operation R3 = R1+R2 We have to provide
following binary selection variable to the select inputs.

1. SEL A : 001 -To place the contents of R1 into bus A.

2. SEL B : 010 - to place the contents of R2 into bus B
3. SEL OPR : 10010 – to perform the arithmetic addition A+B
4. SEL REG or SEL D : 011 – to place the result available on output
bus in R3.

Register and multiplexer input selection code

SELD or
Binary code SELA SELB SELREG

000 Input Input ---

001 R1 R1 R1

010 R2 R2 R2

011 R3 R3 R3

100 R4 R4 R4

101 R5 R5 R5

110 R6 R6 R6

111 R7 R7 R7
Operation with symbol:

Operation
selection code Operation symbol

0000 Transfer A TSFA

0001 Increment A INC A

0010 A+B ADD

0011 A-B SUB

0100 Decrement A DEC

0101 A AND B AND

0110 A OR B OR

0111 A XOR B XOR

1000 Complement A COMA

1001 Shift right A SHR

1010 Shift left A SHL

Stack Organization
Instruction Formats
 Difference between RISC and CISC

Part 2:- Pipeline and Vector Processing

Pipelining is the process of accumulating instruction from the processor
through a pipeline. It allows storing and executing instructions in an
orderly process. It is also known as pipeline processing.
Pipelining is a technique where multiple instructions are overlapped
during execution. Pipeline is divided into stages and these stages are
connected with one another to form a pipe like structure. Instructions
enter from one end and exit from another end.
Pipelining increases the overall instruction throughput.
In pipeline system, each segment consists of an input register followed
by a combinational circuit. The register is used to hold data and
combinational circuit performs operations on it. The output of
combinational circuit is applied to the input register of the next segment.
Pipeline system is like the modern day assembly line setup in factories.
For example in a car manufacturing industry, huge assembly lines are
setup and at each point, there are robotic arms to perform a certain task,
and then the car moves on ahead to the next arm.

Types of Pipeline
It is divided into 2 categories:

1. Arithmetic Pipeline
2. Instruction Pipeline

Arithmetic Pipeline
Arithmetic pipelines are usually found in most of the computers. They
are used for floating point operations, multiplication of fixed point
numbers etc. For example: The input to the Floating Point Adder pipeline
is:
X = A*2^a
Y = B*2^b
Here A and B are mantissas (significant digit of floating point numbers),
while a and b are exponents.
The floating point addition and subtraction is done in 4 parts:

1. Compare the exponents.

 2. Align the mantissas.
3. Add or subtract mantissas
4. Produce the result.

Registers are used for storing the intermediate results between the
above operations.

Instruction Pipeline
In this a stream of instructions can be executed by
overlapping fetch, decode and execute phases of an instruction cycle.
This type of technique is used to increase the throughput of the
computer system.
An instruction pipeline reads instruction from the memory while previous
instructions are being executed in other segments of the pipeline. Thus
we can execute multiple instructions simultaneously. The pipeline will be
more efficient if the instruction cycle is divided into segments of equal
duration.