Digital System Design

1
QUANTUM SERIES
For
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Digital System Design

By
Ankit Tyagi
TM
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Digital System Design (EC : Sem-3)

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CONTENTS
KEC 302 : Digital System Design
UNIT-1 : LOGIC SIMPLIFICATION & COMBINATIONAL LOGIC DESIGN

(1–1 B to 1–32 B)
Binary codes, code conversion, review of Boolean algebra and
Demorgans theorem, SOP & POS forms, Canonical forms,
Karnaugh maps up to 6 variables, tabulation method.
UNIT-2 : MSI DEVICES (2–1 B to 2–31 B)

MSI devices like comparators, multiplexers, encoder, decoder, driver
& multiplexed display, half and full adders, subtractors, serial and
parallel adders, BCD adder, barrel shifter and ALU.
UNIT-3 : SEQUENTIAL LOGIC DESIGN (3–1 B to 3–40 B)

Sequential logic design: Building blocks like S-R, JK and Master-
Slave JK FF, edge triggered FF, state diagram, state reduction,
design of sequential circuits, ripple and synchronous counters,
shift registers, finite state machines, design of synchronous FSM,
algorithmic state machines charts. Designing synchronous circuits
like pulse train generator, pseudo random binary sequence generator,
clock generation.
UNIT-4 : LOGIC FAMILIES & MEMORIES (4–1 B to 4–32 B)

TTL NAND gate, specifications, noise margin, propagation delay,
fan-in, fan-out, tristate TTL, ECL, CMOS families and their
interfacing, memory elements, concept of programmable logic
devices like FPGA, logic implementation using programmable
devices.
UNIT-5 : D/A AND A/D CONVERTER (5–1 B to 5–21 B)

Digital-to-Analog converters (DAC): Weighted resistor, R-2R ladder,
resistor string etc. analog-to-digital converters (ADC): single slope,
dual slope, successive approximation, flash etc. Switched capacitor
circuits: Basic concept, practical configurations, application in
amplifier, integrator, ADC etc.
SHORT QUESTIONS (SQ–1 B to SQ–17 B)
SOLVED PAPERS (2014-15 TO 2019-20) (SP–1 B to SP–44 B)

Digital System Design 1–1 B (EC-Sem-3)
1 Logic Simplification
and Combinational
Logic Design
CONTENTS
Part-1 : Binary Codes ................................................ 1–2B to 1–3B
Part-2 : Code Conversion ....................................... 1–3B to 1–12B
Part-3 : Review of Boolean Algebra and ........... 1–12B to 1–15B

Demorgan’s Theorem : SOP and
POS Forms, Canonical Forms
Part-4 : Karnaugh Maps Upto 6 ......................... 1–15B to 1–22B

Variables
Part-5 : Tabulation (Quine-McCluskey) ........... 1–22B to 1–31B

Method
1–2 B (EC-Sem-3) Logic Simplification & Combinational Logic Design
PART-1
Binary Code.
Questions-Answers
Long Answer Type and Medium Answer Type Questions
Que 1.1. Describe the binary codes. Show the classification of

binary codes in tabular format.
Answer
1. Code is the representation of group of symbols, words, or letters. As the
digital data is used as group of binary numbers, so, we call it as the
binary codes.
2. These binary codes are used for the designing and analysis of digital
circuit, computer applications, in digital communication. The codes are
classified into certain following categories :
i. Weighted codes
ii. Non-weighted codes
iii. Reflective codes
iv. Sequential codes
v. Alphanumeric codes
vi. Error detecting and correcting codes.
3. Since, all these codes use only 0 and 1, so it is easier to implement. The
binary codes can also be used for representing the numbers as well as
the alphanumeric letters.
4. The classification of codes can be composed in tabular form which is as
follows :
Codes
Weighted Reflective Alphanumeric

codes codes codes
• 2421 • ASCII Error detecting
Non-weighted • EBCDIC & correcting codes
Binary BCD • Excess-3
codes • Hamming
• 8421 • Excess-3 Sequential codes
• 8421 • Parity
• 2421 • Gray
• Excess-3
Fig. 1.1.1.
5. Weighted binary codes are those which obey the positional weight for
the number to represent.
6. In non-weighted codes, the positional weights are not assigned.
7. In reflective code, the reflectivity is desirable. For example, in 9’s
complement subtraction, i.e., code for 9 is the complement for 0, code for
8 is complement of 1, 7 for 2, 6 for 3 and 5 for 4.
8. In sequential code, each succeeding code is one binary number greater
than the preceding code.
9. The alphanumeric codes are designed to represent numbers as well as
characters.
10. The error detecting and correcting codes are used to detect and correct
the error like 0 may change to 1 or vice-versa by using some special
codes which possess the capacity to detect and correct the error.
Que 1.2. Represent the decimal number 6 in (i) excess-3 code, (ii)
BCD code, (iii) Gray code, (iv) 8421 code and (v) 2421 codes.
Answer
i. Excess-3 code :
6 (in BCD) = 0110
+3 = 0011
9 = 1001
ii. BCD code : (6)10 = 0110 (in BCD)
iii. Gray code : (6)2 = 0110
  
0 1 1 0
   
0 1 0 1
Gray code = 0101
iv. 8421 code : (6)2 = 0110
(6)8,4, – 2, – 1 = 1010
v. 2421 code :
(6)2,4,2,1 = 1100
PART-2
Code Conversion.
Questions-Answers

Que 1.3. Design Binary to BCD code converter.
Answer
Truth table :
Binary code BCD code

D C B A B4 B3 B2 B1 B0
0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 1
0 0 1 0 0 0 0 1 0
0 0 1 1 0 0 0 1 1
0 1 0 0 0 0 1 0 0
0 1 0 1 0 0 1 0 1
0 1 1 0 0 0 1 1 0
0 1 1 1 0 0 1 1 1
1 0 0 0 0 1 0 0 0
1 0 0 1 0 1 0 0 1
1 0 1 0 1 0 0 0 0
1 0 1 1 1 0 0 0 1
1 1 0 0 1 0 0 1 0
1 1 0 1 1 0 0 1 1
1 1 1 0 1 0 1 0 0
1 1 1 1 1 0 1 0 1
K-map simplification :
Expression for B 0 Expression for B 1

BA 00 01 11 10 BA 00
DC 01 11 10
0 1 3 2 DC
00 0 1 3 2
1 1 00
1 1
4 5 7 6 4 5 7 6
01 1 1 01 1 1
11 12 13 15 14
11
12 13 15 14
1 1
1 1
8 9 11 10 8 9 11 10
10 1 1 10
B0 = A
B1 = DCB + DB

BA 00 01 11 10 BA 00 01 11 10
DC DC
0 1 3 2 0 1 3 2
00 00
4 5 7 6 4 5 7 6
01 01
1 1 1 1
12 13 15 14 12 13 15 14
11 11
1 1
8 9 11 10 8 9 11 10
10 10
1 1
B2 = DC + CB B3 = DCB
Expression for B 4
BA 00 01 11 10
DC
0 1 3 2
00
4 5 7 6
01
12 13 15 14
11
1 1 1 1
8 9 11 10
10
1 1
B4 = DC + DB
Logic diagram :
Binary code
D C B A
BCD code
B0 LSD
B1
B2
B3
B4 MSD
Fig. 1.3.1. Logic circuit for binary to BCD converter.

Que 1.4. Design a combinational circuit that converts a BCD
code to excess-3 code. AKTU 2016-17, Marks 15
Answer
Truth table :
Input BCD Output excess-3 code
A B C D w x y z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1. The maps in Fig. 1.4.1, are plotted to obtain simplified boolean functions
for the outputs.
2. A two-level logic diagram of each output may be obtained directly from
the boolean expressions derived from the maps.
For z For y
CD CD
AB 00 01 11 10 AB 00 01 11 10
00 1 0 1 3
1 2
00 1 0 1
1 3 2
01 1 4 5 7 1 6 01 1 4 5
1 7 6
11 × 12 × 13 × 15 × 14 11 × 12
×
13
×
15
×
14
10 1 8 9 × 11 × 10 10 1 × ×
8 9 11 10
z=D y = CD + CD
For x For w
CD CD
00 01 11 10 00 01 11 10
AB AB
00 1 1 1 00
0 1 3 2 0 1 3 2
01 1 4 5 7 6 01 4 1 5 1 7 16
11 × × × × 11 × × × ×
12 13 15 14 12 13 15 14
1 19 × ×
10 8 19 × 11 × 10 10 8 11 10
x = BC + BD + BCD w = A + BC + BD
Fig. 1.4.1. Maps for BCD to excess-3 code converter.
3. The expressions derived from the maps are :

z= D
y = CD + CD = CD + (C  D)
x = BC  BD  BCD = B(C  D)  BCD
= B (C + D) + B (C  D)
w = A + BC + BD = A +B(C + D)
4. The logic diagram that implements these expressions is shown in
Fig. 1.4.2.
D
z
D CD
y
C
C+D
(C + D)
B
x
A w
Fig. 1.4.2.
Que 1.5. Design excess-3 code to BCD code converter.
Answer
Truth table :
Excess-3 code BCD code
E3 E2 E1 E0 B3 B2 B1 B0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1
The unused Excess-3 codes are 0000, 0001, 0010, 1101, 1110 and 1111.
So place X (Don’t Care condition) for the corresponding codes.
Expression for B0 Expression for B1
E1E0 E1E0
00 01 11 10 00 01 11 10
E3E2 E3E2
0 1 3 2 0 1 3 2
00 × × × 00
× × ×
4 5 7 6 4 5 7 6
01 1 1 01 1 1
12 13 15 14 12 13 15 14
11 1 × × × 11
× × ×
8 9 11 10 8 9 11 10
10 1 1 10 1 1
B0 = E0 B1 = E1 E0 + E1 E0 = E1  E0
E1E0 E1E0
00 01 11 10 00 01 11 10
E3E2 E3E2
0 1 3 2 0 1 3 2
00 × × × 00
× × ×
4 5 7 6 4 5 7 6
01 01
1
12 13 15 14 12 13 15 14
11 11
× × × 1 × × ×
8 9 11 10 8 9 11 10
10 10
1 1 1 1
B2 = E2 E1 + E2 E1 E0 + E3 E1 E 0 B3 = E3 E2 + E3 E1 E0
Logic diagram :
E3 E2 E1 E0
B0
B1
B2
B3
Fig. 1.5.1.
Que 1.6. Design Binary code to Gray code converter.
AKTU 2018-19, Marks 07
Answer
Truth table :
Binary code Gray code

D C B A G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
Expression for G 0 Expression for G 1

BA BA
00 01 11 10 00 01 11 10
DC DC
0 1 3 2 0 1 3 2
00 1 1 00 1 1
4 5 7 6 4 5 7 6
01 1 1 01
1 1
12 13 15 14 12 13 15 14
11 1 1 11
1 1
8 9 11 10 8 9 11 10
10 1 1
10
1 1
G0 = BA + BA = B  A G1 = CB + CB = C  B

BA BA
00 01 11 10 00 01 11 10
DC DC
0 1 3 2 0 1 3 2
00 00
4 5 7 6 4 5 7 6
01 01
1 1 1 1
11 12 13 15 14 11 12 13 15 14
1 1 1 1
8 9 11 10 8 9 11 10
10 10
1 1 1 1 1 1 1 1
G2 = DC + DC = C  D G3 = D
We get the simplified boolean expression for the code converter of Binary
to Gray code.
G0 = BA  BA  B  A
G1 = CB  CB  C  B
G2 = DC  DC  C  D
G3 = D
Logic diagram :
D C B A  Binary code
G3 G2 G1 G0  Gray code
Fig. 1.6.1.
Que 1.7. Design a combinational circuit that converts a 3-bit

Gray code to a 3-bit binary number. Implement the circuit with
i. Exclusive-OR gate
ii. NAND gate only.
Answer
Gray code to binary code converter :
Gray code Binary code
G2 G1 G0 C B A
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 1
1 0 1 1 1 0
1 1 0 1 0 0
1 1 1 1 0 1
G1G0 For A G1G0 For B
G2 G2
00 01 11 10 00 01 11 10
0 1 1 0 1 1
0 1 3 2 0 1 3 2
1 1 1 1 1 1
4 5 7 6 4 5 7 6
A = G 2 G 1 G 0 + G 2 G 1 G 0 + G 2 G 1 G 0 + G2G 1G 0 B = G 2G 1 + G 2G 1
A = G2  G1  G0 B = G2  G1
For C
G1G0
G2 00 01 11 10
0
0 1 2 3
1 1 1 1 1
4 5 7 6
C = G2
Logic diagram :
i. Using XOR gates :
G0 G2 G1 G0 = A
G1
G2
G2 G1 = B
C = G2
Fig. 1.7.1.
ii. Using NAND gates :

G2
G 2G 1G 0
G1
G0
G2 G 2G 1G 0
(G2G1G 0) (G2G 1G0) (G2G1G0) (G2G 1G0)
G1
G0 A = G 2G 1G 0 + G 2G 1G 0 + G 2G 1G 0 + G 2G 1G 0
G2 G 2G 1G 0
G1
G0
G2 G 2G 1G 0
G1
G0
G 2G 1
(G2G1) . (G2G 1) = G 2G1+G2G1 = B
G2 G 2G 1
G1
C = G2
Fig. 1.7.2.
PART-3
Review of Boolean Algebra and Demorgan’s Theorem : SOP and
POS Forms, Canonical Forms.
Questions-Answers
Que 1.8. State De Morgan’s theorem.
Answer
First De Morgan theorem : It states, complement of two or more
variables and then AND operation on these is equivalent to NOR
operation on these variables. (NOR means complement of two or more
variables OR).
A1  A2 = A1 . A2
Second De Morgan theorem : It states that complement of two or
more variables and then OR operation on these is equivalent to a NAND
operation on these variables (NAND means complement of two or more
variables AND).
A1 A2 A3 = A1  A2  A3 ....
Que 1.9. Simplify the following expression as much as possible :

F(w, x, y, z) = y z  wxz  wxyz  wyz
and implement your result using universal gates only.
Answer
F(w, x, y, z) = y z  wx z  w xyz  wyz
= y z  wyz  wx z  wxyz
= z ( y  wy)  wz (x  xy)
= z ( y  w)  wz ( x  y) [ A  AB  A  B]
= y z  wz  wx z  wy z
= y z  wyz  wz  wx z
= z ( y  wy)  z (w  wx)
= z ( y  w)  z (w  x )
= z ( y  w  w  x)
= z ( y  1  x) [  1 + A = 1]
= z ( y  1) [  1 + A = 1]
= z
z z z z
Using NAND gate Using NOR gate
(a) Fig. 1.9.1. (b )
Que 1.10. Simplify the following boolean equation :
Y(A, B, C, D) = ABCD + ABCD
Answer
Given, Y(A, B, C, D) = A B C D + ABCD = ABD (C  C )
since, C+ C =1
 Y(A, B, C, D) = ABD
Que 1.11. Express the following boolean function F in a sum of
minterms and a product of maxterms.
F(x, y, z) = (xy + z) (y + xz)
Answer
1. Given F(x, y, z) = (xy + z) (y + xz)
= xy.y + x.xyz + yz + xz.z
2. By associative property, x.x = x
Fm = xy + xyz + yz + xz = xy(z + z ) + xyz + (x + x )yz + xz(y + y )

= xyz + xy z + xyz + xyz + x yz + xyz + x y z
= xyz + xy z + x yz + x y z ( x  x  x)
F =m(3, 5, 6, 7)
FM = Fm = (x  y  z )( x  y  z)( x  y  z ) ( x  y  z )
F = M(0, 1, 2, 4)
Que 1.12. Simplify the following boolean expression to a minimum

number of literals.
i. AC + ABC + AC + AB
ii. ( x y + z) + z + xy + wz AKTU 2014-15, Marks 3.5
Answer
i. AC + ABC + AC + AB :
Let Y = AC  AC  AB  ABC
= C ( A  A)  A ( B  BC )
= C  A( B  C) [ A + A = 1]
= C  AC  AB [ C  AC  (C  A) (C  C )]
= C  A  AB
= C  A(1  B)
= AC
ii. y
( x + z) + z + xy + wz
Let Y = ( x y + z) + z + xy + wz
= x y + z + xy + wz
= x y + xy + z (1 + w)
= x y + xy + z = x  y + z [ 1 + w = 1]
Que 1.13. Convert the given expression into canonical SOP form
Y = A + AB + BC
Answer
Y = A( B  B)(C  C)  AB(C  C)  BC ( A  A)
Y = ( AB  AB)(C  C)  ABC  ABC  ABC  ABC

= ABC  ABC  ABC  ABC  ABC  ABC  ABC  ABC
= ABC  ABC  ABC  ABC  ABC

[  A + A = A]
Que 1.14. Convert the given expression into canonical POS form
Y = A(A + B )(A + B + C )
Answer
Y = ( A  B B  C C )( A  B  CC )( A  B  C )
= ( A  B B  C )( A  B B  C)( A  B  C )( A  B  C ) ( A  B  C )
= ( A  B  C )( A  B  C)( A  B  C )( A  B  C)
( A  B  C )( A  B  C )( A  B  C )
Y = ( A  B  C )( A  B  C)( A  B  C )( A  B  C)
PART-4
Karnaugh Maps Upto 6 Variables.
Questions-Answers
Que 1.15. Write a short note on Karnaugh map. Also show the
reduction of boolean expression and how to mark pairs. How gate-
level minimization is implemented ?
Answer
1. Karnaugh map is another way of presenting the information given by a
truth table. These maps are also known by the name K-map. Let us
consider the map for two variables. There may be four possible
combinations within four squares.
2. Each square represents unique minterms as shown in Fig. 1.15.1 :
B B B
A B A 0 1
A AB AB 0 00 01
0 1 0 1
OR
A AB AB 1 10 11
2 3 2 3
Fig. 1.15.1.
For three variables :
1. There are eight minterms for three binary variables. Hence the k-map
consists of eight squares.
2. The K-map drawn in Fig. 1.15.2, for three variables is marked with
numbers in each row and each column to show the relationship between
the squares and the three variables.
BC BC
A BC BC BC BC A 00 01 11 10
A m0 m1 m3 m2 0 000 001 011 010
0 1 3 2
OR
A m4 m5 m7 m6 1 100 101 111 110
4 5 7 6
Fig. 1.15.2.
3. For example, the square assigned to m5, which corresponds to row 1
and column 01. When these two numbers reconsidered, they give the
binary number 101, whose decimal equivalent is 5.
For four variables :
1. The map for boolean function of four binary variables require sixteen
minterms, hence the map consists of sixteen squares.
2. The listed terms are from 0 to 15, i.e., 16 minterms. The map shows the
relationship with the four variables.
3. In every square the numbers are written. The number denotes that
this square corresponds to that number’s minterm.
CD CD
AB CD CD CD CD AB 00 01 11 10
AB m0 m1 m3 m2 00 0000 0001 0011 0010

0 1 3 2
AB m4 m5 m7 m6 01 0100 0101 0111 0110

4 5 7 6
OR
AB m 12 m 13 m 15 m 14 11 1100 1101 1111 1110
12 13 15 14
AB m8 m9 m 11 m 10 10 1000 1001 1011 1010

8 9 11 10
Fig. 1.15.3.
Que 1.16. Simplify the boolean function.

F (w, x, y, z) = m(1, 3, 7, 11, 15)
which has the don't care conditions
d (w, x, y, z) = d(0, 2, 5) AKTU 2016-17, Marks 10
Answer
1. F(w, x, y, z) = m(1, 3, 7, 11, 15)
and don’t care conditions
d(w, x, y, z) = d(0, 2, 5)
2. The minterms of F are the variable combinations that make the function
equal to 1. The minterms of d are the don’t care minterms that may be
either 0 or 1.
3. The K-map simplification is shown in Fig. 1.16.1.
yz yz
wx 00 01 11 10 wx 00 01 11 10
00 × 11 1 × × 11 1 ×
0 3 2 00 0 3 2
01 0 × 1 0 0 0
4 5 7 6 01 4 ×5 1 7 6
11 0 0 1 0 11 0 0 1 0
12 13 15 14 12 13 15 14
10 0 0 1 0 0 09 1 11 0 10
8 9 11 10 10 8
F = yz + wx F = yz + wz
(a) Fig. 1.16.1. (b)
4. The minterms of F are marked by 1’s, those of d are marked by ×’s and
the remaining is filled with 0’s.
5. To get the simplified expression in SOP form, we must include all five 1’s
in the map, but we may or may not include any of the ×'s, depending on
the way the function is simplified.
6. In Fig. 1.16.1(a), don’t care minterms 0 and 2 are included with the 1’s,
resulting as
F = yz + wx
7. In Fig. 1.16.1(b), don’t care minterm 5 is included with the 1’s, resulting
as
F = yz + wz
8. The K-map in Fig. 1.16.1(b) is more feasible because, we have to use the
minimum don’t care.
Que 1.17. Simplify the following expression into product of sum

(POS) form
i. ABC  ABD  BCD
ii. ACD + CD + AB + ABCD AKTU 2014-15, Marks 3.5
Answer
1. Let Y = ABC  ABD  BCD
= ABC ( D  D)  AB (C  C) D  ( A  A) BCD
= ABCD  ABCD  ABCD  ABCD  ABCD  ABCD
Y = m(7, 9, 11, 12, 13, 15)
2. Now for POS form we will take complement function,

Y = M(0, 1, 2, 3, 4, 5, 6, 8, 10, 14)
3. Minimization through K-map is shown in Fig. 1.17.1.
CD
C+D C+D C+D C+D
AB
A+B 0 0 0 0
0 1 3 2
A+B 0 0 0
4 5 7 6
A+B 0
12 13 15 14
A+B 0 8 9 11
0 10
Fig. 1.17.1.
Y = (A + B) (A + C)( C + D) (B + D)
ii. ACD + CD + AB + ABCD
1. Let, Y = ACD  CD  AB  ABCD
= A ( B  B) CD  ( A  A)( B  B) CD  AB (C  C )( D  D)  ABCD
= ABCD  ABCD  ABCD  ABCD  ABCD
 ABCD  ABCD  ABCD  ABCD
Y = m(1, 5, 8, 9, 10, 11, 13, 14, 15)
2. Now for POS form, we have to take complement function,
Y =  M(0, 2, 3, 4, 6, 7, 12)
3. Minimization through K-map is shown in Fig. 1.17.2.
CD
AB C+D C+D C+D C+D
A+B 0 0 0
0 1 3 2
0 0 0
A+B
4 5 7 6
A+B 0
12 13 15 14
A+B
8 9 11 10
Fig. 1.17.2.
Y = (A + D) (A + C ) ( B + C + D)
Que 1.18. Implement the following boolean function with NAND
gates. F(x, y, z) =m(1, 2, 3, 4, 5, 7) AKTU 2016-17, Marks 10
Answer
1. The K-map simplification is shown in Fig. 1.18.1.
yz
x 00 01 11 10
0 1 1 1
0 1 3 2
1 1 1 1
4 5 7 6
Fig. 1.18.1.
2. Hence, the simplified function is
F = z  xy  xy
3. Implementation using NAND gates is shown in Fig. 1.18.2.
F = ( x  y ). ( x  y). ( z )
= z  xy  x. y
x y z
x y xy = x + y
xy = x + y
z
Fig. 1.18.2.
Que 1.19. Simplify the boolean function Y together with don't

care condition d using K-map and implement it with two level NAND
gate circuit.
Y = BD + BCD  ABCD AKTU 2014-15, Marks 3.5
Answer
1. Given, Y = BD  BCD  ABCD
= ( A  A) B (C  C ) D  ( A  A) BCD  ABCD
= ABCD  ABCD  ABCD  ABCD  ABCD  ABCD  ABCD

Y = m(5, 6, 7, 10, 13, 14, 15)
2. As there is not given any don’t care condition so K-map is as shown in

Fig. 1.19.1.
CD 00 01 11 10
AB
00 0 1 3 2
01 4 15 1 7 1 6
1 1 1
11
12 13 15 14
10 1
8 9 11 10
Fig. 1.19.1.
Y = BD + BC + ACD
3. NAND gate implementation :
B BD
D BD + BC
(BD + BC)
B BC
C
Y
A AC AC
C
D
D ACD
Fig. 1.19.2.
Que 1.20. Minimize the given boolean function using K-map.

F(A, B, C, D) = m(3, 4, 5, 7, 9, 13, 14, 15)
Answer
CD
AB CD CD CD CD
AB 1
0 1 3 2
AB 1 1 1
4 5 7 6
AB 1 1 1
12 13 15 14
AB 1
8 9 11 10
Fig. 1.20.1.
F = ABC + ACD + ACD + ABC

Que 1.21. Simplify the following Boolean function using K-map

Y = m(0, 1, 3, 5, 6, 7, 9, 11, 16, 18, 19, 20, 21, 22, 24, 26)
Answer
K-map :
f(C, D, E, A, B)
CDE 000 001 011 010 110 111 101 100
AB
00 1 1 1 1
0 4 12 8 24 28 20 16
01 1 1 1 1
1 5 13 9 25 29 21 17
11 1 1 1 1
3 7 15 11 27 31 23 19
10 1 1 1 1
2 6 14 10 26 30 22 18
Fig. 1.21.1
Y = DEAB  CDB  ACDE  CDAB  CDEB  CDEB  CDEA  CDEA
= DB( EA  CA)  CB( D  DE)  DE( AC  AC)  CE(DB  DA)
= DB( EA  CA)  CB( D  E)  DE( A  C )  CE( DB  DA)
Que 1.22. Simplify the Boolean function
F(A, B, C, D, E, F) = m(0, 5, 7, 8, 9, 12, 13, 23, 24, 25, 28, 29, 37, 40, 42, 44,
46, 55, 56, 57, 60, 61)
Answer
1. Group 1 and group 2 are two pairs of 1’s in the first 16-cell map.
2. Group 3 is formed by two isolated 1’s from first 16-cell map and third
16-cell map.
3. Group 4 is a combination of two quads from first 16-cell and second
16-cell map.
4. Similarly group 5 is a combination of two quads from second 16-cell map
and fourth 16-cell map.
5. Group 6 is again a combination is isolated 1’s from second and fourth
16-cell maps.
6. Finally group 7 is a quad within the third 16-cell map.
Group 2
AB (ABCDF) AB
EF EF
CD 00 01 11 10 CD 00 01 11 10
00 1 00
0 1 3 2 16 17 19 18
01 1 1 01 1
Group 1 4 5 7 6 20 21 23 22
ABDEF 1 1 1 1
11 11
12 13 15 14 28 29 31 30
Group 4
10 1 1 (ACE) 10 1 1
8 9 11 10 24 25 27 26
Group 3 Group 5 Group 6
(BCDEF) (BCE) (BCDEF)
EF AB EF AB
CD 00 01 11 10
CD 00 01 11 10
00 00
32 33 35 34 48 49 51 50
01 1 01 1
36 37 39 38 52 53 55 54
11 1 1 11 1 1
44 45 47 46 60 61 63 62
10 1 1 1 1
10
40 41 43 42 56 57 59 58
Group 7
(ABCF)
The expression is,
ABDEF  ABCDF  BCDEF

F=
 ACE  BCE  BCDEF  ABCF
PART-5
Tabulation (Quine-McCluskey) Method.
Questions-Answers
Que 1.23. What is the significance of Quine-McCluskey method or

tabular method ?
Answer
1. The K-map method is suitable for simplification of boolean function
upto 5 or 6 variables.
2. As the number of variables increases beyond this, the visualization of
adjacent square is difficult, as the geometry is more involved.
3. The Quine-McCluskey or tabular method is employed in such cases.
Consider the function,
F (A, B, C, D) = m(0, 2, 3, 6, 7, 8, 10, 12, 13) for simplifying using tabular
method.
Process of solving McCluskey method :
1. The binary representations are grouped a section of numbers in terms
of the number of 1’s index as shown in Table 1.23.1.
2. Now compare each binary term with every term in the next higher
category.
3. Make the two number sectional combination which differ by one bit.
4. Write binary form of the minterm cell.
5. Compare each binary term with higher adjacent cell and write the
combination of 4 cell which are differ by 1-bit.
6. Mark all combinations which are made by the digits of 4 cell.
7. Write the binary form of 4 cell and place a (_) in place of differ bit.
Table 1.23.1.
No. of Minterms Binary Minterms Binary Minterm Binary
1’s (2 cell) (4 cell)
0 m0 0000 0, 2 00_0 0, 2, 8, 10 _0_0
0, 8 _000
2, 3 001_ 2, 3, 6, 7 0_1_
m2 0010 2, 6 0_10
1 2, 10 _010
m8 1000 8, 10 10_0
8, 12 1_00
2 m3 0011 3, 7 0_11
m6 0110 6, 7 011_
m10 1010 12, 13 110_
m12 1100
3 m7 0111
m13 1101
8. Apply same process to the resultant stage.

9. All the terms which remain unchecked are the PI’s. Now prepare a PI
chart to determine essential prime implicants.
10. All the PI’s are represented in rows and each minterm of function in a
column as shown in Table 1.23.2.
11. Put the  in each row to show the composition of minterms that make
PI’s.
Table 1.23.2.
Prime      
Minterms implicant m0 m2 m3 m6 m7 m8 m10 m12 m13
ACD 8, 12  
ABC  12, 13  
BD  0, 2, 8, 10    
AC  2, 3, 6, 7    
13. The column that contains a single dot  is essential prime implicant.
14. A tick mark is put above each column which has only one  mark.
15. The sum of all EPI’s gives the function in its minimal SOP form.
 F(A, B, C, D) = ABC  BD  AC
Que 1.24. Minimize the following switching function using

Quine-McCluskey method.
F(x1, x2, x3, x4, x5 ) = m(0, 1, 2, 8, 9, 15, 17, 21, 24, 25, 27, 31)

Answer
Table 1.24.1. For obtaining all the prime implicants.
0 m0 00000 0, 1  0000_ 0, 1, 8, 9 0 _ 0 0 _C
1 m1 00001 0, 2 H 0 0 0 _ 0 1, 9, 17, 25 _ _ 0 0 1 B
m2 00010 0, 8  0 _ 0 0 0 8, 9, 24, 25 _ 1 0 0 _ A
m8 01000
1, 9  0_001
2 m9 0 1 0 01 1, 17  _0001
m17 10001 8, 9  0100_
m24 11000 8, 24  _1000
3 m21 10101 9, 25  _1001

m25 11001 17, 21 G 10_01
4 m15 01111 17, 25  1_001

m27 11 011 24, 25  1100_
5 m31 11111 25, 27 F 110_1

15, 31 E _1111
27, 31 D 11 _11
Table 1.24.2. Prime-implicant
  
Minterm m0 m1 m2 m8 m9 m15 m17 m21 m24 m25 m27 m31
A    
B    
C    
D  
E  
F  
G  
H  
So the essential prime implicants are,

F(x1, x2, x3, x4, x5) = E + G + A + H= x2 x3 x4 x5  x1 x2 x4 x5  x1 x2 x3 x5  x2 x3 x4
Que 1.25. Minimize the following using Quine-McClus key

method :
F(W, X, Y, Z) = m(0, 3, 5, 6, 7, 10, 12, 13) +d(2, 9, 15)
Answer
1. F(W, X, Y, Z) =m(0, 3, 5, 6, 7, 10, 12, 13) +d (2, 9, 15)
First, we group the minterms according to the numbers of 1’s.
0 m0 0000 0, 2* 00_0 2*, 3, 6, 7 0_1_
1 dm2 0010 2*, 3 001_ 5, 7, 13, 15* _ 1 _ 1
2 m3 0011 2*, 6 0_10
m5 0101 2*, 10 _010
m6 0110 3, 7 0_11
m10 1010 5, 7 01_1
m12 1100 5, 13 _101
dm9 1001 6, 7 011_
3 m7 0111 12, 13 110_
m13 1101 9*, 13 1_01
4 dm15 1111 7, 15* _111
13, 15* 11_1
2. Then, we prepare the table of prime implicants.
Prime
Minterm implicant m0 m3 m5 m6 m7 m10 m12 m13
WXZ  0, 2* 
XYZ  2*, 10 
WXY  12, 13  
WYZ 9*, 13 
WY  2*, 3, 6, 7   
XZ  5, 7, 13, 15*   
F(W, X, Y, Z) = WY  XZ  WXZ  XYZ  WXY
Que 1.26. Use Quine-McCluskey (QM) method to solve the

following function :
F (A, B, C, D) = m(5, 7, 8, 9, 10, 11, 14, 15)
AKTU 2014-15, Marks 3.5
Answer
1. F (A, B, C, D) = m(5, 7, 8, 9, 10, 11, 14, 15)
1. m8 1000 8, 9 100_ 8, 9, 10, 11 10_ _
2. m5 0101 8, 10 1 0 _ 0 10, 11, 14, 15 1 _ 1_
m9 1001 5, 7 01_1
m10 1010 9, 11 10_1
3. m7 0111 10, 11 101_
m11 1011 10, 14 1_10
m14 1110 7, 15 _111
4. m15 1111 11, 15 1_11
14, 15 111_
2. All the terms which are unchecked are prime implicants.
Now, we prepare a prime implicant chart to determine essential prime
implicant is as follows :
   
Minterms Prime implicants m5 m7 m8 m9 m10 m11 m14 m15
ABD  5, 7  
BCD  7, 15  
AB  8, 9, 10, 11    
AC  10, 11, 14, 15    
Therefore, F(A, B, C, D) = AC + AB  ABD

3. Logic diagram :
A AC
C
AB
F = AC + AB + ABD
B
ABD
D
Fig. 1.26.1.
Que 1.27. Use the Quine-McCluskey method to generate the set of

prime implicants for the following function :
F(A, B, C, D) = m(0, 1, 4, 5, 6, 7, 9, 11, 15) +  (10, 14).
Also obtain all minimal expressions for the function. Draw a logic
diagram using only NAND gates to implement your best solution
obtained.
Answer
1. Given, F(A, B, C, D) = Σ m(0, 1, 4, 5, 6, 7, 9, 11, 15) + φ Σ(10, 14)
0 m0 0000 0, 1  000_ 0, 1, 4, 5 0_0_
1 m1 0001 0, 4  0_00 4, 5, 6, 7 01__
m4 0100 1, 5  0 _ 0 1 6, 14*, 7, 15 _ 1 1 _
2 m5 0 1 01 1, 9 _001
m6 0110 4, 5  010_
m9 1001 4, 6  01_0
dm10 1010 5, 7  01_1
3 m7 0111 6, 7  011_
m11 1011 6, 14*  _110
dm14 1110 9, 11 10_1
4 m15 1111 10*, 11 101_
7, 15  _111
11, 15 1_11
14*, 15 111_
 
Minterms Prime m0 m1 m4 m5 m6 m7 m9 m11 m15
implicants
AC  0, 1, 4, 5    
AB 4, 5, 6, 7    
BC 6, 14*, 7, 15   
BC D 1, 9  
ABC  9,11  
AB'C ' 10*,11 
ACD 11,15  
ABC 14*, 15 
The essential prime implicant,
F(A, B, C, D) = AC
A
A
AC AC
C
C
Fig. 1.27.1.
Que 1.28. Minimize the following using Quine-McCluskey

method :
F(A, B, C, D) = m(0, 1, 9, 15, 24, 29, 30) + d(8, 11, 31)
Answer
1. Arrange minterms according to categories of 1’s as shown in table 1.28.1 :

Table 1.28.1.
No. Min- Binary Minterms Binary Min- Binary
of terms (2 cell) terms
1’s (4 cell)
A BC D E A B C D E ABCDE
0 m0 0 0 0 0 0 0, 1  0 0 0 0 – 0, 1, 8*, 9 0 – 0 0 –
m1 0 0 0 0 1 0, 8*  0 – 0 0 0
1
dm 8 0 1 0 0 0 1, 9  0 – 0 0 1
m9 0 1 0 0 1 8*, 9  0 1 0 0 –
2
m 24 1 1 0 0 0 8*, 24 – 1 0 0 0
3 dm 11 0 1 0 1 1 9, 11* 0 1 0 – 1
m15 0 1 1 1 1 11*, 15 0 1 – 1 1
4
m 29 1 1 1 0 1 15, 31* – 1 1 1 1
m 30 1 1 1 1 0 29, 31* 1 1 1 – 1
5 dm 31 1 1 1 1 1 30, 31* 1 1 1 1 –
2. List of prime implicants :

Table 1.28.2.
Prime implicants Binary representation
A B C D E
8*, 24 – 1 0 0 0
9, 11* 0 1 0 – 1
11*, 15 0 1 – 1 1
15, 31* – 1 1 1 1
29, 31* 1 1 1 – 1
30, 31* 1 1 1 1 –
0, 1, 8*, 9 0 – 0 0 –
3. Select the minimum number of prime implicants which must cover all
the minterms except don’t care minterms.
Table 1.28.3.
Prime implicant Minterm
    
0 1 9 15 24 29 30
8*, 24  
9, 11* 
11*, 15 
15, 31* 
29, 31*  
30, 31*  
0, 1, 8*, 9    
Y = BC DE  ABCE  ABCD  AC D
VERY IMPORTANT QUESTIONS

Following questions are very important. These questions
may be asked in your SESSIONALS as well as
UNIVERSITY EXAMINATION.
Q. 1. Design a combinational circuit that converts a BCD code

to excess-3 code.
Ans. Refer Q. 1.4, Page 1–6B, Unit-1.
Q. 2. Simplify the following boolean expression to a minimum

number of literals.
ii. ( x y + z) + z + xy + wz
Q. 3. Simplify the boolean function.

F (w, x, y, z) = m(1, 3, 7, 11, 15)
d (w, x, y, z) = d(0, 2, 5)
Q. 4. Simplify the boolean function Y together with don’t care

condition d using K-map and implement it with two level
NAND gate circuit.
Y = BD + BCD  ABCD
Q. 5. Simplify the following Boolean function using K-map

Y = m(0, 1, 3, 5, 6, 7, 9, 11, 16, 18, 19, 20, 21, 22, 24, 26)
Q. 6. Minimize the following s witching function using

F(x1, x2, x3, x4, x5 ) = m(0, 1, 2, 8, 9, 15, 17, 21, 24, 25, 27, 31)
Q. 7. Use Quine-McCluskey (QM) method to solve the following

function :
F (A, B, C, D) = m(5, 7, 8, 9, 10, 11, 14, 15)

2 MSI Devices
CONTENTS
Part-1 : MSI Devices Like Comparators ............... 2–2B to 2–4B
Part-2 : Multiplexers ............................................... 2–5B to 2–11B
Part-3 : Encoder ..................................................... 2–12B to 2–14B
Part-4 : Decoder ..................................................... 2–14B to 2–19B
Part-5 : Driver and Multiplexed Display ........... 2–19B to 2–20B
Part-6 : Half and Full Adders .............................. 2–20B to 2–23B
Part-7 : Subtractors ............................................... 2–23B to 2–26B
Part-8 : Serial and Parallel Adders .................... 2–26B to 2–27B
Part-9 : BCD Adder ............................................... 2–27B to 2–28B
Part-10 : Barrel Shifter and ALU ......................... 2–29B to 2–30B

2–2 B (EC-Sem-3) MSI Devices
PART-1
MSI Devices Like Comparators.
Questions-Answers
Que 2.1. What is magnitude comparator ? Design a three bit

comparator circuit using logic gates.
Answer
1. A magnitude comparator is a combinational circuit designed primarily
to compare the relative magnitude of the two binary numbers A and B.
2. Naturally, the result of this comparison is specified by three binary
variables that indicate, whether A > B, A = B or A < B.
3. The block diagram of a single bit magnitude comparator is shown in
Fig. 2.1.1.
A A>B
Inputs Magnitude
A=B
B Comparator A<B
Fig. 2.1.1.
4. EX-OR and AND gate is used to implement the circuit. If the
EX-OR gate and two AND gates are combined, the circuit will function
as a single bit magnitude comparator as shown in Fig. 2.1.2.
5. The circuit diagram and truth table of a single bit magnitude comparator
is shown in Fig. 2.1.2.
A Z1 Inputs Outputs
A B Z1 Z2 Z3
AB
Z2 0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
Z3
B 1 1 0 1 0
Fig. 2.1.2.
Z1 is high when A > B,

Z2 is high when A = B,
Z3 is high when A < B.
The same concept is adopted to form an n-bit magnitude comparator.

3-bit magnitude comparator :
A = A2 A1 A0
B = B2 B1 B0
Two number A and B are equal, only if all the pairs of significant digits
are equal. i.e.,
A2 = B2, A1 = B1, A0 = B0
When numbers are binary, then equality relation of each pair of bits
can be expressed by the equivalent function as,
xi = Ai Bi  Ai Bi , i = 0, 1, 2
Design procedure :
i. (A = B) = x 2. x1. x0 = ( A2  B2 ) ( A1  B1 ) ( A0  B0 )
ii. (A > B) = A2 B2  x2 A1 B1  x2 x1 A0 B0
iii. (A < B) = A2 B2  x2 A1 B1  x2 x1 A0 B0
A2
x2 (A < B)
B2
A1
x1
B1 (A > B)
A0
x0
B0
(A = B)
Fig. 2.1.3. 3-bit magnitude comparator using logic gates.
Que 2.2. Design and explain the logic and circuit of 4-bit
magnitude comparator. AKTU 2014-15, Marks 06

OR
Design a 4-bit magnitude comparator using one bit comparator
modules. AKTU 2015-16, Marks 10
OR
Draw and explain 4-bit magnitude comparator.
Answer
1. Let two numbers A and B with four digits each.
A = A3 A2 A1 A0
B = B3 B2 B1 B0
2. The two numbers are equal if all pairs of significant digits are equal,
i.e., if A3 = B3, A2 = B2, A1 = B1 and A0 = B0. Equality relation is generated
by EX-NOR gate.
xi = Ai Bi  Ai Bi ; i = 0, 1, 2, 3.
where xi is equality of two numbers
xi = 1, if A = B
xi = 0, otherwise,
(A = B) = x3x2x1x0 = 1, if all pairs are equal.
3. To determine if A > B or A < B,
(A > B) = A3 B3  x3 A3 B2  x3 x2 A1 B1  x3 x2 x1 A0 B0
(A < B) = A3 B3  x3 A2 B2  x3 x2 A1 B1  x3 x2 x1 A0 B0
4. The logical implementation is shown in Fig. 2.2.1.
A3
x3
B3
A2
x2
B2
(A < B)
A1
x1
B1
A0
x0
(A > B)
B0
(A = B)
Fig. 2.2.1. 4-bit magnitude comparator using logic gates.

PART-2
Multiplexers.
Questions-Answers
Que 2.3. What is the role of multiplexer in the digital electronics ?

Explain the logic how it selects a one input among several inputs.
Answer
1. A multiplexer (MUX) is a combinational circuit that selects one input
out of several inputs and directs it to a single output.
2. The particular input selection is controlled by a set of select inputs.
3. The block diagram of a digital multiplexer with n input lines and single
output line is shown in Fig. 2.3.1(a).
I0
I0
I1 n:1 I1
Y 4:1
MUX I2 Y
MUX
In I3
S0 S1 Sm S1 S0
(a) n : 1 MUX (b) 4 : 1 MUX
Fig. 2.3.1.
4. For selecting one input out of n inputs, a set of m select inputs is
required where, n = 2m
5. On the basis of binary code applied at the select inputs, one output of
n data source is selected. An enable input (E) is built-in for cascading
purpose. Enable input is generally active low.
6. A circuit diagram for a possible 4 : 1 data multiplexer as shown in
Fig. 2.3.1(b).
Que 2.4. Implement the function :

F(A, B, C) = ABC + ABC + ABC + ABC
Using 4 : 1 multiplexer using B and C variables to the selection lines.
Answer
1. Given, F(A, B, C) = ABC + ABC + ABC + ABC
2. Implementation using 4 : 1 MUX, F(A, B, C) = Σm(1, 2, 4, 7)
Input I0 I1 I2 I3 A A
I0
0 A I1 4 : 1
A 1 2 3 F
MUX
A I2
4 5 6 7 A
I3
Output to A A A A A
multiplexer
Fig. 2.4.1. B C
Que 2.5. Construct a 16 × 1 multiplexer with two 8 × 1 and one

2 × 1 multiplexer. Use block diagrams.
Answer
S0 S0
S1 S1
S2 S2
0 0
1 1
2 2 8×1
3 3 MUX
4 4
5 5
6 6
7 7
2×1
y
S0 MUX
S1
S2
8 0 S3
9 1 8×1
10 2
11 3 MUX
12 4
13 5
14 6
15 7
Fig. 2.5.1.
Que 2.6. Design the following boolean function using 4 × 1
multiplexer. AKTU 2014-15, Marks 06
F(A, B, C, D) = m(0, 1, 3, 4, 8, 9, 15)

Answer
1. Given, F (A, B, C, D) = m(0, 1, 3, 4, 8, 9, 15)
2. We have to design it using 4 : 1 multiplexer, so we can use two variable
(A, B) for select lines and implementation table is as follows :
I0 I1 I2 I3
CD 0 4 8 12
CD 1 5 9 13
CD 2 6 10 14
CD 3 7 11 15
C+D CD C CD
3. Now, I0 = CD  CD  CD  C  D
I1 = CD
I2 = CD  CD  C
I3 = CD
4. Logic diagram is shown in Fig. 2.6.1
C
I0
D
I1 4 × 1
F (A, B, C, D)
MUX
I2
I3
A B
Fig. 2.6.1.
Que 2.7. Design the following boolean function using the

multiplexer :
F(A, B, C, D) = m(0, 3, 5, 6, 8, 9, 14, 15).
Answer
F(A, B, C, D) = m(0, 3, 5, 6, 8, 9, 14, 15)
A 1
D0
D1
D2
D3 8 : 1 Y
D0 D1 D2 D3 D4 D5 D6 D7 D MUX
4
A 0 1 2 3 4 5 6 7 D5
D6
A 8 9 10 11 12 13 14 15 D7
1 A 0 A 0 A 1 A 0 B C D
( a) Implementation table (b) Multiplexer implementation
Fig. 2.7.1.
Que 2.8. Implement the function F = m(0, 1, 3, 4, 7, 8, 9, 11, 14, 15)
using 8:1 mux. AKTU 2017-18, Marks 07
Answer
1. The given Boolean function is a four variable function. Any one variable
of the function can be taken as input to the MUX and the remaining
variables are connected to the selection lines.
Decimal A B C D
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
2. A is assumed to be MUX input and B,C, D are used as selection lines.
i. A is complement variable of A for the minterm 0 to 7.

ii. A is normal variable (A) for the minterm 8 to 15.
3. We enter the co mplement variable minterms in first row of
implementation table and enter normal variable minterm in second
row of implementation table.
Implementation table :
I0 I1 I2 I3 I4 I5 I6 I7
A 0 1 2 3 4 5 6 7
A 8 9 10 11 12 13 14 15
1 1 0 1 A 0 A 1
Logic diagram :
Logic 1
Logic 0 I0
I1
I2
I3 8:1
A I4 F(A, B, C, D)
MUX
I5
I6
I7
B C D
Fig. 2.8.1.
Que 2.9. Implement the following Boolean function.

F(A, B, C, D) = (0, 1, 3, 4, 7, 8, 9, 11, 14, 15)
i. 4 : 1 MUX
ii. 2 : 1 MUX AKTU 2018-19, Marks 07
Answer
i. 4 : 1 MUX :
AB AB AB AB
I0 I1 I2 I3
(00) C D 0 4 8 12
(01) C D 1 5 9 13
(10) C D 2 6 10 14
(11) C D 3 7 11 15
First column (I0) = C D  CD  CD

= C ( D  D)  CD = C  CD
= CD
Second column (I1)
= CD  CD = C  D [ EX-NOR]
Third column (I2)
= CD  CD  CD
= C( D  D)  CD
= C  CD = C  D
Fourth column (I3)
= CD  CD
= C( D  D) = C
Logic diagram :
C
D I0
I1
4:1 F(A, B, C, D)
I2 MUX
I3
Select
A B lines
Fig. 2.9.1.
ii. Implementation using 2 : 1 MUX :
We have to use three variables as input of MUX and one variable as
select line
D D
I0 I1
ABC 0 1
ABC 2 3
ABC 4 5
ABC 6 7
ABC 8 9
ABC 10 11
ABC 12 13
ABC 14 15
First column (I0)

= ABC  ABC  ABC  ABC
= AC ( B  B)  A( BC  BC)
= AC  A( B  C )
Second column (I1)
= ABC  ABC  ABC  ABC  ABC  ABC
= BC ( A  A)  BC ( A  A)  BC( A  A)
= BC  BC  BC
= B (C  C)  BC
= B  BC
= BC
Logic diagram :
A
C
I0
B
C
2:1
F(A, B, C, D)
MUX
A
B
I1
C
Select line
D
Fig. 2.9.2.
PART-3
Encoder.
Questions-Answers
Que 2.10. What do you mean by encoder ?
Answer
Encoder :
1. The encoder is another example of combinational circuit that performs
the inverse operation of a decoder. It is designed to generate a different
output code for an input which becomes active.
2. In an encoder, the number of outputs is less than the number of
inputs. There are 2n input lines and n output lines.
3. The block diagram of an encoder is shown in Fig. 2.10.1.
2n n
inputs Encoder outputs
Fig. 2.10.1.
Que 2.11. What is priority encoder ? Explain with the help of

suitable example.
OR
Write a short note on priority encoder. AKTU 2018-19, Marks 07
Answer
Priority encoder : In priority encoder if two or more inputs are equal
to 1 at the same time, the input having highest priority will be considered.
Example :
Four inputs D0, D1, D2, D3 where D3 has highest priority and D0 has
lowest priority.
Y0, Y1 : binary output
V : validity of output
Table 2.11.1 Truth table for 4-bit priority encoder.
Input Output
D0 D1 D2 D3 Y1 Y0 V
0 0 0 0 × × 0
1 0 0 0 0 0 1
× 1 0 0 0 1 1
× × 1 0 1 0 1
× × × 1 1 1 1
D2D3 For Y1 D2D3 For Y0

D0D1 00 01 11 10 D0D1 00 01 11 10
00 1 1 1 00 1 1
0 1 3 2 0 1 3 2
01 1 1 1 01 1 1 1
4 5 7 6 4 5 7 6
11 1 11 1 1
12 13 1 15 1 14 12 13 1 15 14
10 1 1 1 10 1 1
8 9 11 10 8 9 11 10
Y 1 = D 2 + D3 Y 0 = D 3 + D1D2
D2D3 For V
D0D1 00 01 11 10
00 1 1 1
0 1 3 2
01 1 1 1 1
4 5 7 6
11 1 1 1 1
12 13 15 14
10 1 1 1 1
8 9 11 10
V = D0 + D 1 + D2 + D 3
Fig. 2.11.1.
Logic diagram :
D3 D2 D1 D0
Y0
Y1
Fig. 2.11.2.
PART-4
Decoder.
Questions-Answers
Que 2.12. Write a short note on decoder.
Answer
1. A decoder is a combinational circuit that converts binary information
from n input lines to a maximum of 2n unique output lines.
2. If the n-bit coded information has unused combinations, the decoder
may have fewer than 2n outputs.
3. The decoders presented here are called n to m line decoders, where
m  2n. Their purpose is to generate the 2n (or fewer) minterms of n
input variables.
n input lines n : 2n m output lines

decoder m = 2n
Enable
Fig. 2.12.1. Block diagram of a decoder.
2 to 4 binary decoder :
Fig. 2.12.2 shows the 2 to 4 decoder. Here 2 represent the input lines and
4 represents output lines. Fig. 2.12.2 shows the truth table for a
2 to 4 decoder. If enable (E) is 1, one and only one of the outputs Y0 to Y3
is active for the given input.
Inputs Outputs A B Enable

E
E A B Y3 Y2 Y1 Y0
0 X X 0 0 0 0
1 0 0 0 0 0 1 Y0
1 0 1 0 0 1 0 Y1
1 1 0 0 1 0 0 Y2
1 1 1 1 0 0 0 Y3
Fig. 2.12.2. Logic diagram of 2 to 4 decoder.
Que 2.13. Using a decoder and external gates, des ign the
combinational circuit defined by the following three boolean
functions :
F1 = xyz + xz, F2 = xyz + yz, F 3 = xyz + xy
Answer
Let us consider 3 to 8 line decoder. The implementation of the given
three functions using 3 to 8 line decoder and a few OR gates are shown
as follows :
F1 = xyz + xz = xyz + xz(y + y)
= xyz + xyz + xyz =  m(2, 7, 5)
F2 = xyz + yz = xyz + (x + x)yz
= xyz + xyz + xyz =  m(2, 4, 6)
F3 = xyz + xy = xyz + xy(z + z)
= xyz + xyz + xyz= m(0, 6, 7)
Y0
Y1
x
Y2
F1
3:8 Y3
y
Decoder Y4
F2
Y5
z
Y6 F3
Y7
Fig. 2.13.1. Implementation of the given Boolean function using 3:8 decoder.
Que 2.14. Draw the logic diagram of a two to four line decoder
using NOR gates only. AKTU 2016-17, Marks 10
Answer
Truth table :
Enable Input Output
E A B Y3 Y2 Y1 Y0
0 × × 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
Circuit using NOR gate :
A
Y 0 = (A + B + E) = A B E
B
Y 1 = (A + B + E) = A B E
Y 2 = (A + B + E) = A B E
Y 3 = (A + B + E) = A B E
E
Fig. 2.14.1.
Que 2.15. Design a full subtractor circuit with a decoder and two
OR gates.
Answer
Full subtractor using decoder :
Input Output
A B C D B0
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Difference : D = m(1, 2, 4, 7)
Borrow : B0 = m(1, 2, 3, 7)
0
1 D
A 2
3:8 3
B Decoder 4
5
C
6 B0
7
Fig. 2.15.1. Full subtractor using 3:8 decoder.
Que 2.16. Design a BCD to 7 segment decoder. Assume positive
logic, minimize the function. AKTU 2014-15, Marks 06
Answer
1. The truth table for a BCD to 7 segment decoder is as given as follows :
Digit BCD input 7-segment
A B C D a b c d e f g
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 1 0 1 1
2. The unused BCD codes are 1010, 1011, 1100, 1101, 1110, and 1111. So
place × (don’t care condition) for these corresponding cells.
CD For a CD For b
00 01 11 10 00 01 11 10
AB AB
1 1 1 1 1 1 1
00 0 1 3 2 00 0 1 3 2
01 1 1 1 01 1 1
4 5 7 6 4 5 7 6
11 × × × 11
× 12 13 15 14
× × × ×
12 13 15 14
10 1 1 × × 1 1 × ×
10
8 9 11 10 8 9 11 10
a = A + C + BD+ BD b = B + CD+ CD
CD For c CD For d
00 01 11 10 00 01 11 10
AB AB
1 1 1
00 1 0 1 1 1 3 2 00 0 1 3 2
01 01 1 1
1 4 15 1 7 1 6 4 5 7 6
11 × × × × 11 × × × ×
12 13 15 14 12 13 15 14
10 1 × × 10 1 1 × ×
8 9 11 10 8 9 11 10
c=B+C+D d = BD + CD + BCD + BC + A
For e CD For f
CD
00 01 11 10 00 01 11 10
AB AB
1 1 10
00 0 1 3 2 00 1 3 2
01 4 5 7 1 6 01 14 15 7 1 6
11 × × × × 11 × × × ×
12 13 15 14 12 13 15 14
10 1 × × 10 1 1 × ×
8 9 11 10 8 9 11 10
e=BD+CD f = A + CD+ B C + B D
CD For g
00 01 11 10
AB
1 1
00 0 1 3 2
01 1 1 1
4 5 7 6
11 × × × ×
12 13 15 14
10 1 1 × ×
8 9 11 10
g = A + B C+ B C + C D
Fig. 2.16.1.
3. Fig. 2.16.2 shows the logic diagram of BCD to 7 segment display decoder.
A B C D
BD
a
BD
CD
b
CD
CD
BCD
d
BC e
BC
f
BD
g
Fig. 2.16.2.
PART-5
Driver and Multiplexed Display.
Questions-Answers
Que 2.17. Explain multiplexed display.
Answer
1. In a multiplexed display, each seven-segment display is lit in turn with
its appropriate value. This is done by outputting the appropriate lines
with one part of the driver chip, while another part of the logic enables
the common cathode connection of the selected seven-segment display,

(Fig. 2.17.1).
2. Then a small time later, the common cathode of the next display is
activated and lit with its required number.
3. Thus if you could look at the display in slow motion, you would see each
of the seven segment displays light then go out sequentially.
4. The trick is that if the displays are strobed sufficiently rapidly (say a few
hundred times a second) the eye is deceived into thinking they are on all
the time, just like a television set.
5. The advantages of multiplexed displays are as follows: only one set of
current-limiting resistors is required, fewer wiring connections need to
be made and power consumption is less since only one seven-segment
display is lit at any given time.
6. Also, since multiplexed display chips are available from manufacturers,
you do not have to design and build one yourself.
g
f
e
d
c
b
a
Multiplex 330
driver a g a g a g
/A lit A B C
/B lit
/C lit
A
B
C
A lit B lit C lit
Fig. 2.17.1.
PART-6
Half and Full Adders.
Questions-Answers

Que 2.18. Describe half adder and full adder in brief. Implement
the circuit using logic gates.
OR
Design a full adder using two half adders.
AKTU 2015-16, Marks 7.5
Answer
Half adder :
1. The block diagram of half adder is shown in Fig. 2.18.1.
A S
Half Adder
B C
Fig. 2.18.1. Half adder.
where, A and B are the inputs and S and C are the outputs sum and
carry respectively.
2. The truth table and K-map of the system are shown in Fig. 2.18.2.
Input Output For S For C

B B
A B S C A 0 1 0 1
A
0 0 0 0
0 1 0
0 1 1 0 0 1 0 1
1 0 1 0
1 1 1 1
1 1 0 1 2 3 2 3
Fig. 2.18.2.
3. Using two-variable K-map, separately for the sum and carry.

S = AB  AB = A  B
C = AB
4. The circuit can be implemented using XOR gate.
A
B S
C
Fig. 2.18.3.
Full adder :
1. Full adder is a circuit that performs the addition of three binary digits. It
has three inputs A, B and C with two output S and Co, where C is the
previous carry. The block diagram is shown in Fig. 2.18.4.
A S
B Full Adder
C Co
Fig. 2.18.4. Full Adder.
2. If there are three input variables the combinations are eight (23 = 8).
Now form the truth table of the full adder.
Inputs Outputs
A B C S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
For S For C0
BC BC
00 01 11 10 00 01 11 10
A A
0 1 1 0 1
0 1 3 2 0 1 3 2
1 1 1 1 1 1 1
4 5 7 6 4 5 7 6
Fig. 2.18.5.
3. Sum : S = ABC  ABC  ABC  ABC
Carry : Co = AB + AC + BC
4. A full adder can be implemented using two half adders and one OR gate.
Sum : S = ABC + ABC  ABC  ABC
= ABC + ABC  ABC  ABC
= C ( AB  AB)  C ( AB  AB)
= C ( AB  AB)  C ( AB  AB)
= (A  B)  C
= AB + C (A + B)
= AB  C ( A  B) ( A  A) ( B  B)
= AB  C [ AB  AB  AB]
= AB  ABC  C ( AB  AB)
= AB (1 + C) + C (A  B)
= AB + C (A  B)
Half adder
A
B S
C Co
Fig. 2.18.6. Full adder circuit using 2 half adder.
Que 2.19. Implement a full adder circuit using 4 × 1 multiplexer.
Answer
1. Canonical form of sum and carry for full adder :
Sum = m(1, 2, 4, 7) = BCA  BCA  BCA  BCA
Carry = m(3, 5, 6, 7) = BCA  BCA  BCA  BCA
= BCA  BCA  BC
For sum :
I0 I1 I2 I3 A I0
I1 4 : 1
A Sum
0 1 2 3 I2 MUX
A 4 5 6 7 I3
A A A A B C
Implementation table MUX implementation for sum
Fig. 2.19.1.
For carry :
I0 I1 I2 I3 0 I0
A I1 4 : 1
A 0 1 2 3 Carry
I2 MUX
A 4 5 6 7 1 I3
0 A A 1 B C
Implementation table MUX implementation for carry
Fig. 2.19.2.
PART-7
Subtractors.
Questions-Answers
Que 2.20. Describe a half subtractor with its logic diagram.
Answer
1. The block diagram is shown in Fig. 2.20.1.
A D
Half subtractor
B B0
Fig. 2.20.1. Half subtractor.
2. It has two inputs, A (minuend) and B (subtrahend) and two outputs D

(difference) and Bo (borrow) are produced by subtraction of two bits.
3. The truth table can be formed by keeping in mind that difference (output)
is 0 if A = B and 1 if A  B. The K-map and truth table are shown in
Fig. 2.20.2.
Inputs Outputs B B
A 0 1 A 0 1
A B D B0
0 1 0 1
0 0 0 0 0 1 0 1
0 1 1 1 1
1 1
1 0 1 0 2 3 2 3
1 1 0 0 D = AB + AB = A  B B o = A B
Fig. 2.20.2.
4. The logical implementation using basic logic gates and XOR gate :
A
B D
XOR gate
implementation
Bo
Fig. 2.20.3.
Que 2.21. Design a full subtractor circuit with three inputs x, y,

Bin and two outputs Diff and Bout. The circuit subtracts x – y – B in,
where, Bin is the input borrow, Bout is the output borrow and Diff is
the difference. AKTU 2016-17, Marks 10
Answer
1. It is a combinational circuit that performs the subtraction of three binary
digits.
x Diff
y Full subtractor
Bin Bout
Fig. 2.21.1.
2. Fig. 2.21.1 shows the block diagram approach of full subtractor. It has
three inputs x, y and Bin and two outputs ‘Diff’ and Bout produced by
subtraction of three input bits.
3. For the formation of truth table, eight possible combinations of three
input variables with their outputs are required.
Inputs Outputs
x y Bin Diff Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
4. Using the concept of K-map, reduce the truth table to a function (algebraic
or boolean).
yBin yBin
x 00 01 11 10 x 00 01 11 10
0 1 1 0 1 1 1
0 1 3 2 0 1 3 2
1 1 1 1 1
4 5 7 6 4 5 7 6
Diff = x y Bin + x y Bin + xyBin + xyBin Bout = x Bin + yBin + xy

Fig. 2.21.2.
5. A full subtractor can also be implemented using two half subtractors
and an OR gate.
Diff = xyBin  xy Bin  xy Bin  x yBin
= Bin ( xy  x y )  Bin ( x y  x y)
= Bin ( x  y)  Bin ( x  y)  ( x  y)  Bin
and Bout = x y  x Bin  yBin  x y  Bin (x  y)
= x y  Bin ( x  y) ( x  x) ( y  y)
= xy  Bin ( xy  xy  x y)  xy  xyBin  Bin ( xy  x y)
= x y( Bin  1)  Bin ( x  y)  x y  Bin ( x  y)
Half subtractor
B in Diff
x
y
B out
Fig. 2.21.3. Full subtractor circuit using 2 half subtractor.

Que 2.22. Draw a full subtractor circuit using NAND gate.
AKTU 2018-19, Marks 3.5
Answer
Full subtractor using only NAND gates
= A  B  Bin  ( A  B)( A  B) Bin Bin ( A  B) Bin
Bout = AB  Bin ( A  B) = AB  Bin ( A  B)
= AB . B ( A  B)  B( A  B) B  B  ( A  B) 
in in  in 
Bout = B AB Bin  Bin ( A  B)
By using the above expressions for D and Bout, the full subtractor is
implemented using only NAND gates as shown in Fig. 2.22.1.
A
B D
Bin
Bout
Fig. 2.22.1. Full subtractor using only NAND gate.
PART-8
Serial and Parallel Adders.
Questions-Answers
Que 2.23. Design a 4-bit binary parallel adder.
Answer
1. The sum of two n-bit binary numbers, A and B, can be generated in two
ways: either in a serial fashion or in parallel.
2. The series addition method uses only one full-adder circuit and a storage
device to hold the generated output carry.
3. The pair of bits in A and B are transferred serially, one at a time,
through the single full-adder to produce a string of output bits for the
sum.
4. The stored output carry from one pair of bits is used as an input carry
for the next pair of bits.
5. The parallel method uses n full-adder circuits, and all bits of A and B
are applied simultaneously.
6. A binary parallel adder is a digital function that produces the arithmetic
sum of two binary numbers in parallel.
7. It consists of full-adders connected in cascade, with the output carry
from one full-adder connected to the input carry of the next full-adder.
B4 A4 B3 A3 B2 A2 B1 A1
C5 C4 C3 C2 C1
FA FA FA FA
S4 S3 S2 S1
Fig. 2.23.1. 4-bit full adders.
PART-9
BCD Adder.
Questions-Answers
Que 2.24. Draw a BCD adder circuit and explain its working.

OR
Draw a decimal adder to add BCD number.
Answer
1. BCD adder is circuit that adds two BCD digits in parallel and produces a
sum digit which is also BCD. BCD numbers use 10 symbols (group of
4 bits 0000 to 1001). BCD adder circuit must be able to do the following
and it is shown in Fig. 2.24.1.
2. Add two 4-bit BCD numbers using straight binary addition.
3. If 4-bit sum is equal to or less than 9, the sum is a valid BCD number and
no correction is needed.
4. If the 4-bit sum is greater than 9 or if a carry is generated from the sum,
the sum is invalid BCD number. Then the digit 6 (0110)2 should be added
to the sum to produce the valid BCD symbols.
Addend (BCD digit) Augend (BCD digit)
Binary adder-1 Carry in

K
Z8 Z4 Z2 Z 1
Output
carry
C
C = K + Z8 Z 4 + Z 8 Z 2
0
4-bit binary adder
S8 S4 S2 S1
Fig. 2.24.1. Block diagram of a BCD adder.
Binary Sum BCD Sum Decimal

Z8 Z4 Z2 Z1 C S8 S4 S2 S1
0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 1 1
0 0 1 0 0 0 0 1 0 2
0 0 1 1 0 0 0 1 1 3
0 1 0 0 0 0 1 0 0 4
0 1 0 1 0 0 1 0 1 5
0 1 1 0 0 0 1 1 0 6
0 1 1 1 0 0 1 1 1 7
1 0 0 0 0 1 0 0 0 8
1 0 0 1 0 1 0 0 1 9
1 0 1 0 1 0 0 0 0 10
1 0 1 1 1 0 0 0 1 11
PART-10
Barrel Shifter and ALU.
Questions-Answers
Que 2.25. Explain barrel shifter.
Answer
1. A barrel shifter performs a right rotate operation. It handles left
rotations using the complementary shift amount.
2. Barrel shifters can also perform shifts when suitable masking hardware
is included.
3. Barrel shifters come in array and logarithmic forms; we focus on
logarithmic barrel shifters because they are better suited for large
shifts.
A3 A2 A1 A0 A3 A2 A1 A0 left
Preshift
K1
S1
K0 K1
Y3 Y2 Y1 Y0 S0
K0
Y3 Y2 Y1 Y0
(a) (b)
A3 A2 A1 A0 left
K1
K0
X3 X2 X1 X0
sign Mask
arithmetic
shift
Y3 Y2 Y1 Y0
(c)
Fig. 2.25.1.
4. Fig. 2.25.1(a) shows a simple-4 bits barrel shifter that performs right
rotations. How, unlike funnel shifters, barrel shifters contain long
wrap-around wires.
5. In a large shifter, it is beneficial to upsize or buffer the drivers for
these wires. Fig. 2.25.1(b), shows an enhanced version that can rotate
left by prerotating right by 1, then rotating right by k .
6. Performing logical or arithmetic shifts on a barrel shifter requires a
way to mask out the bits that are rotated off the end of the shifter, as
shown in Fig. 2.25.1(c).
Que 2.26. Write a short note on Arithmetic Logic Unit (ALU).
Answer
1. An Arithmetic Logic Unit (ALU) is a multioperation, combinational
logic digital function.
2. It can perform a set of basic arithmetic operations and a set of logic
operations. The ALU has a number of selection lines to select a
particular operation in the unit.
3. The selection lines are decoded within the ALU so that k selection
variables can specify up to 2k distinct operations.
4. Fig. 2.26.1 shows the block diagram of a 4-bit ALU.
5. The four data inputs from A are combined with the four inputs from B
to generate an operation at the F output.
6. The mode-select input s2 distinguishes between arithmetic and logic
operations.
7. The two function-select inputs s1 and s0 specify the particular arithmetic
or logic operation to be generated. With three selection variables, it is
possible to specify four arithmetic operations (with s2 in one state) and
four logic operations (with s2 in the other state).
8. The input and output carries have meaning only during an arithmetic
operation.
9. The input carry in the least significant position of an ALU is quite often
used as fourth selection variable that can double the number of
arithmetic operations. In this way, it is possible to generate four more
operations, for a total of eight arithmetic operations.
A B
A4 A3 A2 A1 B 4 B3 B2 B1 s2 (Mode-select)
Arithmetic logic unit s1
Cout
(ALU) s 0 (Function-select)
(Output carry)
F4 F3 F2 F1 Cin (Input carry)
F
Fig. 2.26.1.

Q. 1. Draw and explain 4-bit magnitude comparator.

Q. 2. Design the following boolean function us ing 4 × 1
multiplexer.
F(A, B, C, D) = m(0, 1, 3, 4, 8, 9, 15)
Q. 3. Implement the function F = m(0, 1, 3, 4, 7, 8, 9, 11, 14, 15)
using 8:1 mux.
Q. 4. Using a decoder and external gates, des ign the
combinational circuit defined by the following three
boolean functions :
F1 = xyz + xz, F2 = xyz + yz, F 3 = xyz + xy
Q. 5. Draw the logic diagram of a two to four line decoder using
NOR gates only.
Q. 6. Implement the following Boolean function.
F(A, B, C, D) = (0, 1, 3, 4, 7, 8, 9, 11, 14, 15)
i. 4 : 1 MUX
ii. 2 : 1 MUX
Q. 7. Design a full adder using two half adders.
Q. 8. Design a full subtractor circuit with three inputs x, y, Bin
and two outputs Diff and B out . The circuit subtracts
x – y – B in, where, Bin is the input borrow, Bout is the output
borrow and Diff is the difference.
Q. 9. Draw a BCD adder circuit and explain its working.
Q. 10. Draw a full subtractor circuit using NAND gate.

3–1 B (EC-Sem-3) Digital System Design
3 Sequential Logic
Design
CONTENTS
Part-1 : Building Block Like S-R Flip Flop ........... 3–2B to 3–3B
Part-2 : JK and Master-Slave JK FF ..................... 3–3B to 3–5B
Part-3 : Edge Triggered FF ...................................... 3–5B to 3–6B
Part-4 : State Diagram, State Reduction ............ 3–6B to 3–16B

Design of Sequential Circuits
Part-5 : Ripple and Synchronous Counters ..... 3–16B to 3–24B
Part-6 : Shift Registers ......................................... 3–24B to 3–31B
Part-7 : Finite State Machines (FSM), .............. 3–31B to 3–33B

Design of Synchronous FSM
Part-8 : Algorithmic State Machines ................. 3–33B to 3–35B

(ASM) Charts
Part-9 : Designing Synchronous Circuits ......... 3–36B to 3–38B

Like Pulse Train Generator
Part-10 : Pseudo Random Binary Sequence ...... 3–38B to 3–39B

Generator, Clock Generation
3–2 B (EC-Sem-3) Sequential Logic Design
PART-1
Building Block Like S-R Flip Flop.
Questions-Answers
Que 3.1. What do you mean by flip flop ? Explain SR flip-flop.
Answer
Flip-flops :
Flip-flops are binary cells capable of storing one bit of information. A
flip-flop circuit has two outputs, one for the normal value and one for
the complement value of the bit stored in it.
SR flip-flop :
1. The circuit diagram and truth table of SR flip-flop are shown in
fig. 3.1.1. This is also known as clocked set-reset flip-flop.
2. The circuit functions when clock pulse is active, i.e., 1 otherwise it will
hold its output values (Q and Q ).
Input Output
S S R Qn Qn + 1
Q
0 0 × Q (Hold)
CLK 0 1 0 1 (Reset)
1 0 1 0 (Set)
Q 1 1 × × (Invalid)
R
Fig. 3.1.1. SR Flip-flop.
3. It can be observed from the truth-table that if S = R = 0 and CLK is active
then the output is same as previous.
4. If S = 0 and R = 1, the flip-flop will be in reset stage, i.e., output Q will be
0.
5. If S = 1 and R = 0, the flip-flop will be in set stage, i.e., output Q will be 1.
6. If S = 1 and R = 1 then output is invalid i.e., Q and Q both will attain
logic 1 which contradicts the assumption of complementary outputs.
Que 3.2. Write the difference between latches and flip-flops.

Answer
S. No. Latch Flip-flop

1. Storage element that Storage elements that are
operate with signal levels. controlled by clock transitions.
2. It is level triggered. It is edge triggered.
3. There is no clock pulse. There is a clock pulse.
4. Circuit diagram : Circuit diagram :
Latch Flip-Flop
A Q A
Q
CLK
Q
B Q B
PART-2
JK and Master-Slave JK FF.
Questions-Answers
Que 3.3. Discuss JK flip-flop with its circuit diagram.
Answer
1. The circuit diagram and truth table of JK flip-flop is shown in
Fig. 3.3.1.
J K Qn Q(n+ 1)
0 0 0 0 No change
0 0 1 1 i.e., Qn
J Q 0 1 0 0
Reset
0 1 1 0
CLK
1 0 0 1
Set
K Q 1 0 1 1
1 1 0 1
1 1 1 0 Toggle
Fig. 3.3.1. JK flip-flop.

2. The previous problem that S = R = 1 is invalid in SR flip-flop has been

overcome by JK flip-flop.
3. The working of JK flip-flop is similar to SR flip-flop except that when
J = K = 1, the output exists, i.e., when J = K = 1, the output is 1 when its
previous output is 0 and 0 if its previous output is 1.
4. The condition J = K = 1 causes a major problem, i.e., race-around
condition. Consider J = K = 1 and Q = 0 and a pulse is applied at CLK
input.
5. After a time interval t equal to propagation delay through two NAND
gates in series. The output will oscillate between 0 and 1.
6. At the end of CLK the output is uncertain and the condition is
race-around condition. There are two methods to avoid race-around
condition by using :
a. Master Slave JK flip-flop.
b. Edge-triggered flip-flop.
Que 3.4. Write a short note on master-slave JK flip-flop.
Answer
1. Master-slave combination can be constructed for any type of flip-flop by
adding a gated SR flip-flop. Fig. 3.4.1 explains the master-slave operation
of JK flip-flop.
Master Slave
JQ(t)
Set (J) SM Q M SS QS Q
Clock JK SR
pulse
(Cp) Flip-flop Flip-flop
KQ(t) QM QS Q
Reset (K) RM RS
Fig. 3.4.1. Master-slave JK flip-flip.

2. It requires two flip-flops where one is gated JK acts as master and other
SR flip-flop acts as slave. Output of slave flip-flop is fed as input to AND
gate of master flip-flop which acts as JK flip-flop.
3. Information present at JK flip-flop is transmitted to output of master
flip-flop on positive level clock and is held there until negative level clock
pulse appears.
4. The truth table 3.4.1 follows negative level triggering. This cascading
avoids race around condition when J and K inputs are having logic-1
information.
Table 3.4.1. Characteristics of master and slave JK flip-flop.
Input Outputs Remarks

J (Set) K (Reset) CP Q (t + 1)
0 0 Q (t ) Previous state
0 1 0 Set
1 0 1 Clear (Reset)
1 1 Q (t ) Toggle state
5. Let both inputs J and K are 1. Previous outputs of master and slave
flip-flops are QM = 0 and QS = 0, respectively.
6. During high level clock pulse, information is transmitted to master
flip-flop because Cp  1 for master and slave flip-flop holds previous
output because Cp  0. So output of master flip-flop are QM  1 and
QM  0 and outputs of slave flip-flop are QS  0 and QS  1 .
7. During low level clock pulse, information is transmitted to slave flip-flop
because Cp  1 for slave and master flip-flop holds previous output
because Cp  0. So outputs of master flip-flop are QM  1 and QM  0
and outputs of slave flip-flop are QS  1 and QS  0 .

8. During next high level clock pulse, information is transmitted to master
flip-flop because Cp  1 for master and slave flip-flop holds previous
output because C p  0 for slave. Input of master flip-flop is
SM = JCP QS  1.1.0  0 and RM = KCPQS  1.1.1  1 will reset the
master flip-flop.
9. During low level clock pulse, information is transmitted to slave flip-flop
and master flip-flop holds previous output. Slave flip-flop copies master’s
output. Hence, race around situation is avoided.
PART-3
Edge Triggered FF.
Questions-Answers

Que 3.5. Explain edge triggered flip-flop.
Answer
1. Edge triggered flip-flop synchronizes state change with clock pulse.
II S
Q
Clock pulse
(Cp) R Q
III
Data (D) IV
Fig. 3.5.1. D type positive edge triggered flip-flop.

2. Output is transmitted at a specific level of clock pulse otherwise inputs
are locked and flip-flop does not perform operation.
3. The operation is resumed when the clock pulse level return to zero and
high level pulse occurs.
4. Flip-flop shown in Fig. 3.5.1 is positive edge-triggered flip-flop. Flip-flop
can be negative edge-triggered also.
5. Let D be 0 and clock pulse, CP → 0. NAND-II and NAND-III gates give
outputs R  1 and S  1 as one input; C P is 0. Outputs of
NAND-I and NAND-IV gates are 0 and 1, respectively. The output will
not change any state. So, the inputs are locked.
PART-4
State Diagram, State Reduction, Design of Sequential Circuits.
Questions-Answers
Que 3.6. Discuss the concept of state equation, state table and
state diagram in clocked sequential circuit.
Answer
State equations :
1. The behavior of a clocked sequential circuit can be described algebraically
by means of state equations.
2. A state equation (also called a transition equation) specifies the next

state as a function of the present state and inputs a set of state equations
for the circuit :
A(t + 1) = A(t)x(t) + B(t)x(t)
B(t + 1) = A(t) x(t)

3. The present state value of the output can be expressed algebraically
y(t) = [A(t) + B(t)] x(t)

4. By removing the symbol (t) for the present state, we obtain the output
boolean equation :
y = (A + B) x
State table :
1. The time sequence of inputs and flip-flop states can be enumerated in a
state table (sometimes called a transition table). The state table for the
circuit of Fig. 3.6.1 is shown in Table 3.6.1.
2. The Table 3.6.1 consists of four sections labeled present state, input,
next state, and output. The present state section shows the states of
flip-flops A and B at any given time t.
3. The input section gives a value of x for each possible present state. The
next state section shows the states of the flip-flops one clock cycle later,
at time (t + 1).
4. The output section gives the value of y at time t for each present state
and input condition.
5. The next state of flip-flop A must satisfy the state equation
A(t + 1) = Ax + Bx
Table 3.6.1.
Present state Input Next state Output
A B x A B y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0
6. The next state of flip-flop B is derived from the state equation
B(t + 1) = Ax
7. The output column is derived from the output equation

y=Ax +Bx
State diagram :
1. The information available in a state table can be represented graphically
in the form of a state diagram.
2. In this type of diagram, a state is represented by a circle, and the
(clock-triggered) transitions between states are indicated by directed
lines connecting the circles.
Table 3.6.2.
Present state Next state Output
x=0 x=1 x=0 x=1
A B A B A B y y
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0
0/0 0/1 1/0
00 10
0/1
1/0 0/1 1/0
1/0
01 11
Fig. 3.6.1. State diagram of the circuit.

3. The state diagram provides the same information as the state table and
is obtained directly from Table 3.6.1 or Table 3.6.2.
Que 3.7. Design the clocked sequential circuit for the following
state diagram using JK flip-flop.
0
1 00 1
1 01 11 0
0 10 1
0
Fig. 3.7.1.

Answer
The state table for the given state diagram is (Moore model) :
Input Present state Next state Flip-flop inputs
x Q1 Q0 Q1 Q0 J1 K1 J0 K0
0 0 0 0 0 0 × 0 ×
0 0 1 1 0 1 × × 1
0 1 0 1 0 × 0 0 ×
0 1 1 1 1 × 0 × 0
1 0 0 0 1 0 × 1 ×
1 0 1 0 1 0 × × 0
1 1 0 1 1 × 0 1 ×
1 1 1 0 0 × 1 × 1
Columns of J1, K1, J0, K0 are filled by the help of excitation table of JK
flip-flop.
Excitation table of JK flip-flop :
Present state Next state J K
0 0 0 ×
0 1 1 ×
1 0 × 1
1 1 × 0
K-maps for J0, K0, J1 and K1 are :
For J 1 For K1
Q1Q0 Q1Q0
x 00 01 11 10 x 00 01 11 10
0 1 × × 0 × ×
0 1 3 2 0 1 3 2
1 × × 1 × × 1
4 5 7 6 4 5 7 6
J1 = x Q 0 K1 = x Q0
Q1Q0 For J 0 Q1Q0 For K0

x 00 01 11 10 x 00 01 11 10
0 × × 0 × 1 ×
0 1 3 2 0 1 3 2
1 × × 1 × 1 ×
1 1
4 5 7 6 4 5 7 6
J0 = x Fig. 3.7.2. K0 = x Q1 + x Q1
The boolean expressions for J1, K1, J0 and K0 are :

K0 = xQ1 + xQ1 = x  Q1 = x  Q1
J0 = x
K1 = xQ0
J1 = xQ0
J1 Q1 J0 Q0
CLK
K1 Q1 K0 Q0
Fig. 3.7.3.
Que 3.8. Derive the state table and state diagram for the
sequential circuit shown in Fig. 3.8.1.
A x
JA QA JB QB B
A B
A
x KA QA KB QB B
x
CLK
y
B
Fig. 3.8.1.
Answer
1. Type of circuit :
The output y of the sequential circuit depends on present state only, so
the given logic circuit is the Moore type circuit.
2. Excitation equations :
For flip-flop A : JA = B
KA = Bx
For flip-flop B : JB = x
KB = A  x
For output y : y = AB

3. We know that characteristics equation of JK flip-flop :
An+1 = JQn  KQn
4. State equation for flip-flop A :
An+1 = BA  ( Bx ) A (  Qn = A)
= BA  A( B  x)
= BA  AB  xA
An+1 = (A  B) + xA
5. State equation for flip-flop B :
Bn+1 = xB  ( A  x) B (  Qn = B)
= xB  ( Ax  Ax ) B
Bn+1 = xB  AxB  AxB
State table :
x=0 x=1 y
AB AB AB
00 01 00 0
01 11 10 1
10 11 10 1
11 00 11 0
State diagram :
1
00 State
0 Output
0
0
11 0 01
1 0 1
0 1
10
1
1
Fig. 3.8.2.
Que 3.9. What do you understand by state reduction ? Reduce

the state diagram shown in Fig. 3.9.1.
0/0
a
0/0
1/0
0/0 0/0
0/0
b c
1/0
1/0
g d e
0/0
1/1
1/1
0/0 1/1
f
1/1
Fig. 3.9.1.

OR
Draw the reduced state table and reduced state diagram for the
state table given in Fig. 3.9.1. AKTU 2018-19, Marks 07
Answer
State reduction :
1. Any logic design process must consider the problem of minimizing the
cost of the final circuit. One way to reduce the cost is, by reducing the
number of flip-flops, i.e., by reducing the number of states.
2. The state reduction technique basically avoids the introduction of
redundant equivalent states. The reduction of redundant states reduces
the number of flip-flops and logic gates required, thus reducing the
cost of the final circuit.
3. Two states are said to be redundant or equivalent, if every possible set
of inputs generate exactly the same outputs and the same next states.
4. When two states are equivalent one of them can be removed without
altering input-output relationship.
Numerical :
1. The given Fig. 3.9.1 has seven states, one input and one output. The
given state diagram is converted to state table.
2. From the state table, it is clear that states e and g are equivalent. So the
state g is replaced by state e.
State table :

x=0 x=1 x= 0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
Both are equivalent
e a f 0 1 states because of
f g f 0 1 state e and g having
same next state and
g a f 0 1 same output.
Reducing the state table :

x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
Both are
equivalent e a f 0 1
states e
f f 0 1
3. From the reduced table, states d and f are equivalent, hence f can be
replaced by d and it can be removed.
Reduced table :
Present State Next state Output

x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e d 0 1
e a d 0 1
4. The state diagram of the reduced state table is shown in Fig. 3.9.2.
0/0
0/0
e a
1/0
0/0 1/1
0/0
1/0
d b
1/0 c 0/0
1/1
Fig. 3.9.2. State diagram.
Que 3.10. Derive the state table and state diagram for the
sequential circuit is shown in Fig. 3.10.1.
A
x
DA QA A
B A A
QA A B Y
x
A DB
x QB B
B
QB B
Cp
Fig. 3.10.1.
Answer
1. The behaviour of circuit is determined by the following Boolean
expression,
Y = AB  x ...(3.10.1)
DA = Ax + Bx ...(3.10.2)
DB = Ax ...(3.10.3)
2. From eq. (3.10.1), (3.10.2) and (3.10.3) then state table will be
Table 3.10.1.

A B x=0 x=1 x=0 x=1
0 0 0 0 0 1 1 0
0 1 0 0 1 1 1 0
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 1
3. We draw state diagram with the help of state table

1/0 0/1
00
0/1 0/1
01 0/1 11
1/0 1/1
10
1/0
Fig. 3.10.2.
Que 3.11. Derive the state table and state diagram of the
synchronous sequential circuit shown below (X is an input to the
circuit). Explain the circuit function. AKTU 2017-18, Marks 07
B
A
A D Q
X CLK Q
B B
D Q
CLK Q
A CLK
Fig. 3.11.1.
Answer
1. From the circuit shown in Fig. 3.11.1, the output equation can be
obtained as,
A(t + 1) = ( BX  BX )  A
B(t + 1) = ( AX  AX )  B
2. The state table for the circuit shown in Fig. 3.11.1.
Present state Input Next state
A B X A(t + 1) B(t + 1)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 0
1 0 0 1 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
3. State diagram :
0
0 00
1 1
1 0
11 01
1
0
10
Fig. 3.11.2.
PART-5
Ripple and Synchronous Counters.
Questions-Answers
Que 3.12. Design a 3-bit up/down ripple counter.
Answer
1. The 3-bit up/down ripple counter, which can count in upward direction
of sequence from 000, 001, 010, 011, 100, 101, 110, 111 and downward
direction of sequence from 111, 110, 101, 100, 011, 010, 001, 000.
2. 3-bit counter consists of 3 flip-flops. In ripple counter, a flip-flop output
transition serves as a source for triggering other flip-flops.
3. The control signal M is used to select the direction of count sequence.
Fig. 3.12.1 shows the 3-bit ripple.
M = 1; counter acts as up-counter
M = 0; counter acts as down counter
M Logic 1
Logic 1 Logic 1
JA QA JB Q B JC Q C Q
CLK A B C
KA QA KB QB KC QC Q
Fig. 3.12.1. 3-bit ripple up-down.

Que 3.13. Draw the logic diagram of a 4-bit binary counter with
parallel load.
Answer
1. The operation of the counter is summarized in Table 3.13.1. The four
control inputs–Clear, CLK, load, and count, determine the next state.
2. The clear input is asynchronous and when equal to 0, causes the counter
to be cleared regardless of the presence of clock pulses or other inputs.
Table 3.13.1.
Clear CLK Load Count Function
0 × × × Clear to 0
1 1 1 × Load inputs
1 1 0 1 Count next binary state
1 1 0 0 No change
3. The logic diagram for 4-bit binary counter with parallel load is shown in
Fig. 3.13.1.
Count
Load
I0 J A0
I1 A1
J
I2 J A2
I3 J A3
Clear
CLK
Cout
Fig. 3.13.1.
Que 3.14. Draw diagram of a 4-bit binary ripple down counter

using flip-flops that trigger on negative edge transition. Also draw
a timing diagram of the counter.
OR
Design a ripple decade counter using JK flip-flop.
AKTU 2018-19, Marks 3.5
Answer
4-bit binary ripple down counter :
1. The 4-bit asynchronous counter is constructed by using JK flip-flop
(asynchronous counter are also called ripple counter).
2. The output QA must be externally connected to clock input of flip-flop B.
3. The input count pulses are applied to clock input of flip-flop A.
Simultaneous divisions of 2, 4, 8, and 16 are performed at the QA, QB,
QC, QD outputs.
Timing diagram :
CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
QA
QB
QC
QD
Fig. 3.14.1.
Logic diagram :
M
M
High
JA QA JB QB JC QC JD QD
CLK A B C D
KA QA KB QB KC QC KD QD
Fig. 3.14.2.
4-bit ripple counter needs 4 flip-flop. To work in down mode M should

be high.
Que 3.15. Design a synchronous counter using JK flip-flop for the

following input sequences :
A B C 0
0 0 0 1
0 0 1 6
0 1 0
1 0 0 2
5
1 0 1 4
1 1 0
3
0 0 0
Fig. 3.15.1.
Answer
Present Next Flip-Flop inputs

state state
QA QB QC QA+1 QB+1 QC+1 JA KA JB KB JC KC
0 0 0 0 0 1 0 × 0 × 1 ×
0 0 1 0 1 0 0 × 1 × × 1
0 1 0 1 0 0 1 × × 1 0 ×
0 1 1 1 0 0 1 × × 1 × 1
1 0 0 1 0 1 × 0 0 × 1 ×
1 0 1 1 1 0 × 0 1 × × 1
1 1 0 0 0 0 × 1 × 1 0 ×
1 1 1 × × × × × × × × ×
K-maps :
For J A For KA
QBQC QBQC
Q 00 01 11 10 QA 00 01 11 10
A
0 1 1 0 × × × ×
0 1 3 2 0 1 3 2
1 × × × × 1 × 1
4 5 7 6 4 5 7 6
JA = Q B KA = QB
QBQC For J B QBQC For K B

QA 00 01 11 10 QA 00 01 11 10
0 1 × × 0 × × 1 1
0 1 3 2 0 1 3 2
1 1 × × 1 × × × 1
4 5 7 6 4 5 7 6
JB = Q C KB = 1
QBQC For J C QBQC For K C
QA 00 01 11 10 QA 00 01 11 10
1 × × × 1 1 ×
0 0
0 1 3 2 0 1 3 2
1 × × 1 × ×
1 × 1
4 5 7 6 4 5 7 6
JC = Q B KC = 1
Flip-flop required are : 2n > N

Here N = 6
So, n = 3, i.e., three flip-flops are required.
JA QA JB QB JC QC
KA QA 1 KB QB 1 KC QC
CLK
Fig. 3.15.2. Synchronous counter using JK flip-flop.
Que 3.16. Design a 3-bit asynchronous up-down counter using
T flip-flop. AKTU 2015-16, Marks 7.5
Answer
1. The number of flip-flop to be used is three. We shall use three toggle
flip-flop. Let, up counting takes place with M = 0 and down counting
take place for M = 1.
2. First, we write the circuit excitation table.
Table 3.16.1 : Excitation table for a 3-bit up/down synchronous counter

Mode Present state Next state Flip-flop inputs
control M QC QB QA QC+1 QB+1 QA+1 TC TB TA
0 0 0 0 0 0 1 0 0 1
0 0 0 1 0 1 0 0 1 1
0 0 1 0 0 1 1 0 0 1
0 0 1 1 1 0 0 1 1 1
0 1 0 0 1 0 1 0 0 1
0 1 0 1 1 1 0 0 1 1
0 1 1 0 1 1 1 0 0 1
0 1 1 1 0 0 0 1 1 1
1 0 0 0 1 1 1 1 1 1
1 0 0 1 0 0 0 0 0 1
1 0 1 0 0 0 1 0 1 1
1 0 1 1 0 1 0 0 0 1
1 1 0 0 0 1 1 1 1 1
1 1 0 1 1 0 0 0 0 1
1 1 1 0 1 0 1 0 1 1
1 1 1 1 1 1 0 0 0 1
For TC For T B
QBQA QBQA
MQC 00 01 11 10 MQ C 00 01 11 10
00 0 0 1 0 00 0 1 1 0
0 1 3 2 0 1 3 2
01 0 4 0 5 1 7 0 6 01 0 4 1 5 1 7 0 6
11 1 12 0 13 0 15 0 14 11 1 12 0 13 0 15 1 14
10 1 8 0 9 0 11 0 10 10 1 8
0
9
0
11
1 10
TC = MQB QA + MQB QA TB = MQA + QAM

= M Q A
QBQA For TA
MQ C 00 01 11 10
00 1 1 1 1
0 1 3 2
01 1 4
1 5
1 7
1
6
11 1 1 1 1
12 13 15 14
10 1 8 1 9 1 11 1 10
TA = 1
4. Finally, let us draw the logic diagram.

Mode
control M = 0 for up counting
(M) M = 1 for down counting
Logic 1 MQAQB
MQA
TA Q A T B QB TC Q C
A B C
QA QB QC
MQA
MQAQB
CLK
Fig. 3.16.1. Logic diagram of a 3-bit synchronous up/down counter.
Que 3.17. Design a 3-bit synchronous counter using JK flip-flops.
Answer
3-bit synchronous counter :
For a 3-bit synchronous counter using JK flip-flop, we need 3 flip-flops.
Excitation table and state diagram of JK flip-flop :
Present Next Flip-flop
state state inputs
0
Qn Qn + 1 J K 7 1
0 0 0 ×
6 2
0 1 1 ×
1 0 × 1
5 3
1 1 × 0 4
Excitation table of JK flip-flop State diagram.
Fig. 3.17.1.
Excitation table for 3-bit synchronous counter :
Table 3.17.1 : Circuit excitation table
Present state Next state Flip-flop inputs
QC QB QA QC+1 QB+1 QA+1 JC KC JB KB JA KA
0 0 0 0 0 1 0 × 0 × 1 ×
0 0 1 0 1 0 0 × 1 × × 1
0 1 0 0 1 1 0 × × 0 1 ×
0 1 1 1 0 0 1 × × 1 × 1
1 0 0 1 0 1 × 0 0 × 1 ×
1 0 1 1 1 0 × 0 1 × × 1
1 1 0 1 1 1 × 0 × 0 1 ×
1 1 1 0 0 0 × 1 × 1 × 1
K-maps and simplified expressions for all flip-flop inputs :

QBQA For JC QBQA For K C
QC 00 01 11 10 QC 00 01 11 10
0 0 1 0 0 × × × ×
0 1 3 2 0 1 3 2
1 × × × × 1 0 × 1 0
4 5 7 6 4 5 7 6
JC = Q B QA KC = QB QA
QBQA For JB QBQA For K B

QC 00 01 11 10 QC 00 01 11 10
0 0 1 × × 0 × × 1 0
0 1 3 2 0 1 3 2
1 1 × × 1 × × 1 0
4 5 7 6 4 5 7 6
JB = Q A KB = QA
QBQA For JA QBQA For K A

QC 00 01 11 10 QC 00 01 11 10
0 1 × × 1 0 × 1 1 ×
0 1 3 2 0 1 3 2
1 1 × × 16 1 × 1 1 ×6
4 5 7 4 5 7
JA = 1 KA = 1
Thus the simplified equations are :
JC = QBQA KC = Q B Q A
JB = QA KB = Q A
JA = 1 KA = 1
Logic diagram :
Fig. 3.17.2 shows the logic diagram of a 3-bit synchronous counter using
JK flip-flops.
QA
Logic 1 J C = KC = Q AQ B
QB
JB = KB = Q A
JA = KA = 1 JA QA JB QB JC QC
FF-A FF-B FF-C

KA QA KB QB KC QC
CLK
Fig. 3.17.2. 3-bit synchronous counter using JK FFs.
Que 3.18. Describe the operation of four bit synchronous binary
counter with neat sketch. AKTU 2016-17, Marks 10
Answer
1. The C inputs of all flip-flops are connected to a common clock. The
counter is enabled by count enable.
2. If the enable input is 0, all J and K inputs are equal to 0 and the clock
does not change the state of the counter.
3. The first stage A0 has its J and K equal to 1 if the counter is enabled.
The other J and K inputs are equal to 1 if all previous least significant
stages are equal to 1 and the count is enabled.
4. The chain of AND gates generates the required logic for the J and K
inputs in each stage.
5. The counter can be extended to any number of stages, with each stage
having an additional flip-flop and an AND gate that gives an output of
1 if all previous flip-flop outputs are 1.
J A0
C
Count enable K
J A1
C
K
J A2
C
K
J A3
C
K
To next stage
CLK
Fig. 3.18.1. Four-bit synchronous binary counter.
PART-6
Shift Registers.
Questions-Answers
Que 3.19. Write down the classification of shift registers.

OR
What do you mean by shift register ? What is the need of shift
register ? Draw and explain bidirectional shift register.
Answer
Shift registers :
The binary data in a register can be moved within the register from one
flip-flop to the other or outside it with application of clock pulses. The
registers that allow such data transfers are called shift registers.
Need of a register : A register is a sequential logic circuit with two basic
functions :
i. Temporary storage.
ii. Shifting capability.
Classification of shift registers :
1. Classification based on the direction of data movement :
i. Shift left register.
ii. Shift right register.
iii. Bidirectional shift registers.
2. Classification based on the mode of input and output :
i. Serial in serial out shift register (SISO)
ii. Serial in parallel out shift register (SIPO)
iii. Parallel in serial out shift register (PISO)
iv. Parallel in parallel out shift register (PIPO)
v. Universal shift register.
Bidirectional shift register :
1. It consists of four D flip-flops, four OR gates, eight AND gates and one
NOT gate as shown in Fig. 3.19.1.
M
DR DL
A3 B3 A2 B2 A1 B1 A0 B0
D3 Q3 D2 Q2 D1 Q1 D0 Q0
CLK
Fig. 3.19.1.
Operation :
1. When mode control M = 1, all the A AND gates (A3, A2, A1, A0) are
enabled and the data at DR is shifted to the right when clock pulses are
applied.
2. When M = 0, all A gates are disabled and all B gates are enabled. These
enabled B gates allow data DL to be shifted to left.
3. M should be changed only when CLK = 0, otherwise the data stored in
the register may be changed.
Que 3.20. Write a short note on different types of shift register.

OR
Draw and explain the PISO, PIPO register.
Answer
Serial in serial out shift register (SISO) :
1. The serial in serial out shift register accepts the data serially on a single
input line.
2. It also produces the stored information on its output in serial form. We
can shift the data from left side or right side.
3. Based on the shifting of data, the register is called shift left or shift right
register. Fig. 3.20.1 shows the block diagram of serial in serial out shift
register (SISO).
Serial Serial Serial Serial
in out out in
(a) Shift right (b) Shift left
Fig. 3.20.1. 4-bit serial in serial out shift register.
Shift right register :

1. In this register while accepting data serially, the group of bits is shifted
towards the right side.
2. Hence the serial data is entered onto the left side of register and it
leaves from the right side serially. Fig. 3.20.2 shows the logic circuit for
a 4-bit shift right register.
D3 Q3 D2 Q2 D1 Q1 D0 Q0
Din Dout
D C B A
CLK
Fig. 3.20.2. Logic circuit for a 4-bit shift right register.
Shift left register :
1. The group of bits is shifted towards the left side in serial form. Hence the
serial data is entered from right and the binary data at the output is
taken from the left most flip-flop.
2. Fig. 3.20.3 shows the logic circuit for a 4-bit shift left register.
FF 4 FF 3 FF2 FF1
Q3 D3 Q2 D2 Q1 D1 Q0 D0
Dout Din
D C B A
CLK
Fig. 3.20.3. Logic circuit for a 4-bit shift left register.
3. The binary data is entered into right most flip-flop (FF1) and output is
taken from the left most flip-flop (FF4) in serial form.
Serial in parallel out shift register :
1. This is one type of shift register in which the data is entered in serial
form and output is in parallel form.
2. Hence, it is necessary to have all the data bits available as outputs at the
same time.
3. This type of shift register operation is same as the serial in serial out
shift register.
4. The difference between serial out and parallel out shift registers is the
way in which the data bits are taken out of the register.
5. Fig. 3.20.4 shows the block diagram of 4-bit serial in parallel out shift
register.
Parallel out
Serial in
Fig. 3.20.4. Block diagram of 4-bit serial in parallel out shift register.
5. Fig. 3.20.5 shows the logic circuit for 4-bit serial-in parallel out shift
register.
Q3 Q2 Q1 Q0
D3 Q3 D2 Q2 D1 Q1 D0 Q0
Din Dout
D C B A
CLK
Fig. 3.20.5. Logic circuit for 4-bit serial in parallel out shift register.
Parallel in serial out shift register :
1. Fig. 3.20.6 shows the block diagram of a parallel in serial out shift register.
In this type, the bits are entered in parallel, i.e., simultaneously into
their respective stages on a parallel line.
2. It produces the stored information on its output, in serial form.
Parallel in
Serial out
Fig. 3.20.6. Parallel in serial out shift register.

Parallel in parallel out shift register :
1. All the data appear simultaneously along with all the flip-flop inputs and
outputs.
2. Fig. 3.20.7 shows the logic diagram for 4-bit parallel in parallel out shift
register.
Parallel outputs
Q3 Q2 Q1 Q0
D3 Q3 D2 Q2 D1 Q1 D0 Q0
D C B A
CLK
D C B A
Parallel inputs
Fig. 3.20.7. Logic diagram for 4-bit parallel in parallel out shift register.
Que 3.21. With the help of diagram, explain the operation of
universal shift register. AKTU 2014-15, Marks 06

OR
Draw and explain 4-bit universal shift register.
OR
Design a universal shift register that performs HOLD, SHIFT RIGHT,
SHIFT LEFT, and LOAD. AKTU 2017-18, Marks 07
Answer
1. A shift register that can shift the data in both the directions (shift right
or left) as well as load it parallely, it is called as a universal shift register.
2. This shift register is capable of performing the following operations :
i. Parallel loading (parallel input parallel output).
ii. Left shifting. iii. Right shifting.
3. The block diagram of a 4-bit universal shift register is shown in
Fig. 3.21.1. It consists of four D flip-flop and four 4 : 1 multiplexers.
4. The four multiplexers have two common select lines S1 and S0. Input I0
in each multiplexer is selected when S1S0 = 00, input I1 is selected
when S1S0 = 01 and so on.
5. The selection inputs (S1S0) control the mode of operation of the register
according to the function table shown in table 3.21.1.
Parallel output
A3 A2 A1 A0
FF 4 Q FF3 Q FF 2 Q FF 1 Q
Clear
D D D D
CLK
S1 4×1 MUX 4×1 MUX 4×1 MUX 4×1 MUX

S0 I3 I2 I1 I0 I3 I2 I1 I0 I3 I2 I1 I0 I3 I2 I1 I0
Serial
input
Serial
for shift
I3 I2 I1 I0 input
right
for shift
Parallel inputs left
Fig. 3.21.1. Block diagram of 4-bit universal shift register.
Table 3.21.1. Function table
S1 S0 Function
0 0 Hold
0 1 Shift right
1 0 Shift left
1 1 Load
Operation :
1. When S1S0 = 00, the present value of the register is applied to the D
inputs of the flip-flops. This condition forms a path from the output of
each flip-flop to the binary value input of the same flip-flop.
2. The next clock edge transfers into each flip-flop the binary value it
held previously and no change of state occurs.
3. When S1S0 = 01, the input I1 of the multiplexer has a path to the D
inputs of the flip-flops. This causes a shift right operation, with the
serial input transferred in flip-flop FF4.
4. When S1S0 = 10, a shift left operation results, with the other serial
input going into flip-flop FF1. In this case, Input I2 of each multiplexer
is connected to the output of each flip-flop. The data bit is shifted to left
side for every clock.
5. When S1S0 = 11, the binary information on the parallel input lines is
transferred into the register simultaneously during the next clock edge.
Que 3.22. What are the applications of shift register ?
Answer
i. Time delay : The serial out shift register can be used to provide a time
delay from input to output that is a function of both the number of
stages (n) in the register and the clock frequency.
ii. Serial to parallel data converter : Serial data transmission from one
digital system to another is commonly used to reduce the number of
wires in the transmission line. We can convert the received serial data
to parallel data by using serial in parallel out shift register.
iii. Parallel to serial data converter : Serial data transmission requires
a stream of serial data to be transferred from one digital system to
another. We can convert the parallel data to serial data by using parallel
in serial out shift register.
Que 3.23. Design a 4-bit serial in serial out shift register using JK
flip-flop.
Answer
Serial in-serial out shift register using JK flip-flop :
Serial J3 Q3 J2 Q2 J1 Q1 J0 Q0
in (D) Serial
out
K3 Q3 K2 Q2 K1 Q1 K0 Q0
CLK
Fig. 3.23.1.
Conversion table and K-map :

For J For K
Qn Qn Qn Qn Qn Qn
D Qn Qn + 1 J K D D
0 0 0 0 × D × D × 1
0 1 0 × 1 0 1 0 1
1 0 1 1 × D 1 × D ×
1 1 1 × 0 2 3 2 3
J=D K=D
PART-7
Finite State Machines (FSM), Design of Synchronous FSM.
Questions-Answers
Que 3.24. Explain Moore type of synchronous sequential machine

(FSM) using block diagram and suitable example.
Answer
1. When the output of the sequential network depends only on the present
state of the flip-flop, the sequential network is referred to as Moore
model.
2. Fig. 3.24.1 shows a sequential network which consists of two JK flip-flop
and AND gates.
X
X JA QA JB QB
CP A B
1 KA QA KB QB
Y
Fig. 3.24.1. Example of Moore model.
3. The network has one input X and one output Y.

4. As shown in the Fig. 3.24.2, input is used to determine the inputs of the
flip-flops.
5. It is not used to determine the output.
6. The output is derived using only present states of the flip-flops or
combination of it (in this case QA QB ).
7. In general form the Moore model can be represented with its block
schematic as shown in Fig. 3.24.2 (a) and (b).
8. In the Moore model, as output depends only on present state of the
flip-flops, it appears only after the clock pulse is applied, i.e., it varies in
synchronism with the clock input.
Inputs Next Memory

Outputs
state elements
decoder
(a) Moore model.
Next Output
Inputs Memory
state decoder Outputs
elements (combinational
decoder
circuit)
(b) Moore circuit model with an output decoder.

Fig. 3.24.2.
Que 3.25. Explain Mealy model.
Answer
1. When the output of the sequential network depends on both the present
state of flip-flop(s) and on the input(s), the sequential circuit is referred
to as Mealy model.
2. Fig. 3.25.1 shows the sample Mealy model.
X
X JA QA JB QB
CP A B
1 KA QA KB QB
Y
Fig. 3.25.1. Example of Mealy model.
3. As shown in the Fig. 3.25.1, the output of the circuit is derived from the
combination of present state of flip-flops and input(X) of the circuit.
4. Looking at Fig. 3.25.1, we can easily realize that, changes in the input
within the clock pulses cannot affect the state of the flip-flop. However,
they can affect the output of the circuit.
5. If the input variations are not synchronized with the clock, the derived
output will also not be synchronized with the clock and we get false
output (as it is synchronous sequential network).
6. The false outputs can be eliminated by allowing input to change only at
the active transition of the clock (in our example HIGH-to-LOW).
7. In general form the Mealy model can be represented with its block
schematic as shown in Fig. 3.25.2.
Output
Outputs
Inputs Next decoder
state Memory
decoder elements
Fig. 3.25.2. Mealy circuit model.
PART-8
Algorithmic State Machines (ASM) Charts.
Questions-Answers
Que 3.26. What is ASM chart ? Explain. Draw the state diagram,
state table and ASM chart for a D flip-flop.
Answer
ASM chart is composed of three basic elements : State box, decision box
and conditional box.
State box : The state of the system is indicated by a state box. The shape
of the state box is a rectangle.
General description entry
State name Binary code
Register operation or
unconditional list
Exit
Fig. 3.26.1.
Decision box : It is a diamond shaped box used to describe the effect of
an input on the control subsystem.
Entry
0 I/P 1
condition
Exit path 1 Exit path 2

Fig. 3.26.2.
Conditional box : It is a unique box of ASM chart. The area shape of
the conditional box is shown in Fig. 3.26.3. The round corners
differentiate it from the state box.
Entry path from decision box
Conditional register
operation / output
Exit
Fig. 3.26.3.
To draw ASM chart, first we form a state table for easy understanding of
the operation of the given circuit.
Z
DA QA DB QB
X
QA QB
CLK
Fig. 3.26.4.
State table :
Present Next state, output

state X=0 X=1
QA QB QA+1 QB+1 Z QA+1 QB+1 Z
0 0 0 1 1 1 1 1
0 1 0 1 1 1 1 1
1 0 0 0 0 1 0 1
1 1 1 0 0 0 0 1
State diagram :
00
1/1 0/1
1/1
0/0
11 01 0/1
1/1
0/0
10 1/1
Fig. 3.26.5.
ASM chart :
S0 00
Z=1
0 1
S1 X
Z=1
S3 11
Z=1 Z=1
1 1
X X
Z=1
10 Z=0
S2
Z=1
Z=1
1 0
X
Fig. 3.26.6.
PART-9
Designing Synchronous Circuits Like Pulse Train Generator.
Questions-Answers
Que 3.27. Generate the following pulse train using indirect logic.
1 0 1 1 0 1 0 1 1 0 1
Answer
1. The given sequence is 10110. It is written vertically under the column
heading output (f) in the truth table of Fig. 3.27.1(a).
2. It is 5 bits long, so we need five unique states to generate pulse train so,
any mod-5 counter can be used.
3. For simplicity, we use a ripple counter.
4. It goes through states 0, 1, 2, 3, 4, 0 ... States 5, 6, 7 are invalid, so the
corresponding outputs arc don’t cares.
5. The K-map for the output 1 in terms of the outputs of the flip-flops, its
minimization, and the minimal expression obtained from it are shown in
Fig. 3.27.1.
6. The logic diagram (using a mod 5 ripple counter) based on that minimal
expression for f is shown in Fig. 3.27.2.
7. While at state 0, it output a 1, i.e., the first bit of the sequence.
8. While at state 1, it outputs a 0; i.e., the second bit of the sequence, and so
on.
Q3 Q2 Q1 Output (f) States

0 0 0 1 0
0 0 1 0 1
0 1 0 1
0 1 1 1 3
1 0 0 0 4
1 0 1 x 5
1 1 0 × 6
1 1 1 × 7
(a) Truth table.
Q2Q1
Q3 00 01 11 10
0 1 3 2
0 1 1 1
4 5 7 6
1 × × ×
Output, f = Q2 + Q3 Q1
(b) K-map
Fig. 3.27.1. Pulse train generator.
1 J1 Q1 1 J2 Q2 1 J3 Q3
FF 1 FF 2 FF 3
CLK
K1 Q1 K2 Q2 K3 Q3 f
Fig. 3.27.2. Logic diagram of the pulse train generator.
Que 3.28. Design a pulse generator using indirect logic to produce

the following waveforms.
0 1 0 0 1 1 0 0 0
0 1 1 1 1 1 1 0 0
Answer
1. The pulse trains to be generated written vertically under column heading
f1 and f2 in the truth table of Fig. 3.28.1(a) are : (a) 100 11000 and (b)
11111100.
2. These are both eight bits long.
3. So we need eight unique states to generate those two pulse trains.
4. Therefore, a mod-8, i.e., a 3-bit ripple counter can be used.
5. Let f1 and f2 be the outputs of the combinational circuits.
6. The state assignment is shown in the truth table.
7. The K-map for outputs f1 and f2 in terms of the outputs of the flip-flops,
their minimization and the minimal expressions obtained from them
are shown in Fig. 3.28.1(b).
8. The logic diagram (using a mod-8 ripple counter) based on those minimal
expressions for f1 and f2 is shown in Fig. 3.28.2.
States Q3 Q2 Q1 f1 f2 Q2Q1 Q2Q1

Q3 00 01 11 10 Q3 00 01 11 10
0 0 0 0 1 1
1 0 0 1 0 1 0 1 0 1 1 3 2 0 0 1 3 2
2 0 1 0 0 1 1 1 1 1
3 0 1 1 1 1 1 1 4 5 7 6 1 4 5 7 6
4 1 0 0 1 1 1 1
5 1 0 1 0 1 f1 = Q2Q1 + Q3Q2Q1
6 1 1 0 0 0 f2 = Q2+ Q 3
7 1 1 1 0 0
(b)
(a)
Fig. 3.28.1. Truth lable and K-maps for f1 and f 2.
1 J1 Q1 1 J2 Q2 1 J3 Q3
FF1 FF 2 FF 3
CLK
K1 Q1 K2 Q2 K3 Q3 f2
f1
Fig. 3.28.2. Logic diagram of the pulse train generator.
PART-10
Pseudo Random Binary Sequence (PRBS) Generator,
Clock Generation.
Questions-Answers
Que 3.29. Write a short note on PSBR generator.
Answer
1. Another important application of shift register is a Pseudo-Random
Binary Sequence (PSBR) generator. Here, suitable feedback is used to
generate pseudo-random sequence.
2. The term random here means that the outputs do not cycle through a
normal binary count sequence.
3. The term pseudo here refers to the fact that the sequence is not truly
random because it does cycle through all possible combinations once
every 2n – 1 clock cycles, where n represents the number of shift register
stages (number of flip-flops).
Que 3.30. Explain clock generator.
Answer
1. The clock generator is a circuit that produces a timing signal for
synchronization of the circuit’s operation.
2. Examples of clock generators used in microprocessor systems include
8284 and 82284. 8284 generates the system clock for the 8086 and 8088
processors.
3. It requires a crystal or a TTL signal source for producing clock waveforms.
It provides local READY and MULTIBUS READY synchronization.
4. 82284 is a clock generator/driver that provides clock signals for the
80286 processor and support components.
5. It also contains logic to supply READY to the CPU from either
asynchronous or synchronous sources and synchronous RESET from
an asynchronous input with hysteresis.
6. The 82284 is packaged in 18-pin DIP and contains a crystal-controlled
oscillator, an MOS clock generator, a peripheral clock generator, multibus
ready synchronization logic and system reset generation logic.

Q. 1. Design the clocked sequential circuit for the following state

diagram using JK flip-flop.
0
1 00 1
1 01 11 0
0 10 1
0
Fig. 1.
Q. 2. Derive the state table and state diagram for the sequential
circuit is shown in Fig. 2.
A
x
DA QA A
B A A
QA A B Y
x
A DB QB
x B
B
QB B
Cp
Fig. 2.
Q. 3. Draw the reduced state table and reduced state diagram
for the state table given in Fig. 3.
0/0
a
0/0
1/0
0/0 0/0
0/0
b c
1/0
1/0
g d e
0/0
1/1
1/1
0/0 1/1
f
1/1
Fig. 3.
Q. 4. Design a ripple decade counter using JK flip-flop.
Q. 5. Describe the operation of four bit synchronous binary
counter with neat sketch.
Q. 6. Write down the classification of shift registers.
Q. 7. Draw and explain 4-bit universal shift register.

4 Logic Families and

Semiconductor
Memories
CONTENTS
Part-1 : TTL NAND Gate, Specifications .............. 4–2B to 4–3B
Part-2 : Noise Margin ................................................ 4–3B to 4–4B
Part-3 : Propagation Delay ...................................... 4–4B to 4–5B
Part-4 : Fan-in, Fan-out ........................................... 4–5B to 4–6B
Part-5 : Tristate TTL ................................................. 4–6B to 4–9B
Part-6 : ECL .............................................................. 4–9B to 4–11B
Part-7 : CMOS Families and ................................ 4–11B to 4–17B

Their Interfacing
Part-8 : Memory Elements, Concept of ............ 4–18B to 4–20B

Programmable Logic Devices
Like FPGA
Part-9 : Logic Implementation using ................. 4–20B to 4–31B

Programmable Devices
4–2 B (EC-Sem-3) Logic Families & Semiconductor Memories
PART-1
TTL NAND Gate, Specifications.
Questions-Answers
Que 4.1. Describe the construction and operation of TTL NAND

gate.
OR
Draw and explain the operation of a TTL NAND gate.
Answer
1. The circuit of the two-input TTL NAND gate is shown in Fig. 4.1.1. The
input transistor, Q1 is a multiple emitter transistor.
+VCC
RC 130 
RC 4
RB 4 k 2 1.6 k
1
IC
2
Q4
TTL
multiple
emitter
Q1 Q2 DT
A
B Vo
DA DB Q3
RE 1 k
2
Fig. 4.1.1. TTL NAND gates.

2. Transistor Q2 is called the phase splitter. Emitter of transistor, Q4 is
connected to collector of transistor, Q3 through diode DT.
3. Transistors Q3 and Q4 form a totem-pole arrangement. Diodes, DA and
DB protect transistor, Q1 from being damaged by the negative spikes of
voltages at the inputs.
4. When negative spikes appear at the input terminals, the diodes conduct
and bypass the spikes to ground.
5. Diode DT ensures that transistors, Q 3 and Q 4 do not conduct

simultaneously. Transistor, Q3 acts as an emitter follower.
Operation :
1. A LOW voltage at either emitter E1 or emitter E2 forward-biases the
corresponding diode D1 or D2 and reverse-biases diode D3 which is a
base-collector junction of transistor Q1. There is no flow of current from
base to collector of transistor Q1.
2. A LOW voltage on both emitters of transistor Q1 does the same action.
3. A HIGH voltage on both emitters reverse-bias both input diodes D1 and D2 and
forward bias D3. The current flows from base to collector of transistor Q1.
Base, B
Diode, D 1 Diode, D3
Emitter, E1
Collector, C
Diode, D 2
Emitter, E2
Fig. 4.1.2. Diode equivalent of TTL multiple emitters.

Table 4.1.1. Operation of TTL NAND gate
Inputs Transistors Output
A B Q1 Q1 Q2 Q3 Q4 Vo
Emitter junction, A Emitter junction, B

0 0 Forward bias (ON) Forward bias (ON) OFF OFF ON 1
0 1 Forward bias (ON) Reverse bias (OFF) OFF OFF ON 1
1 0 Reverse bias (OFF) Forward bias (ON) OFF OFF ON 1
1 1 Reverse bias (OFF) Reverse bias (OFF) ON ON OFF 0
PART-2
Noise Margin.
Questions-Answers
Que 4.2. What do you understand by noise margin of logic

circuit ? Explain with an example.
Answer
1. The noise immunity of a logic circuit refers to the circuit’s ability to
tolerate noise voltages at its inputs. A quantitative measure of noise
immunity is called noise margin.
2. Noise margin represents the maximum noise signal that can be added to
the input signal of a digital circuit without causing an undesirable change
in the circuit output.
3. Noise margin can be HIGH state noise margin or LOW state noise margin.
HIGH state noise margin (NMH ) is, VNH = VOH – VIH
LOW state noise margin (NML ) is, VNL = VIL – VOL
4. High state noise margin is the difference between the lowest possible
high output and the minimum input voltage required for a HIGH. Low
state noise margin is the difference between the largest possible LOW
output and the maximum input voltage for a LOW.
5. Consider an example of a TTL AND gate. The TTL gate has VOH = 2.4 V,
VOL = 0.4 V, VIH = 2 V and VIL = 0.8 V. The noise introduced in the signal
(VNH or VNL) is shown in Fig. 4.2.1.
VOL = 0.4 V VIL = 0.8 V
Logic 0 VOL = 0.4 V
G1 ± Noise
Logic 0 G2
Logic 0
Fig. 4.2.1.
6. Let the inputs of gate, G1 cause output as logic 0. This output acts as
input for gate, G2. Due to noise, actual input given to gate, G2 is
VNL = VIL – VOL ...(4.2.1)
7. Let the inputs of gate, G1 cause output as logic 1 in Fig. 4.2.2. This output
acts as input for gate, G2. Due to noise, actual input given to gate, G2 is
VNH = VOH – VIH ...(4.2.2)
VOH = 2.4 V VIH = 2.0 V
Logic 1 VOL = 0.4 V
G1 ± Noise
Logic 1 G2
Logic 0
Fig. 4.2.2.
VIH in eq. (4.2.2) that acts as input to gate G2. Minimum high level noise
level is
VNH = 2.4 V – 2.0 V = 0.4 V
PART-3
Propagation Delay.
Questions-Answers
Que 4.3. Write a short note on propagation delay.

Answer
1. Propagation delay is defined as the time interval between changes in a defined
logic level input and reflection of its effect at the output logic level.
2. The propagation delay for an integrated circuit (IC) logic gate may
differ for each of the inputs. If all other factors are held constant, the
average propagation delay in a logic gate IC increases as the complexity
of the internal circuitry increases.
PART-4
Fan-in, Fan-out.
Questions-Answers
Que 4.4. Describe the fan-out and fan-in condition of the digital
logic gate.
Answer
Fan-out :
1. The fan-out of a logic gate is defined as the maximum number of standard
load that the output of the gate can drive without impairing its normal
operation. Fan-out is also called the loading factor.
2. HIGH state fan-out is the fan-out of the gate when its output is logic 1.
LOW state fan-out is the fan-out of the gate when its output is logic 0.
The smaller of these two numbers is taken as the actual fan-out.
3. High state fan-out is given by
I
HIGH state fan-out = OH
I IH
where, IOH is the maximum current that the driver gate can source
when it is in a 1 state. IIH is the current drawn by each driven gate from
the driver gate.
4. Similarly, low state fan-out is given by
I
LOW state fan-out = OL
I IL
where, IOLis the maximum current that the driver gate can sink when
its output is a logic 0. IIL is the current drawn from each driven gate by
the driver gate.
5. The fan-out of a logic family can be calculated as
 IOH IOL 
Fan-out = minimum of  , 
 I IH I IL 
Fan-in :
1. The fan-in of a digital logic gate refers to the number of inputs. For
example, an inverter has a fan-in of 1, a 2-input NOR gate has a fan-in
of 2, a 4-input NAND gate has a fan-in of 4 and so on.
2. A logic designer has to select the fan-in of the gate to accommodate the
number of inputs.
3. At the hardware level, however, the fan-in provides information about
the intrinsic speed of the gate itself.
4. In general, the propagation delay increases with the fan-in. This means
that 2-input NAND gate is faster than the 4-input NAND if both are
from same logic family.
PART-5
Tristate TTL.
Questions-Answers
Que 4.5. Describe the construction and operation of TTL inverter

gate (NOT gate).
Answer
1. Fig. 4.5.1 shows a standard TTL circuit for an inverter. Transistor, Q1 is
the input coupling transistor, and D1 is the input clamp diode. Transistor,
Q2 is called a phase splitter, and the combination of Q3 and Q4 forms the
output circuit often referred to as a totem-pole arrangement.
+VCC
RC 130 
4
RB RC 1.6 
1 4 K 2
Q4
A Q1 Q2
DT
Vo
D1 Q3
RE 1
2
Fig. 4.5.1. TTL inverter gates.

2. When the input is HIGH, the base-emitter junction of transistor, Q1 is

reverse-biased and the base-collector junction is forward-biased.
3. This condition permits current to flow through RB1 and the base-collector
junction of transistor, Q1 into the base of transistor, Q2.
4. It drives transistor, Q2 into saturation. As a result, transistor, Q3 is
turned ON due to ON state of transistor, Q2 and its collector voltage,
which is the output, is near to ground potential.
5. Therefore, a LOW output is produced for a HIGH input. At the same
time, the collector of transistor, Q2 is at a sufficiently LOW voltage level
to keep transistor, Q4 OFF.
6. When the input is LOW, the base-emitter junction of transistor, Q1 is
forward-biased, and the base-collector junction is reverse-biased.
7. The current flows through resistor, RB1 and the base-emitter junction of
transistor, Q1, to the LOW input. A LOW provides a path to ground for
the current.
8. No current flows into the base of transistor, Q2 so it is OFF. The collector
of transistor, Q2 is HIGH, thus turning transistor, Q4 ON. A saturated
transistor, Q4 provides a low-resistance path from VCC to the output.
9. Therefore, a HIGH on the output is produced for a LOW on the input. At
the same time, the emitter of transistor, Q2 is at ground potential, keeping
transistor, Q3 OFF.
Table 4.5.1. Operation of TTL inverter.
A Q1 Q2 Q3 Q4 Vo
Emitter junction, A
Logic 0 Forward bias (ON) OFF OFF ON Logic 1
Logic 1 Reverse bias (OFF) ON ON OFF Logic 0
Que 4.6. Describe the construction and operation of TTL NOR

gate.
Answer
1. The circuit of the two-input TTL NOR gate is shown in Fig. 4.6.1. Two
input transistors QA and QB are emitter transistors.
2. Transistor Q1 and Q2 are called the phase splitters. Emitter of transistor
Q4 is connected to collector of transistor Q3 through diode DT .
3. Transistors Q3 and Q4 form a totem-pole arrangement. Diodes DA and
DB protect transistor QA and QB from being damaged by the negative
spikes of voltages at the inputs.
4. When negative spikes appear at the input terminals, the diodes conduct
and bypass the spikes to ground.
5. Diode D T ensures that transistors Q 3 and Q 4 do not conduct
simultaneously. Transistor Q3 acts as an emitter follower.
+VCC
RC 130 
RB 4 k RC 1.6 k 4
A 1
RBB 4 k
Q4
A QA
Q1
DT
Vo
B QB
Q2 Q3
DA DB
RE12 1 k
Fig. 4.6.1. TTL NOR gate.

Operation :
Table 4.6.1. Operation of TTL NOR gate.
A B QA QB Q1 Q2 Q3 Q4 Vo

0 0 Forward bias (ON) Forward bias (ON) OFF OFF OFF ON 1
0 1 Forward bias (ON) Reverse bias (OFF) OFF ON ON OFF 0
1 0 Reverse bias (OFF) Forward bias (ON) ON OFF ON OFF 0
1 1 Reverse bias (OFF) Reverse bias (OFF) ON ON ON OFF 0
Que 4.7. State various TTL parameters in brief.
Answer
i. Current sinking :
1. A TTL circuit acts as a current sink in LOW state, as it receives current
from the input of the gate by which it is driving.
2. Transistor is the current-sinking transistor or the pull-down transistor,
because it brings the output voltage down to its LOW state.
ii. Current sourcing :
1. A TTL circuit acts as a current source in the HIGH state, as it supplies
current to the gate by which it is driving.
2. Transistor is the current-sourcing transistor or the pull-up transistor,
because it pulls up the output voltage to its HIGH state.
iii. Floating inputs :
i. When a TTL input is HIGH (ideally + 5 V), the emitter current is
approximately zero. When a TTL input is floating no emitter current is
possible because of the open circuit.
ii. Therefore, a floating TTL input is equivalent to a HIGH output. Because

of this, unused TTL inputs are left unconnected : an open input allows
the rest of the gate to function properly.
iv. TTL loading and fan-out :
1. The TTL output has a limit, IOL that gives the maximum current it can
sink in LOW state and a limit, IOH, gives the maximum current it can
source in HIGH state.
2. To determine the fan-out, the drive capabilities of the output, i.e., IOL
and IOH and the current requirements of each input, i.e., IIL and IIH are
known.
3. So, HIGH and LOW state fan-outs are given by :
I
HIGH state fan-out = OH
I IH
IOL
LOW state fan-out =
I IL
4. The actual fan-out capability is equal to the smaller of the above two
fan-out values and is given by
I I 
Actual fan-out capability = minimum  OH , OL 
 IH I IL 
I
v. Unit load :
Unit load means the current drawn or sourced back by similar gates.
Example : For 7400,
One unit load is 40 A in HIGH state that is known as IIH
One unit load is 1.6 mA in LOW state that is known as IIL.
PART-6
ECL.
Questions-Answers
Que 4.8. Explain the basic circuit and operation of emitter coupled
logic (ECL). What are the functions of emitter follower ?
Answer
Basic ECL circuit :
1. The basic circuit for emitter-coupled logic is a differential amplifier
configuration as shown in Fig. 4.8.1.
2. The VEE supply produces a fixed current IE, which remains around 3 mA
during normal operation. This current is allowed to flow through either
transistor Q1 or transistor Q2, depending on the voltage level at VIN.
R1 R2
VC1 VC2
VIN Q1 Q2 VBB
R3 IE
V EE
Fig. 4.8.1.
3. In other words, this current switches between collector of Q1 transistor
and collector of Q2 transistor as VIN switches between its two logic levels
of – 1.7 V (logical 0 for ECL) and – 0.8 V (logical 1 for ECL).
4. Table 4.8.1 shows the resulting output voltages for these two conditions
at VIN.
Table 4.8.1. Operating states of ECL
VIN Outputs Remarks
Voltage level Binary logic VC1 VC2
– 1.7 V Logic 0 0V – 0.9 V Q2 conducts
– 0.8 V Logic 1 – 0.9 V 0V Q1 conducts
5. Two important points are noted :

i. VC1 and VC2 are the complements of each other, and
ii. The output voltage levels are not same as the input logic levels.
6. The emitter followers perform two functions :
i. Emitter followers subtract approximately 0.8 V from VC1 and VC2 to shift
the output levels to the correct ECL logic levels.
ii. Emitter followers provide very low output impedance (typically 7 ),
which provides for large fan-out and fast charging of load capacitance.
Que 4.9. Describe the construction and operation of ECL
OR/NOR gate.
Answer
1. A two-input ECL OR/NOR gate is shown in Fig. 4.9.1.
2. It has two outputs which are complements of each other. Transistors Q2
and Q1 form a differential amplifier. Transistors Q1 and Q3 are in parallel.
3. Transistors Q4 and Q5 are emitter followers whose emitter voltages are
the same as the base voltages (less than 0.8 V base to emitter drops).
RC1 RC2
VC2
Q5
VC1 A+B
Q4
RE5
A Q3 B Q1 Q2 VBB
A+B
RE4 VEE
R3 IE
VEE
VEE
Fig. 4.9.1. ECL NOR and OR gates.
4. Inputs are applied to transistors Q1 and Q3, and transistor Q2 is supplied
with constant – 1.3 V.
Table 4.9.1. Operation of ECL OR/NOR gate.
A B Q3 Q1 Q2 Q4 Q5 A+B A B
0 0 OFF OFF ON ON OFF 0 1

0 1 OFF ON OFF OFF ON 1 0
1 0 ON OFF OFF OFF ON 1 0
1 1 ON ON OFF OFF ON 1 0
PART-7
CMOS Families and their Interfacing.
Questions-Answers
Que 4.10. Describe the circuit and performance of CMOS inverter
and state the characteristics of CMOS. AKTU 2018-19, Marks 3.5
Answer
CMOS inverter :
1. It consists of an NMOS transistor Q1 and a PMOS transistor Q2. The
input is connected to the gates of both the devices and the output is at
the drain of both the devices. The positive supply voltage is connected to
the sources of the PMOS transistor Q2, and the source of transistor Q1
is grounded.
2. When A is LOW (0 V). Gate to source voltage VGS2 of transistor Q2 is
– 5 V, and gate to source voltage VGS1 of transistor Q1 is 0 V. So,
transistor Q2 acts as ON and transistor Q1 acts as OFF. Therefore, the
switching circuit shown in Fig. 4.10.1(b) results in Vo as logic HIGH that
is + 5 V.
+5 V +5 V +5 V
Q 2(ON)
Q2 Q2(OFF)
A=1
A=0 Vo = 5 V Vo = 0 V
A Vo
Q 1(ON)
Q 1(OFF)
Q1
(a) (b ) A = 0 (c ) A = 1
Fig. 4.10.1. (a ) CMOS as inverter, (b) and (c) equivalent circuit.
3. When A is HIGH (+ 5 V), gate to source voltage VGS2 of transistor Q2 is
0 V, and gate to source voltage VGS1 of transistor Q1 is + 5 V. So, transistor
Q2 acts as OFF and transistor Q1 acts as ON. Therefore, the switching
circuit shown in Fig. 5.13.1(c) results with Vo as logic LOW that is 0 V.
Table 4.10.1. Operation of CMOS inverter.
Input, A p-channel n-Channel Output, Vo
MOSFET, Q1 MOSFET, Q2
LOW (0 V) ON OFF + 5 V (HIGH)

HIGH (5 V) OFF ON 0 V (LOW)
Truth table :
A Vo
0 1
1 0
Characteristics of CMOS :
i. Supply voltage : The 4000 and 74C series can operate with VDD values
ranging from 3 to 15 V. The 74HC and 74HCT series can operate with
VDD values ranging from 2 to 6 V.
ii. Voltage levels : When a CMOS output drives only a CMOS input and
CMOS gate has an extremely high input resistance, the current drawn
is almost zero and, therefore, the output voltage levels will be very close
to zero for LOW state and VDD for HIGH state.
iii. Power dissipation : When a CMOS circuit is in a static state, its power
dissipation per gate is extremely small, but it increases with increase in
operating frequency and supply voltage level. For DC, CMOS power
dissipation is only 2.5 nW per gate when VDD = 5 V, and it increases to
10 nW per gate when VDD = 10 V.
iv. Switching speed : The speed of the CMOS gate increases with increase
in VDD. The increase in VDD results in increase in power dissipation too.
Unused inputs : The CMOS inputs should never be left disconnected.
All CMOS inputs have to be tied either to a fixed voltage level
(0 V or VDD) or to another input.
Que 4.11. Discuss the circuit diagram and operation of CMOS

NAND gate.
Answer
1. Fig. 4.11.1 shows a CMOS two-input NAND gate. Here, p-channel
MOSFETs Q1 and Q2 are connected in parallel and n-channel MOSFETs
Q3 and Q4 are connected in series.
2. When A is LOW (0 V) and B is also LOW (0 V). p-channel MOSFET Q1
acts ON, n-channel MOSFET Q3 acts OFF, p-channel MOSFET Q2 acts
ON and n-channel MOSFET Q4 acts OFF. Thus, the switching results
Vo as logic HIGH i.e., +5 V.
3. When A is LOW (0 V) and B is HIGH (5 V). p-channel MOSFET Q1 acts
ON, n-channel MOSFET Q3 acts OFF, p-channel MOSFET Q2 acts
OFF and n-channel MOSFET Q4 acts ON. Thus, the switching circuit
results Vo as logic HIGH i.e., +5 V.
4. When A is HIGH (+ 5 V) and B is LOW (0 V). p-channel MOSFET Q1
acts OFF, n-channel MOSFET Q3 acts ON, p-channel MOSFET Q2 acts
ON and n-channel MOSFET Q4 acts OFF. Thus, the switching circuit
results Vo as logic HIGH i.e., + 5 V.
5. When A is HIGH (+ 5 V) and B is also HIGH (+5 V). p-channel MOSFET
Q1 acts OFF, n-channel MOSFET Q3 acts ON, p-channel MOSFET Q2
acts OFF and n-channel MOSFET Q4 acts ON. Thus, the switching
circuit results Vo as logic LOW i.e., 0 V.
+5 V
Q1 Q2
Vo
Q3
A
Q4
B
Fig. 4.11.1. CMOS as NAND gate.

Table 4.11.1. Switching operation of CMOS NAND gate

Inputs p-channel MOSFET n-channel MOSFET Output
A B Q1 Q2 Q3 Q4 V0
0 0 ON ON OFF OFF 1
0 1 ON OFF OFF ON 1
1 0 OFF ON ON OFF 1
1 1 OFF OFF ON ON 0
Que 4.12. Discuss the circuit diagram and operation of CMOS NOR
gate.
Answer
1. Fig. 4.12.1 shows a CMOS two-input NOR gate. Here, p-channel
MOSFETs Q1 and Q2 are connected in series and n-channel MOSFETs
Q3 and Q4 are connected in parallel.
VDD = +5 V
A
Q1
Q2
B
Vo
Q3 Q4
Fig. 4.12.1. CMOS as NOR.

Table 4.12.1. Switching operation of CMOS NOR gate
Inputs p-channel MOSFET n-channel MOSFET Output
A B Q1 Q2 Q3 Q4 V0
0 0 ON ON OFF OFF 1
0 1 ON OFF OFF ON 0
1 0 OFF ON ON OFF 0
1 1 OFF OFF ON ON 0
Que 4.13. Discuss the circuit and operation of CMOS transmission

gate.
Answer
1. A transmission gate is simply a digitally controlled CMOS switch. When
the switch is open (OFF), the impedance between its terminals is very
large.
2. It is used to implement special logic functions. Since the CMOS gate can
transmit signals in both directions, it is called a bilateral transmission
gate or bilateral switch.
3. It is useful for digital and analog applications. The TTL and ECL gates
are essentially unidirectional.
4. Fig. 4.13.1 shows the schematic diagram and logic symbols of a CMOS
transmission gate. The n-channel MOS and p-channel MOS transistors
are connected in parallel.
5. So, both polarities of input voltages can be switched. The control signal,
C is connected to the n-channel MOSFET and its inverse is connected to
the p-channel MOSFET.
O/P
Q1 Q2
+VDD
Control, C I/P
Fig. 4.13.1. CMOS transmission gate.
Table 4.13.1. Operation of CMOS transmission gate

Inputs p-channel n-channel Action
MOSFET MOSFET
C I/P VG1 Q1 VG2 Q2
0 0 +ve OFF 0V OFF No transmission
0 1 0V OFF –ve OFF No transmission
1 0 0V OFF +ve ON Transmission
1 1 –ve ON 0V OFF Transmission
6. So, it can be concluded that when the control, C is HIGH, the circuit acts as a
closed switch and allows the transmission of the signal from input to output.
7. When the control, C is LOW, the circuit acts as an open switch and
blocks the transmission of the signal from input to output.
8. Since, the input and output terminals are interchangeable, the circuit can also
transmit signals in the opposite direction. So, it acts as a bilateral switch.
Que 4.14. Explain TTL to CMOS interfacing and CMOS to TTL

interfacing.
Answer
TTL to CMOS :
1. The MOS and CMOS gates are slower than the TTL gates, but consume
less space. Hence, there is an advantage is using TTL and MOS devices
in combination.
2. The input current values of CMOS are low as compared to the output
current capabilities of any TTL series. Thus, TTL has no problem in
meeting the CMOS input current requirements.
3. So, a level translator is used to raise the level of the output voltage of
the TTL gate to an acceptable level for CMOS.
4. The presence of the pull-up resistor will cause the TTL output to rise to
approximately + 5 V in the HIGH state, thereby providing an adequate
CMOS input as shown in Fig. 4.14.1.
+5V +5V + 10 V
RP RP
Buffer
TTL CMOS TTL CMOS
(a) TTL to CMOS interfacing (b) TTL to CMOS interfacing

(low voltage) (high voltage)
Fig. 4.14.1.
CMOS to TTL :
1. The CMOS output can supply enough voltage and current to satisfy
the TTL input requirements in the HIGH state. Hence, no special
consideration is required for the HIGH state.
2. But the TTL input current requirements at LOW state cannot be met
directly.
3. Therefore, an interface circuit with a LOW input current requirement
and a sufficiently high output current rating is required. The
arrangement is shown in Fig. 4.14.2.
4. When a high voltage CMOS has to drive a TTL gate, a voltage level
translator that converts the high voltage input to a + 5 V output is used
between CMOS and TTL as shown in Fig. 4.14.2.
+ 15 V +5V
15 V 5V
0V 0V
CMOS Buffer Buffer

TTL input CMOS TTL
(a) CMOS to TTL (b) CMOS to TTL

interfacing (low voltage) interfacing (high voltage)
Fig. 4.14.2.
Que 4.15. Explain the interfacing of TTL to ECL and ECL to TTL.
Answer
TTL to ECL :
1. The TTL is the most widely used logic family, but its speed of operation
is not very high.
2. The ECL is the fastest family. In some applications, the rate at which
input data is to be handled may be much lower than the rate at which
the output data is to be handled.
3. Therefore, it becomes necessary to interconnect the two different logic
systems, such as TTL and ECL.
4. A TTL cannot interface directly with an ECL; it requires a translator as
shown in Fig. 4.15.1.
A
B X
TTL
TTL to ECL
ECL
translator
Fig. 4.15.1. TTL driving ECL.

5. One such application is in the time division multiplexing of n digital
signals to form a single digital signal.
6. Although, the bit rate of each of the n signals may be handled using TTL,
the bit rate of the composite signal is n times faster and may require
ECL to process it.
ECL to TTL :
1. Sometimes, the input data is at a faster rate, but the output data is at
a slower rate like in demultiplexers.
2. An ECL to TTL logic translator will be of use in such cases. It shows
that the input logic levels of a translator are compatible with the output
logic levels of ECL and the output logic levels of a translator are
compatible with the input logic levels of a TTL.
3. Fig. 4.15.2 shows the ECL gate driving a TTL gate.
A
B X
ECL
ECL to TTL TTL
VCC translator
Fig. 4.15.2. ECL driving TTL.

PART-8
Memory Elements, Concept of Programmable
Logic Devices Like FPGA.
Questions-Answers
Que 4.16. Discuss the concept of field programmable gate array

(FPGA). Describe the various structures of FPGA.
AKTU 2018-19, Marks 3.5
Answer
Field Programmable Gate Array :
1. FPGA is high capacity PLD (programmable logic device). The gate array
of FPGA has the ability to be programmed for a function by the user
instead of the manufacturer of device.
2. FPGA consists of three configurable (programmable) logic modules
(LMs) : configurable logic blocks (CLBs), input and output blocks and
switching matrix for interconnection.
3. The CLB consists of a combinational logic array, data multiplexer (MUX)
and flip-flops. The combinational array function is performed by look-up
table (LUT).
Structures of FPGA :
i. Programmable logic structure :
1. The programmable logic structure of FPGA consists of a two-dimensional
array of CLBs.
2. Each CLB typically contains one or two flip-flops to allow implementation
of sequential logic.
3. Large designs are partitioned and mapped to a number of CLBs with
each CLB configured (programmed) to perform a particular function.
4. These CLBs are then connected together to fully implement the target
design.
ii. Programmable routing structure :
1. To allow for flexible interconnection of CLB, FPGA has three
programmable routing resources.
2. Vertical and horizontal routing channels which consist of different length
of wires that can be connected together if needed.
3. These channels run vertically and horizontally between columns and
rows of CLBs as shown in the Fig. 4.16.1.
4. Connection boxes, which are set of programmable links, can connect

input and output pins of the CLBs to wires of the vertical or the horizontal
routing channels.
5. Switch boxes are located at the intersection of the vertical and horizontal
channels.
6. These are a set of programmable links that can connect wire segments
in the horizontal and vertical channels.
Vertical
channel
Programmable Horizontal
input / output channel
Configurable
logic block(CLB)
Switch box
Horizontal
connections
Vertical channel
Fig. 4.16.1. Programmable structure of
field programmable logic array (FPGA).
iii. Programmable input/output :
1. These are mainly buffers that can be configured either as input buffers
or output buffers or input/output as shown in Fig. 4.16.1.
2. These allow the pins of the FPGA chip to function either as input pins or
output pins or input/output pins.
iv. Configurable logic blocks :
1. There are a number of CLBs in an FPGA organized as an array of rows
and columns. The logic blocks are connected to the I/O blocks through
common row / column programmable interconnects.
2. The common row / column interconnects are known as global
interconnects.
3. A logic block consists of a number of LMs. The LMs are the basic logic
elements in a FPGA. The LMs within a CLB are connected through local
programmable interconnects.
v. Logic module :
1. A logic module (LM) consists of a LUT, a D-type flip-flop and a MUX.
Most of the FPGAs are based on 4-input LUT. Fig. 4.16.2 shows a block
diagram of a LM with 4-input LUT.
2. Output of the LUT becomes the output of the LM either directly or
through D-type flip-flop. Thus, the output can be configured for
combinational or registered (i.e., through flip-flop).
Four-input Output
MUX
Input look-up D
table Flip-flop
(LUT) Clock
Select lines
Fig. 4.16.2. Block diagram of logic module.
PART-9
Logic Implementation Using Programmable Devices.
Questions-Answers
Que 4.17. Draw the basic configuration of three PLDs.
Answer
1. The PROM is a combinational programmable logic device (PLD)-an
integrated circuit with programmable gates divided into an AND array
and an OR array to pro vide an AN D–OR sum-o f-product
implementation. Fig. 4.17.1 shows the configuration of the three PLDs.
Fixed AND Programmable

Inputs Outputs
array (decoder) OR array
(a) Programmable read-only memory (PROM)
Programmable Fixed
Inputs Outputs
AND array OR array
(b) Programmable array logic (PAL)
Programmable Programmable
Inputs Outputs
AND array OR array
(c) Programmable logic array (PLA)
Fig. 4.17.1.
2. The PROM has a fixed AND array constructed as a decoder and a

programmable OR array. The programmable OR gates implement the
boolean functions in sum-of-minterms form.
3. The PAL has a programmable AND array and a fixed OR array. The
AND gates are programmable to provide the product terms for the
boolean functions which are logically summed in each OR gate.
4. The most flexible PLD is the PLA, in which both the AND and OR arrays
can be programmed. The product terms in the AND array may be shared
by any OR gate to provide the required sum of products implementation.
Que 4.18. What is the basic architecture of a PLA ? How is the

capacity of a PLA specified ? How is it programmed ? Explain.
OR
Write a short note on PLA. AKTU 2017-18, Marks 3.5
OR
Write down the classification of semiconductor memories. Draw
and explain the programmable logic array (PLA).
Answer
Classification of semiconductor memories :
Fig. 4.18.1 shows an overview of semiconductor memory types.
Semiconductor memories
Read/write memory Read only memory

or random access memory (RAM) (ROM)
Dynamic RAM Static • Mask (Fuse) ROM

(DRAM) RAM • Programmable ROM (PROM)
(SRAM) • Erasable PROM (EPROM)
• Electrically Erasable PROM
• Flash memory
• Ferroelectric RAM (FRAM)
Fig. 4.18.1. Classification of semiconductor memories.
Programmable logic array (PLA) :
1. PLAs are used to map irregular combinational function onto regular
structures. The PLA provides the designer with a systematic and regular
way of implementing output functions of n variable in sum of product
form.
2. PLA is one of the regular macro used in the implementation of FSM
(finite state machine). PLA functions may be significantly changed
without requiring major changes of either the design or layout. It is
more compact in nature. Any of the logical function can be expressed in
terms of SOP or POS.
3. PLA can be implemented in se veral forms, i.e., N OR–NOR,

NAND–NAND, NAND–NOR.
4. The structure of PLA is shown in Fig. 4.18.2, and its internal logic with
three inputs and two outputs is shown in Fig. 4.18.3.
5. The particular boolean functions implemented in the PLA of
Fig. 4.18.3, are
F1 = AB  AC  ABC
F2 = ( AC  BC )
· ·
m input · AND · OR
lines · array · array
· ·
·· ·
n output lines
Fig. 4.18.2. PLA structure.
6. The programming table that specifies the PLA of Fig. 4.18.3 is listed in
the table 4.18.1. The PLA programming table consists of three sections.
A
C
×× 1 ×
× × 2 × × AC
× × 3 × BC
×× × 4 ×
C C B B A A × 0
× 1
F1
F2
Fig. 4.18.3. PLA with three inputs, four product terms, and two outputs.
7. The first section lists the product term numerically. The second section
specifies the required paths between input and AND gates. The third
section specifies the path between the AND and OR gates.
8. For each output variable, we may have a T (true) or C (complement)
for programming the XOR gate.
9. For each product term, the inputs are marked with 1, 0 or — (dash).
10. If the variable in the product term appears in the form in which it is
true, the corresponding input variable is marked with a 1. If it appears
complemented, the corresponding input variable is marked with a 0. If
the variable is absent from the product term, it is marked with a dash.
Table 4.18.1. PLA programming
Input Output
Product term A B C (T) F1 (C) F2
AB 1 1 0 — 1 —
AC 2 1 — 1 1 1
BC 3 — 1 1 — 1
ABC 4 0 1 0 1 —
11. The size of the PLA is specified by the number of inputs, the number of
product terms, and the number of outputs. A typical integrated circuit
PLA may have 16 inputs, 48 product terms and eight outputs.
12. For n inputs, k product terms, and m outputs, the internal logic of the
PLA consists of n buffer-inverter gates, k AND gates, m OR gates, and
m XOR gates.
Que 4.19. Draw the logic configuration of four input and four
output PAL and explain.
Answer
1. A programmable array logic has the same structure as a ROM, but has
a programmable AND array and a fixed OR (or NOR) array.
2. Because of the fixed OR array, a PAL device is cheaper comparatively
and easier to program.
3. However, the lack of shared rows with the column requires that each
output function be simplified, with no common product term with others.
It is easier to program, but is not flexible.
PAL with the four input and four output :
1. Each input has a buffer-inverter gate and each output is generated by
fixed OR gate.
2. In designing with a PAL, the boolean function must be simplified to fit
into each section unlike the situation with a PLA, a product term cannot
be served among two or more OR gates. Therefore, each function can
be simplified by itself, without regarding common product terms.
3. The number of product terms in each section is fixed, and if the number
of terms in the function is too large, it may be necessary to have two
sections to implement one boolean function.
AND gate input
1 2 3 4 5 6 7 8 9 10
Product term
1
2
F1
3
I1
4
5
F2
6
I2
7
8 F3
9
I3
10
11
F4
12
I4
1 2 3 4 5 6 7 8 9 10
Fig. 4.19.1. PAL with four inputs, four outputs and a three wire
AND-OR structure.
Que 4.20. Realize the full adder circuit using the PAL.
Answer
Full adder using PAL : There are two functions used for the
implementation of full adder :
S = ABC  ABC  ABC  ABC
C = ABC  ABC  ABC  ABC

A A B B C C
× × ×
× × × S
× × ×
× × ×
A
× × ×
× × × C
× × ×
× × ×
Fig. 4.20.1.
Que 4.21. Differentiate between PLA and PAL. Realize the full
adder circuit using PAL. AKTU 2018-19, Marks 3.5
Answer
A. Difference :
S. No. PAL PLA
1. It is moderately expensive It is expensive than PAL and PROM
and moderately complicated. and complicated to use.
2. In this, only the AND array In this, both AND and OR arrays
is programmable, OR array are programmable.
is fixed.
3. It is easier to program It is complicated to program because
because only the AND gates both the AND and OR gates are
are programmable. programmable.
4. It is less flexible due to fixed It is more flexible than PAL.
OR gates.
B. Full adder using PAL : Refer Q. 4.20, Page 4–24B, Unit-4.

Que 4.22. Implement the following four boolean functions with a

PAL.
W (A, B, C, D) = m(2, 12, 13)
X (A, B, C, D) = m(7, 8, 9, 10, 11, 12, 13, 14, 15)
Y (A, B, C, D) = m(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
Z (A, B, C, D) = m(1, 2, 8, 12, 13)
Answer
1. Simplifying the four functions to a minimum number of terms results
in the following boolean functions :
CD For W CD For X
AB 00 01 11 10 AB 00 01 11 10
00 1 00
0 1 3 2 0 1 3 2
01 01 1
4 5 7 6 4 5 7 6
11 1 1 11 1 1 1 1
12 13 15 14 12 13 15 14
10 10 1 1 1 1
8 9 11 10 8 9 11 10
CD For Y CD For Z
AB 00 01 11 10 AB 00 01 11 10
00 1 1 1 00 1 1
0 1 3 2 0 1 3 2
01 1 1 1 1 01
4 5 7 6 4 5 7 6
11 1 11 1 1
12 13 15 14 12 13 15 14
10 1 1 1 10 1
8 9 11 10 8 9 11 10
Fig. 4.22.1.
W = ABC  ABCD
X =  + BCD
Y = AB  CD  BD
Z = ABC  ABCD  ACD  ABCD
= W  ACD  ABCD
2. Table 4.22.1 lists the PAL programming table for the four boolean
functions. The table 4.22.1 is divided into four sections with three
product terms in each section.
3. The first two sections need only two product terms to implement the
boolean function. The last section for output Z needs four product
terms. Using the output from W, we can reduce the function to three
terms.
4. The fuse map for the PAL as specified in the programming Table 4.22.1
is shown in Fig. 4.22.2 for each 1 or 0 in the Table 4.22.1.
5. We mark the corresponding intersection in the diagram with the symbol
for an intact fuse. For each dash, we mark the diagram with blown
fuses in both the true and complement inputs.
6. If the AND gate is not used we leave all its input fuse intact. Since the
corresponding input receives both the true value and the complement
of each input variable, we have A A = 0 and the output of the AND
gate is always 0.
Table 4.22.1. PAL programming
Product Term AND Input Outputs
A B C D W
1 1 1 0 — — W = ABC  ABCD
2 0 0 1 0 —
3 — — — — —
4 1 — — — — X =  + BCD
5 — 1 1 1 —
6 — — — — —
7 0 1 — — — Y = AB  CD  BD
8 — — 1 1 —
9 — 0 — 0 —
10 — — — — 1 Z = W + ACD  ABCD
11 1 — 0 0 —
12 0 0 0 1 —
Product A A B B C C D D W W
term
1 × × ×
2 × × × × W
3 ×
A
4 ×
5 × × × X
6 ×
B All fuses intact
(always = 0)
7 × ×
8 × × Y
9 × ×
C
10 ×
11 × × × Z
12 × × × × × Fuse intact
D + Fuse blown
A A B B C C D D W W
Fig. 4.22.2. Fuse map for PAL as specified in Table. 4.22.1.
Que 4.23. A combinational circuit is defined by the functions :

F1(A, B, C) = m(3, 5, 6)
F2(A, B, C) = m(0, 2, 7)
Implement the circuit with a PLA.
Answer
Simplify the given boolean expression
F1(A, B, C) = m(3, 5, 6)
F2(A, B, C) = m(0, 2, 7)
BC For F1 : BC For F 2 :
A 00 01 11 10 A 00 01 11 10
0 1 0 1 1
0 1 3 2 0 1 3 2
1 1 1 1 1
4 5 7 6 4 5 7 6
F1 = ABC + ABC + ABC F2 = AC + ABC

Fig. 4.23.1.
PLA program table :
Product term Inputs Outputs
A B C F1 F2
ABC 0 1 1 1 –
ABC 1 0 1 1 –
ABC 1 1 0 1 –
AC 0 – 0 – 1
ABC 1 1 1 – 1
Implementation :
A
× × ×
× ×
B × × ×
×
C × × ×
× ×
Product
term
ABC ABC ABC AC ABC
× × × F1
× × F2
Sum
term
Fig. 4.23.2.
Que 4.24. Design a 3-bit binary to Gray code converter using PLA.

Answer
Truth table :
Binary input Gray output

B2 B1 B0 G2 G1 G0
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0
Simplification using K-map :

The K-maps for the Gray outputs are as shown in Fig. 4.24.1.
For G 2 For G 1
B1B0 B1B0
B2 00 01 11 10 B2 00 01 11 10
0 0 0 0 0 0 0 0 1 1
0 1 3 2 0 1 3 2
1 1 1 1 1 1 1 1 0 0
4 5 7 6 4 5 7 6
(a) (b )
B1B0 For G0
B2 00 01 11 10
0 0 1 0 1
0 1 3 2
1 0 1 0 1
4 5 7 6
(c )
Fig. 4.24.1.
G2 = B2
G1 = B2 B1  B2 B1
G0 = B1 B0  B1 B0
Implementation :
Fig. 4.24.2 shows the implementation using PLA.
B0
× B0
× B0
Binary B1 × × B1
AND matrix
inputs × × B1
B2 × × B2
× B2
B2
B0B1 B 0B 1 B 2B 1 B 2B 1
× G2
× × G0
Gray
output
× × G1
Fig. 4.24.2. OR matrix

Q. 1. Describe the circuit and performance of CMOS inverter and

state the characteristics of CMOS.
Q. 2. Discuss the concept of field programmable gate array

(FPGA). Describe the various structures of FPGA.
Q. 3. What is the basic architecture of a PLA ? How is the capacity

of a PLA specified ? How is it programmed ? Explain.
Q. 4. Differentiate between PLA and PAL. Realize the full adder

circuit using PAL.
Q. 5. Implement the following four boolean functions with a

PAL.
W (A, B, C, D) = m(2, 12, 13)
X (A, B, C, D) = m(7, 8, 9, 10, 11, 12, 13, 14, 15)
Y (A, B, C, D) = m(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
Z (A, B, C, D) = m(1, 2, 8, 12, 13)
Q. 6. Design a 3-bit binary to Gray code converter using PLA.

Q. 7. Describe the construction and operation of TTL NAND gate.

Q. 8. Draw the basic configuration of three PLDs.


5 D/A and A/D Converter
CONTENTS
Part-1 : Weighted Resistor, R–2 R Ladder ........... 5–2B to 5–7B
Part-2 : Resistor String ............................................ 5–7B to 5–8B
Part-3 : Analog to Digital Converters : ............... 5–8B to 5–10B

Single Slope
Part-4 : Dual Slope, Successive .......................... 5–10B to 5–15B

Approximation, Flash
Part-5 : Switched Capacitor Circuits : ............... 5–15B to 5–17B

Basic Concepts, Practical
Configurations
Part-6 : Application in Amplifier ......................... 5–17B to 5–18B
Part-7 : Integrator, ADC ...................................... 5–18B to 5–20B

5–2 B (EC-Sem-3) D/A and A/D Converter
PART-1
Weighted Resistor, R–2 R Ladder.
Questions-Answers
Que 5.1. Explain working of weighted resistor D/A converter.
Answer
1. In a weighted resistor D/A converter every resistor has a definite weight
assigned to it.
2. One of the simplest circuit shown in Fig. 5.1.1, is a summing amplifier
with a binary weighted resistor network. It has n-electronic switches
Dn, Dn–1 ... D2, D1 controlled by binary input word.
3. If the binary input to a particular switch is 1, it connects the resistor to
the reference voltage (– VR). And if the input bit is 0, the switch connects
the resistor to the ground.
Rf
Io
a –
In
I3 I2 I1 Io Vo
+
n 3 2 1
2R 2R 2R 2R
(LSB) Dn D3 D2 D1
(MSB)
–VR
Fig. 5.1.1. A simple weighted resistor D/A converter.
4. From Fig. 5.1.1, the output current Io for an ideal op-amp can be written
as
Io = I1 + I2 + I3 ... + In
VR V V V
= D1  2R D2  3R D3  ...  nR Dn
2R 2 R 2 R 2 R
VR
= ( D1 2  D2 2  D3 2  ...  Dn 2 n )
1 2 3
R
5. The output voltage,

Vo = IoRf
Rf
= VR ( D1 2 1  D2 2 2  D3 2  3  ...  Dn 2 n )
R
Que 5.2. Draw a 4-bit binary weighted D/A converter, find the
value of step size if R = 10 K and Rf = 1.2 K. What is the output
voltage when all binary inputs are at 5 V ?
Answer
A. Weighted resistor D/A converter :
Rf
Io
a –
I4 I3 I2 I1 Io Vo
+
4 3 2 1
2R 2R 2R 2R
LSB D4 D3 D2 D1
(MSB)
–VR
Fig. 5.2.1. 4-bit binary weighted resistor D/A converter.
B. Numerical :
Given : R = 10 K, Rf = 1.2 K, Vin = 5 V, N = 4
To Find : Step size, Output voltage.
Vin 5 5
1. Step size = N
 4  = 0.333 V
2 – 1 2  1 15
Rf
2. Output voltage = VR (2 1  2 2  2  3  2 4 )
R
5  1.2 1 1 1 1
=     
10 2 4 8 16 
= 0.5625 V
Que 5.3. What is a DAC ? Describe the weighted resistor DAC.

Give mathematical expressions in support of your answer.
OR
Explain different types of DAC.
Answer
DAC :
1. It is the process of taking a value represented in digital code and
converting it into a voltage or current which is proportional to digital
value. It is accomplished by the use of DAC or D/A converter.
2. The analog voltage output Vo of an N-bit straight binary D/A converter
is related to the digital input by the relation.
Vo = K (2N–1 bN–1 + 2N–2 bN–2 + ... 22 b2 + 2 b1 + b0)
K = Proportionality factor
bN = 1, if Nth bit of digital input is 1
= 0, if Nth bit of digital input is 0.
There are two types of D/A converters :
i. Weighted resistor D/A converter : Refer Q. 5.1, Page 5–2B, Unit-5.
ii. R-2R Ladder D/A converter :
1. This network uses resistors of only two values R and 2R. The inputs to
the resistor network are applied through digitally controlled switches.
RF
R R 2R
–
+ Vo
2R 2R 2R 2R
LSB
MSB
0 1 0 1 0 1
VR VR VR
Fig. 5.3.1.
2. Consider a 3 bit R-2R Ladder D/A network. Let us assume a digital input
of 001. The equivalent circuit becomes as shown in Fig. 5.3.2.
X Y Z
R R 2R
2R 2R 2R 2R
X Y Z
VR
Fig. 5.3.2.
3. Applying Thevenin’s theorem at point XX', we get
Y Z
R X R R 2R
VR
2 2R 2R
X
Y Z
Fig. 5.3.3.
4. Applying Thevenin's theorem at YY', we get
R Y R Z 2R
VR
2R
22
Y Z
Fig. 5.3.4.
5. Applying Thevenin's theorem at ZZ', we get

R Z 2R
VR
3
2
Z
Fig. 5.3.5.
6. The equivalent resistance is 3R in each case. The circuit reduces to
VR 3R RF
3
2
VR 3R
2 –
2 + Vo
VR 3R
2
Fig. 5.3.6.
7. The output voltage is given as
 Rf VR Rf VR Rf VR 
Vo =   b  b  b2
 3 R 23 0
3 R 2 2 1
3 R 21 
Rf VR
=  [4 b2  2b1  b0 ]
3 R 23
8. The number of resistors required for N-bit D/A converter is 2N in the
case of R-2R ladder D/A converter.
Que 5.4. Explain the performance characteristics of D/A

converters.
Answer
1. Resolution :
i. It is the smallest possible change in output voltage as a fraction or
percentages of the full-scale output range.
ii. Example for a 8-bit converter there are 28 or 256 values of analog output
voltage, hence the smallest change in the output voltage is 1/255th of full
scale output range.
2. Linearity :
i. The input-output relationship should be linear for a D/A converter. But
sometimes the relation is non-linear. This is due to error in resistor
values and voltage across the switches.
ii. If converter was ideal the dots will fall on straight line. But if it has
errors it is indicated by as shown in Fig. 5.4.1.
3. Accuracy : It is the measure of the difference between the actual
output voltage and expected output voltage. It is specified as percentage
of full scale or maximum output voltage.
4. Settling time : When a digital input to a D/A converter changes, the
output voltage does not change abruptly because of the delay in the
circuit. The time required for the analog output voltage to settle within
 (1/2) LSB of the final value after a change in digital input is called
settling time.
7
6
5
4 
3
2
000 001 010 011 100 101 110 111

Fig. 5.4.1.
PART-2
Resistor String.
Questions-Answers
Que 5.5. Write a short note on resistor string.
Answer
1. A simple DAC that in inherently monotonic is the resistor string DAC,

as shown in Fig. 5.5.1.
2. In this circuit, a reference voltage (VREF) is connected across a resistor
string of equal value resistance.
3. For an n-bit DAC, this requires 2n resistors and the taps between the
resistors are connected to switches controlled by the digital logic input
values (and their complement).
4. At the output node, an output voltage (VOUT) is generated, the value set
by the positions of the switches.
5. The output would need to be suitably buffered in order to prevent
electrical loading of the converter output.
VREF R +
–
R VOUT
(LSB) b2 b2 b1 b1 (MSB)
Fig. 5.5.1. Resistor string DAC.
PART-3
Analog to Digital Converters : Single Slope.
Questions-Answers
Que 5.6. Write short note on analog to digital converter (ADC).
Answer
1. The block schematic of ADC in Fig. 5.6.1 provides the function just
opposite to that of a DAC.
Start EOC
d1 MSB
d2
Analog Digital
ADC output
input Va
dn
VR(Reference)
Fig. 5.6.1. Functional diagram of ADC.
2. It accepts an analog input Va and produces an output binary word
d1, d2,..., dnof functional value D, so that
D = d12 – 1 + d22 – 2 + ... + dn2 – n ...(5.6.1)
where d1 is the most significant bit and dn is the least significant bit.
3. An ADC usually has two additional control lines, the START input to tell
the ADC when to start the conversion and the EOC (end of conversion)
output to announce when the conversion is complete.
4. Depending upon the type of application, ADCs are designed for
microprocessor interfacing or to directly drive LCD or LED displays.
5. ADCs are classified broadly into two groups according to their conversion
technique.
6. These are Direct type ADCs and Integrating type ADCs. Direct type
ADCs compares a given analog signal with the internally generated
equivalent signal.
7. Integrating type ADCs perform conversion in an indirect manner by
first changing the analog input signal to a linear function of time or
frequency and then to a digital code. The two most widely used integrating
type converters are :
i. Charge balancing ADC.
ii. Dual slope ADC.
8. The most commonly used ADCs are successive approximation and the
integrator type. The successive approximation ADCs are used in
applications such as data loggers and instrumentation where conversion
speed is important.
9. The successive approximation and comparator types are faster but
generally less accurate than integrating type converters. The flash
(comparator) type is expensive for high degree of accuracy.
10. The integrating type converter is used in applications such as digital
meter, panel meter and monitoring systems where the conversion
accuracy is critical.
Que 5.7. Explain the working of single slope ADC.
Answer
1. It consists of a ramp generator and BCD or binary counters. The
Fig. 5.7.1 shows the single slope ADC.
2. At the start, the reset signal is provided to the ramp generator and the
counters. Thus counters are reset to 0’s.
3. The analog input voltage Vin is applied to the positive terminal of the
comparator.
4. As this is more positive than the negative input, the comparator output
goes high.
5. The output of ramp generator is applied to the negative terminal of the
comparator.
6. The high output of the comparator enables the AND gate which allows
clock to reach to the counters and also this high output starts the ramp.
7. The ramp voltage goes positive until it exceeds the input voltage. When
it exceeds Vin, comparator output goes low.
8. This disables AND gate which in turn stops the clock to the counters.
The control circuitry provides the latch signal which is used to latch the
counter data.
9. The reset signal resets the counters to 0’s and also resets the ramp
generator. The latched data is then displayed using decoder and a display
device.
Analog
input Clock
Vin IN
+
– AND gate
Comparator
BCD or Binary counters
Ramp Timing and Reset
generator Ramp control
Latches
reset Latch
Decoder or drivers
Display
Fig. 5.7.1. Single slope ADC.
PART-4
Dual Slope, Successive Approximation, Flash.
Questions-Answers
Que 5.8. Explain the working of dual slope integrating ADC with
the help of circuit diagram.
Answer
1. Fig. 5.8.1(a) shows the dual slop ADC functional diagram. The circuit
consists of a high input impedance buffer A1, precision integrator A2 and
a voltage comparator.
2. The converter first integrates the analog input signal Va for a fixed
duration of 2n clock periods as shown in Fig. 5.8.1(b).
3. Then it integrates an internal reference voltage VR of opposite polarity
until the integrator output is zero.
4. The number N of clock cycles required to return the integrator to zero

is proportional to the value of Va averaged over the integration period.
Hence, N represents the desired output code.
R C
v0
– – –
Va + SW 1 A1 A2 CMP
– + + +
+
– SW2
VR
CAZ
Start d1
Control n-stage d2
EOC logic counter dn
(a)
Integrator
output voltage
vo
Autozero T = 2nT N-cycles Autozero
1
t1 t2 t3
0
Time
v1
Integrate Integrate
Va –VR
(b)
Fig. 5.8.1. (a) Functional diagram of the dual slope ADC
(b) Integrated output waverform for the dual slope ADC.
Operation :
1. Before the START command arrives, the switch SW1 is connected to
ground and SW2 is closed.
2. Any offset voltage present in the A 1 , A 2 , comparator loop after
integration, appears across the capacitor CAZ till the threshold of the
comparator is achieved.
3. The capacitor CAZ thus provides automatic compensation for the
input-offset voltages of all the three amplifiers.
4. Later, when SW2 opens, CAZ acts as a memory to hold the voltage required
to keep the offset nulled.
5. At the arrival of the START command at t = t1, the control logic opens
SW2 and connects SW1 to Va and enables the counter starting from zero.
6. The analog voltage Va is integrated for a fixed number 2n counts of clock
pulses after which the counter resets to zero.
7. If the clock period is T, the integration takes place for a time

T1 = 2n × T and the output is a ramp going downwards as shown in
Fig. 5.8.1(b).
8. The counter resets itself to zero at the end of the interval T1 and the
switch SW1 is connected to the reference voltage (– VR).
9. The output voltage vo will now have a positive slope. However, when vo
becomes just zero at time t = t3, the control logic issues an end of
conversion (EOC) command and no further clock pulses enter the
counter.
2 n counts
T1 = t2 – t1 =
Clock rate
Digital count N
and t3 – t2 =
Clock rate
10. For an integrator,
vo = (– 1/RC) V (t)
11. The voltage vo will be equal to v1 at the instant t2 and can be written as
v1 = (– 1/RC) Va(t2 – t1)
12. The voltage v1 is also given by
v1 = (– 1/RC) (– VR) (t2 – t3)
So, Va(t2 – t1) = VR(t3 – t2)
Putting the value of (t2 – t1) = 2n and (t3 – t2) = N, we get
Va(2n) = (VR)N
or, Va = (VR) (N/2n)
Que 5.9. Write a short note on successive approximation A/D

converter.
Answer
1. The successive approximation technique uses a very efficient code
strategy to provide n-bit conversion in n-clock periods.
Start EOC
Va –
SAR CLK
+
Vd d1 d2 d8
d1(MSB)
d2
d8
DAC
Fig. 5.9.1. Functional diagram of the successive approximation ADC.

Working :
1. With the arrival of the START command, the SAR sets the MSB d1 = 1
with all other bits to zero so that the trial code is 10000000.
2. The output Vd of the DAC is now compared with analog input Va. If Va
is greater than the DAC output Vd then 10000000 is less than the correct
digital representation.
3. The MSB is left at ‘1’ and the next lower significant bit is made ‘1’ and
further tested.
4. However, if Va is less than the DAC output, then 10000000 is greater
than the correct digital representation.
5. So reset MSB to ‘0’ and go on to the next lower significant bit. This
procedure is repeated for all subsequent bits, one at a time, until all bit
positions have been tested.
6. Whenever the DAC output crosses Va, the comparator changes state
and this can be taken as the end of conversion (EOC) command.
Que 5.10. Draw and explain the flash type A/D converter. Also
discuss the corresponding digital output with respect to input signal
voltage.
OR
Design a parallel-flash ADC and explain its working.
Answer
The commonly used A/D converter is parallel or flash converter. A 3-bit

parallel comparator A/D converter is shown in Fig. 5.10.1.
Working :
1. Let Va is the input analog voltage to be converted into digital form. The
reference voltage like Vr1, Vr2, ….. are generated using resistor network.
2. Va is compared simultaneously with the reference voltage by using
comparators.
V
R/2
Vo
Vr7 = 13/14 V –
+ C7
R
Vr6 = 11/14 V –
+ C6
R
Vr5 = 9/14 V – L D
+ B1
R C5 A E
Vr4 = 7/14 V – T C Digital
+ C O B2
C4 output
R H D
Vr3 = 5/14 V –
E E B0
+ C3
R S R
Vr2 = 3/14 V –
+ C2
R
Vr1 = 1/14 V –
+ C1
R/2
Fig. 5.10.1.
3. A 7-bit output is obtained from the comparator is converted to a 3-bit

output using decoder circuit.
4. The process adopted here is the simplest and it works quite fast.
5. The demerits rapidly increase in the number of comparators with the
number of bits and the corresponding complications of the decoder circuit.
6. The analog input, comparator outputs and digital output are shown in
Table 5.10.1
Table 5.10.1.
Analog input Comparator outputs Digital output
Va C7 C6 C5 C4 C3 C2 C1 B2 B1 B0
0  Va < Vr1 0 0 0 0 0 0 0 0 0 0
Vr1 < Va < Vr2 0 0 0 0 0 0 1 0 0 1
Vr2 < Va < Vr3 0 0 0 0 0 1 1 0 1 0
Vr3 < Va < Vr4 0 0 0 0 1 1 1 0 1 1
Vr4 < Va < Vr5 0 0 0 1 1 1 1 1 0 0
Vr5 < Va < Vr6 0 0 1 1 1 1 1 1 0 1

Vr6 < Va < Vr7 0 1 1 1 1 1 1 1 1 0
Vr7 < Va  V 1 1 1 1 1 1 1 1 1 1
PART-5
Switched Capacitor Circuits : Basic Concept,
Practical Configurations.
Questions-Answers
Que 5.11. Explain a 4-bit switched capacitor DAC.
Answer
1. Fig. 5.11.1(a) shows a 4-bit switched capacitor DAC, that the capacitance
values have binary weights.
2. A two-phase clock is used to control switching of the capacitors. When 1
goes HIGH, all capacitors are switched to ground and discharged.
3. When 2 goes HIGH, those capacitors where the digital inputs are HIGH
are switched to EREF , whereas those inputs are LOW remain grounded.
4. Fig. 5.11.1(b) shows the equivalent circuit when 2 is HIGH and the
digital input is 1101.
C C C C C
2 4 8 8
V out
Two-phase
clock  1,  2
+ –
EREF
D3 D2 D1 LSB D0
MSB
Digital input
(a) All capacitors are switched to ground by  2. Those capacitors whose
digital inputs are HIGH are switched to EREF by  2.
C C C C
C Vout
2 8 4 8
EREF
(b) Equivalent circuit when the input is 1101. The capacitors switched
to EREF are in parallel as are the ones connected to ground.
13C 3C 13C
V out = E REF 13
8 8 8 = EREF
16
EREF 2C
(c) Circuit equivalent to (b). The output is determined

by a capacitor voltage divider.
C C C C 0 =
C Vout = EREF 0V
2 8 4 8 2C
EREF
(d) Equivalent circuit when the input is 0000.

Fig. 5.11.1. The switched capacitor type DAC.
5. The capacitors whose digital inputs are 1, are in parallel and the capacitors
whose digital inputs are 0, are in parallel with C/8.
6. The circuit as shown in Fig. 5.11.1(c), where each set of the parallel
capacitors is replaced by its equivalent capacitance. The output of the
capacitive voltage divider is
 13C 
  13
Vout = E REF  8   EREF
 2C  16
 
7. In general, for any binary input,
 CEQ 
Vout =  E
 2C 
where 2C is the sum of all the capacitance values in the circuit and CEQ
is the sum of all the capacitors whose digital inputs are HIGH.
8. The analog output is proportional to the digital input. When the input is
0000, the positive terminal of EREF is effectively open-circuited as shown
in Fig. 5.11.1(d) so, the output is 0 V.
9. Switched capacitor technology has been developed for implementing

analog functions in integrated circuits, particularly MOS circuits. It is
used to construct filters, amplifiers, and many other special devices.
10. The principal advantage of this technology is that, small capacitors of
the order of a few picofarads can be constructed in the integrated circuits
to perform the function of the much larger capacitors that are normally
needed in low-frequency analog circuits.
PART-6
Application in Amplifier.
Questions-Answers
Que 5.12. Write a short note on switched capacitor amplifier.
Answer
1. The switched capacitor amplifier of Fig. 5.12.1 lends itself to
implementation in CMOS technology much more easily than in other
technologies.
2. This is because discrete-time operations require switches to perform
sampling as well as a high input impedance to sense the stored quantities
with no corruption.
3. For example, if the op-amp of Fig. 5.12.1 incorporates bipolar transistors
at its input, the base current drawn from the inverting input in the
amplification phase Fig. 5.12.1 creates an error in the output voltage.
Vin Vout
CLK
Sample
Amplify
t
Fig. 5.12.1. General view of switched-capacitor amplifier.
4. The existence of simple switches and high input impedance has made
CMOS technology the dominant choice for sampled-data applications.
5. The foregoing discussion leads to the conceptual view illustrated in

Fig. 5.12.1 for switched-capacitor amplifiers. In the simplest case, the
operation takes place in two phases : sampling and amplification. Thus,
in addition to the analog input, Vin, the circuit requires a clock to define
each phase.
PART-7
Integrator, ADC.
Questions-Answers
Que 5.13. Discuss switched-capacitor (SC) parasitic-sensitive

integrator with circuit diagram.
Answer
C1 Cp4
C p3
1 2
Vin –
CR1 Vout
+
Cp1
Cp2
Fig. 5.13.1. Switched-capacitor parasitic-sensitive integrator.

1. The SC parasitic-sensitive integrator as shown in Fig. 5.13.1 was
suggested by replacing the resistor in a Miller integrator with a parallel
switch network.
2. Analyzing the charge across the capacitors in each phase, and considering
that the output of the circuit will be sampled at the end of phase 1,
Table 5.13.1 is obtained. Capacitance Cp1 represents the top plate parasitic
capacitance of CR1 and the parasitic.
Table 5.13.1. Charge in the capacitors in each phase.

(n – 1)T (n – 0.5)T nT
QC Vin[(n – 1)T]CR1 0 Vin[nT]CR1
R1
QC – Vout[(n – 1)T]C1 – Vout[(n–0.5)T]C1 – Vout[nT]C1

1
QC Vin[(n – 1)T]Cp1 0 Vin[nT]Cp1

p1
QC 0 0 0
p2
QC 0 0 0
p3
QC Vout[(n – 1)T]Cp4 Vout[(n – 0.5)T]Cp4 Vout[nT]Cp4

p4
3. Capacitances of both switches; capacitance Cp2 represents the bottom

plate parasitic capacitance of CR1; capacitance Cp3 represents the top
plate parasitic capacitance of C1, the input capacitance of the op-amp,
and the parasitic capacitance of switch 2.
4. Capacitance Cp4 represents the bottom plate parasitic capacitance of C1
and the input capacitance of the following stage.
5. Considering the transition (n – 1)T  (n – 0.5)T (1  2) and the
transition (n – 0.5)T  (n)T (2 1), Eq. 5.14.1 is obtained from adding
all the capacitors that are connected to the virtual ground at the end of
that transition (2 in the first case and 1 in the second).
6. From the calculations it can also be concluded that the parasitic
capacitance Cp3 does not influence the performance of the circuit due to
the virtual ground node in the negative node of the op-amp.
Que 5.14. Write a short note on parasitic-insensitive integrator.
Answer
Parasitic-Insensitive Integrator :
1. To overcome the nonlinear effect of the parasitic capacitance Cp1, new
parasitic-insensitive structures were developed.
2. Fig. 5.14.1 shows one of these structures. Analyzing the charge across
the capacitors in each phase, and considering that the output of the
circuit will again be sampled at the end of phase 1, Table 5.14.1 is
obtained.
3. Capacitance Cp1 represents the bottom plate parasitic capacitance of CR1
and the parasitic capacitances of the switches connected to the bottom
plate of CR1.
4. Capacitance Cp2 represents the top plate parasitic capacitance of CR1
and the parasitic capacitances of the switches connected to the top plate
of CR1.
C1 Cp4
Cp3
Cp1 Cp2
1
2
Vin –
Vout
C R1 +
2 1
Fig. 5.14.1. Switched-capacitor parasitic-insensitive integrator.
Table 5.14.1. Charge in the capacitors in each phase.

(n – 1)T (n – 0.5)T nT
QC – Vin[(n – 1)T]CR1 0 – Vin[nT]CR1
R1
QC – Vout[(n – 1)T]C1 – Vout[(n–0.5)T]C1 – Vout[nT]C1
1
QC Vin[(n – 1)T]Cp1 0 Vin[nT]Cp1
p1
QC 0 0 0
p2
QC 0 0 0
p3
QC Vout[(n – 1)T]Cp4 Vout[(n – 0.5)T]Cp4 Vout[nT]Cp4
p4
5. Capacitance Cp3 represents the top plate parasitic capacitance of C1, the
input capacitance of the op-amp, and the parasitic capacitance of switch
connected to the top plate of C1.
6. Capacitance Cp4 represents the bottom plate parasitic capacitance of C1
and the input capacitance of the following stage.
7. Considering the transition (n – 1)T  (n – 0.5)T (1  2) and the
transition (n – 0.5)T  (n)T (2 1), Eq. 5.14.1 is obtained from adding
all the capacitors that are connected to the virtual ground at the end of
that transition (2 in the first case and 1 in the second).

Q. 1. Explain working of weighted resistor D/A converter.

Q. 2. What is a DAC ? Describe the weighted resistor DAC. Give

mathematical expressions in support of your answer.
Q. 3. Write short note on analog to digital converter (ADC).

Q. 4. Explain the working of single slope ADC.

Q. 5. Explain the working of dual slope integrating ADC with

the help of circuit diagram.
Q. 6. Draw and explain the flash type A/D converter. Also discuss
the corresponding digital output with respect to input
signal voltage.

SQ–1 B (EC-Sem-3) Digital System Design
Logic Simplification
1 and Combinational
Logic Design
(2 Marks Questions)
1.1. Define combinational circuits.

Ans. It consists of input variables, logic gates and output variables. Logic
gates accept signal from input variable and generate output signals.
This process transforms binary information from given input data
to the required output data.
1.2. Write the difference between combinational and sequential

circuits. AKTU 2017-18, Marks 02
Ans.
S. No. Combinational circuits Sequential circuits.
1. It consists of interconnection It consists of storage elements
of logic gates only. and logic gates.
2. Output o f co mbinational Output of sequential circuit
circuits depends only on the depends on present and previous
present value of input. value of input and output.
1.3. In how many ways the binary codes are classified ?

Ans.
1. Weighted codes
2. Non-weighted codes
3. Reflective codes
4. Sequential codes
5. Alphanumeric codes
6. Error detecting and correcting codes.
1.4. Define cyclic codes. AKTU 2018-19, Marks 02

Ans. When a bit pattern of two consecutive numbers differ by only one
bit position, these codes are called cyclic codes.
SQ–2 B (EC-Sem-3) 2 Marks Questions
1.5. Write the advantages of Gray code over the straight binary
number sequence. AKTU 2016-17, 2018-19; Marks 02
Ans.
1. The Gray code is used in applications in which the normal sequence
of binary numbers generated by the hardware may produce an
error or ambiguity during the transition from one number to the
next. The Gray code eliminates this problem, since only one bit
change its value during any transition between two numbers.
2. Gray code represents analog data by a continuous change in the
angular position of a shaft. Gray code eliminates ambiguity between
the angle of the shaft and the value encoded by the sensor.
1.6. Convert (153.513)10 to an octal number ?

Ans.
(153)10 to octal : (0.513)10 to octal :
8 153 1 0.513 × 8 = 4.104
0.104 × 8 = 0.832
8 19 3 0.832 × 8 = 6.656
8 2 2 0.656 × 8 = 5.248
0.248 × 8 = 1.984
0
0.984 × 8 = 7.872
(153)10 = (231)8, (0.513)10 = (0.406517......)8
So, (153.513)10 = (231.406517)8
1.7. Write four advantages of digital systems over analog

system. AKTU 2017-18, Marks 02
Ans.
1. Digital communication system is more robust than analog system
because it can resist the corruption of signal much better in
presence of channel noise.
2. Implementation of digital hardware in digital communication
system is flexible and permits the use of microprocessor, digital
switching etc.
3. In digital system, it is possible to multiplex several digital signals
that offer more efficient use of available bandwidth.
4. In digital system, it is easy to store large quantities of information.
1.8. Convert the following expression into canonical POS form

Y = (A + B) (B + C) (A + C)
Ans. Given, Y = (A + B) (B + C) (A + C)
=  A  B  CC  B  C  AA  A  C  BB
Canonical form,
Y = ( A  B  C )( A  B  C)( A  B  C)( A  B  C)( A  B  C )( A  B  C )
= ( A  B  C)( A  B  C)( A  B  C )( A  B  C )
1.9. Convert the binary number (1 1 0 1 1 1)2 into Gray code.

Ans.
Binary code 1 1 0 1 1 1
     
Gray code 1 0 1 1 0 0
Hence, Gray code is (101100).
1.10. Convert gray code 1001011 to binary.

Ans.
Gray code 1 0 0 1 0 1 1
Binary code 1 1 1 0 0 1 0
Hence, Binary code is (1110010).
1.11. Convert the decimal number 32.57 in octal, binary,

hexadecimal and Gray. AKTU 2015-16, Marks 02
Ans.
For octal : For hexadecimal :
8 32 0 16 32 0
8 4 4 16 2 2
0 0
32 = (40)8 32 = (20)16
and .57 × 8 = 4.56 4
.56 × 8 = 4.48 4
.48 × 8 = 3.84 3
and .57 × 16 = 9.12 9
.12 × 16 = 1.92 1
.92 × 16 = 14.72 E
Hence, (32.57)10 = (40.443)8
Hence, (32.57)10 = (20.91E)16
For binary : For Gray :

2 32 0
2 16 0
2 8 0
+ + + + + + +
2 4 0 1 0 0 0 0 0 1 0
2 2 0
2 1 1
1 1 0 0 0 0 1 1
0
32 = (100000)2
and .57 = .57 × 2 = 1.14
0.14 × 2 = 0.28
Hence, (32.57)10 = (100000.10)2
Hence, (32.57)10 = (110000.11)Gray
1.12. Simplify the following boolean expression to a minimum

number of literals : (xy + z) + z + xy + wz
Ans.
Given, (xy + z) + z + xy + wz
Using De-Morgan’s theorem
(xy + z) = (x + y) z
(xy + z) + z + xy + wz = (x + y) z + z + xy + wz
= z[1 + (x + y)] + xy + wz = z + xy + wz
= z[1 + w] + xy = z + xy
1.13. Convert the following :

i. (562.13)7 = (?)10
ii. (467.342)8 = (?)10 AKTU 2017-18, Marks 02
Ans.
i. (562.13)7 = 5 × 72 + 6 × 71 + 2 × 70 + 1 × 7–1 + 3 × 7–2
= (289.20)10
ii. (467.342)8 = 4 × 82 + 6 × 81 + 7 × 80 + 3 × 8–1 +4 × 8–2 + 2 × 8–3
= (311.441)10
1.14. Determine the value of base x, if (193)x = (623)8.

Ans. (193)x = (623)8
1 × x2 + 9 × x + 3 × x0 = 6 × 82 + 2 × 81 + 3 × 80
x2 + 9x + 3 = 403
x2 + 9x – 400 = 0
x2 + 25x – 16x – 400 = 0
(x + 25)(x – 16) = 0
x  – 25 ( Base can’t be negative)
 x = 16
1.15. Implement the expression Y = ABC + BD + E using NAND
gate only. AKTU 2017-18, Marks 02
Ans. Y = ABC + BD + E
There are five variables, A, B, C, D and E
Y = Y = ABC  BD  E = ABC · BD · E
C
C
ABC
A
B
BD
Y
D
E
E
Fig. 1.15.1.

2 MSI Devices
(2 Marks Questions)
2.1. Design a half adder using multiplexer.

Ans. For sum, S = A  B = AB  AB

0
1 4×1 Sum = A  B
1 MUX
0
A B
For carry, C = AB
0
0 4×1 Carry = AB
0 MUX
1
A B
Fig. 2.1.1. Half adder using multiplexer.
2.2. Give the expression of full adder output.
Ans. Sum output, S = ABC  ABC  ABC  ABC = A  B  C
Carry output, C0 = AB + AC + BC
2.3. Draw the logic diagram of half subtractor.
Ans.
A
D
B
Bo
Fig. 2.3.1. Half subtractor.

2.4. Explain multiplexer circuit.
Ans. It is a combinational circuit that selects binary information from
one of many lines and directs it to a single output line. The selection
of particular input line is controlled by a set of selection lines. There
2.5. Implement the following function using 8 × 1 MUX,

Y (A, B, C) = m(0, 1, 3, 5, 7).
Ans.
Logic 1
I0
I1
I2
I3 8 × 1 Y
I MUX
4
I5
I6
I7
Logic 0 A B C
Fig. 2.5.1.
2.6. Give the circuit diagram and output equation for 4 × 1 MUX.
Ans.
I0
4 Input I1 4×1 Y
lines I2 MUX Output line
I3
S1 S0
Fig. 2.6.1.
Output equation, Y = I0 S1 S0  I1 S1 S0  I2 S1 S0  I3 S1 S0 .
2.7. Implement the following expression using 4 : 1 MUX.

Y(A, B) = AB  AB
Ans.
Logic 1
I0
I1 4:1
Y
I2 MUX
I3
Logic 0 A B
Fig. 2.7.1.
2.8. What do you mean by priority encoder ?

Ans. It is an encoder circuit that includes the priority function. The
operation of priority encoder is such that, if two or more inputs are
equal to 1 at the same time, the input having the highest priority
will take precedence.
2.9. Which circuit is used at input of communication system ?

Ans. Encoder is used at input of communication system.
2.10. Specify the purpose of valid bit indicator in priority

encoder. AKTU 2016-17, Marks 02
Ans. In priority encoder, valid bit indicator is set to 1, when one or more
inputs are equal to 1. If all inputs are 0, there is no valid input and
valid bit indicator is equal to 0. The other two outputs are not
inspected when valid bit indicator equals to 0 and are specified as
don’t care conditions.
Table 2.10.1. Truth table of a priority encoder.
Inputs Outputs
D0 D1 D2 D3 x y V
0 0 0 0 × × 0
1 0 0 0 0 0 1
× 1 0 0 0 1 1
× × 1 0 1 0 1
× × × 1 1 1 1
2.11. What are the circuits by which all the expressions are
implemented ?
Ans. Multiplexer and decoder, both are used for implementing all
boolean expression.
2.12. Write the difference between decoder and demultiplexer.
Ans.
S. No. Decoder Demultiplexer
1. It has n input line. It has 1 input line.
2. Enable line is present. There is no enable line.
3. There is no select line. Select line is present.
2.13. What is (33)6 + (45)6 AKTU 2017-18, Marks 02

Ans. (33)6 = 3 × 61 + 3 × 60 = (21)10
+ (45)6 = 4 × 61 + 5 × 60 = (29)10
––––––––
(50)10
Now, 6 50
6 8 2
6 1 2
0 1
So, (33)6 + (45)6 = (50)10 = (122)6

3 Sequential Logic
Design
(2 Marks Questions)
3.1. Define sequential circuits.

Ans. Sequential circuits consist of a combinational circuit to which storage
elements are connected to form a feedback path.
3.2. What do you mean by flip-flops ?

Ans. Storage elements that are controlled by a clock transition are
flip-flops. It is a binary storage device capable of storing one bit of
information. Flip-flops are edge triggered devices.
3.3. Give the major differences between latch and flip-flop.

Ans.
1. Sto rage e le me nt that Storage element that are
operates with signal levels. controlled by clock transition.
3.4. Give the function table of SR latch.

Ans.
S R Qn + 1
0 0 Qn (Preset state)
0 1 0
1 0 1
1 1 ×
3.5. Draw Master-Slave flip-flop. AKTU 2015-16, Marks 02

Ans.
Master Slave
J Qn
Q
CLK
K Q
Qn
Fig. 3.5.1. Master-Slave JK flip-flop.
3.6. Express the characteristic equation for the JK flip-flop.

OR
Write the excitation table and characteristic equation of
JK flip-flop. AKTU 2017-18, Marks 02
Ans. JK flip-flop : Qn + 1 = JQn  KQn

Excitation table :
Flip-flop Present Next
inputs state state
J K Qn Qn + 1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
3.7. Define shift registers.

Ans. The binary data in a register can be moved within the register from
one flip-flop to the other or outside it with application of clock
pulses. The registers that allow such data transfers are called shift
registers.
3.8. Give the classification of shift register on the basis of mode

of operation.
Ans.
1. Serial in serial out shift register (SISO)
2. Serial in parallel out shift register (SIPO)
3. Parallel in serial out shift register (PISO)
4. Parallel in parallel out shift register (PIPO)
3.9. Give the application of shift register.

Ans. Shift register are used in many application as :
1. Time delay 2. Serial to parallel data converter
3. Parallel to serial data converter
3.10. What is counter ?

Ans. A counter is a sequential logic circuit capable of counting the number
of clock pulses arriving at its clock input. This count sequence may
be ascending, descending or non sequence. A specified sequence of
states appears at the counter output.
3.11. Define asynchronous counter or ripple counter.

Ans. A binary asynchronous/ripple counter consists of a series connection
of complementing flip-flops, with the output of each flip-flop
connected to the clock input of the next higher-order flip-flop. The
flip-flop holding the least significant bit receives the incoming clock
pulses.
3.12. Define synchronous counter.

Ans. The synchronous counter is one in which all the flip-flops are
triggered simultaneously by the clock pulse, so they are also called
as parallel counters. Synchronous counter may reduce the delay
occurred in asynchronous counter.
3.13. What is modulus of a counter ? AKTU 2018-19, Marks 02

Ans. The number of states passed by the counter before going to its
initial state is called modulus of counter.
3.14. The contents of a four bit register are initially 1011. The
register is shifted six times to the right with serial input
being 101111. What are the contents of the register after
each shift ? AKTU 2016-17, Marks 02
Ans. Given : Serial input = 101111, initial content = 1011.
CLK Din = D3 Q3 = D2 Q2 = D1 Q1 = D0 Q0
initially  1 0 1 1
st
1  1 1 1 0 1
nd
2  1 1 1 1 0
rd
3  1 1 1 1 1
th
4  1 1 1 1 1
th
5  0 0 1 1 1
th
6  1 1 0 1 1
3.15. How many flip-flops are required to design Mod-5 ring

counter and Mod-5 Johnson counter ?
Ans. Mod-5 Ring counter - 5 Flip-flop.
Mod-5 Johnson counter - 3 Flip-flop.
3.16. What are the required numbers of flip-flops in a MOD-16

asynchronous counter, MOD-16 synchronous counter,
MOD-16 Johnson counter ? AKTU 2015-16, Marks 02
Ans. MOD-16 asynchronous counter : 4 flip-flops required.
MOD-16 synchronous counter : 4 flip-flops required.
MOD-16 Johnson counter : 8 flip-flops required.
3.17. What is race around condition ?

AKTU 2017-18, 2018-19; Marks 02
Ans. A race around condition is said to exist in an asynchronous
sequential circuit when two or more binary state variable change
value in response to a change in input variable.
It is eliminated by using master-slave JK flip-flop.

Logic Families and
4 Semiconductor
Memories
(2 Marks Questions)
4.1. What do you mean by bipolar and unipolar logic families ?

Ans. Bipolar logic family : In this logic family, the current flows
because of both electrons and holes being charge carriers.
Unipolar logic family : It includes p-channel metal oxide
semiconductor field-effect transistor (PMOS), n-channel metal
oxide field effect transistor (NMOS) and CMOS. The current flows
due to any one types of carrier.
4.2. What are the uses of ECL family ?
Ans. ECL family is used in very high frequency application where its
speed is superior. It is used in superfast computers and high-
speed special purpose applications.
4.3. What are the difference between CMOS gate and TTL gate ?
Ans. 1. CMOS gate can transmit signal in both direction but TTL and
ECL gates are essentially unidirectional.
2. CMOS consists of n-MOS and p-MOS but TTL and ECL uses
transistors.
4.4. What do you mean by fan-out and fan-in ?
Ans. Fan-out : The fan-out of a logic gate is defined as the maximum
number of standard load that the output of the gate can drive
without impairing its normal operation. Fan-out is also called the
loading factor.
 I I 
Fan-out = Minimum of  OH , OL 
 I IH I IL 
Fan-in : The fan-in of a logic gate refers to the number of inputs
that the gate is designed to handle.
4.5. What do you understand by noise margin ?
Ans. The noise immunity of a logic circuit refers to the circuit’s ability to
tolerate noise voltages at its inputs. A quantitative measure of
noise immunity is called noise margin.
4.6. What is memory ?
Ans. A memory unit is a device to which binary information is transferred
for storage and from which information is retrieved when needed
for processing. A memory is a collection of cells capable of storing a
large quantity of binary information.
4.7. What do you mean by FPGA ?

Ans. FPGA (Field Programmable Gate Array) is high capacity PLD. The
gate array of FPGA has the ability to be programmed for a function
by the user instead of the manufacturer of device.
4.8. Write the steps that must be taken for the purpose of
transferring a new word to be stored into memory.
Ans. The steps that must be taken for the purpose of transferring a
new word to be stored into memory are as follows :
1. Apply the binary address of the desired word to the address lines.
2. Apply the data bits that must be stored in memory to the data
input lines.
3. Activate the write input.
4.9. What do you mean by CPLD ?
Ans. Complex-programmable logic device (CPLD) contains a bunch of
PLD blocks whose input and output are connected together by a
global interconnection matrix.
I/O I/O
PLD Global PLD
I/O interconnection
matrix
PLD PLD
I/O
Fig. 4.9.1. CPLD.
4.10. How many address lines and data I/O lines are required
for a 16K × 12 memory ? AKTU 2015-16, Marks 02
Ans. 16K × 12 = 24 × 210 × 12
Address lines = 14, Data lines = 12
4.11. Define memory read and write operation.
Ans. The process of storing new information into memory is referred
to as a memory write operation and the process of fetching the
stored information from the memory is referred to as a memory
read operation.
4.12. What is ROM ?
Ans. Read only memory is a type of memory used in digital system
which can perform only the read operation. This means that
suitable binary information is already stored inside memory and
can be retrieved or read anytime. However, that information
cannot be altered by writing. ROM is non-volatile memory.
4.13. Define the random access memory (RAM).
Ans. RAM can perform both read and write operations, the time it takes
to transfer information to or from any desired random location is
always the same, hence, the name random access memory. RAM is
volatile memory.

5 D/A and A/D Converter

(2 Marks Questions)
5.1. Define D/A conversion.

Ans. It is the process of taking a value represented in digital code and
converting it into a voltage or current which is proportional to
digital value.
5.2. What are the characteristics of D/A converter ?

Ans.
1. Resolution 2. Linearity
3. Accuracy 4. Settling time
5. Temperature sensitivity
5.3. What is the disadvantage of DAC ?

Ans. The disadvantage of binary weighted type DAC is the wide range of
resistor value required. It may be observe that for better resolution,
the input binary word length has to be increased. Thus, as the
number of bit increases, the range of resistance value increases.
5.4. Draw the circuit diagram of A/D and D/A converter.

Ans.
Anti Band Analog to
Sensor or Analog limited Sample Discrete Discrete
aliasing digital
Transducer analog & hold analog digital
signal filter converter Computer
signal
Plant
or digital
signal
Staircase signal Digital binary signal processor
Analog signal Smoothing D-A
filter converter
Fig. 5.4.1.
5.5. Name the different types of ADCs used.

Ans.
1. Flash (comparator) type converter
2. Counter type converter
3. Tracking or servo type converter
4. Successive approximation type comparator
5.6. Write the application in which integrating type converter

is used ?
Ans.
1. Digital meter
2. Panel meter
3. Monitoring systems where the conversion accuracy is critical.
5.7. Draw the functional diagram of ADC and define its two
additional control lines.
Ans.
Control lines :
1. The START input to tell the ADC when to start the conversion.
2. The EOC output to announce when the conversion is complete.
Functional diagram :
Start EOC
d1 MSB
d2
Analog Digital
input ADC output
dn
VR (Reference)
Fig. 5.7.1
5.8. The basic step of 9-bit DAC is 10.3 mV. If 000000000 represents
0 V, what output is produced if the input is 101101111 ?
Ans. The output voltage for input 101101111 is
10.3 × 10–3 × (1 × 28 + 0 × 27 + 1 × 26 + 1 × 25 + 0 × 24 + 1 × 23 + 1 × 22
+ 1 × 21 + 1 × 20) = 10.3 × 367 × 10–3 = 3.78 V
5.9. The basic step of a 8-bit DAC is 20 mV. If 00000000 represents

0 V, what is represented by the input 10110111 ?
Ans. The output voltage for input 10110111 is given by
20 mV (1 × 27 + 0 × 26 + 1 × 25 + 1 × 24 + 0 × 23
+ 1 × 22 + 1 × 21 + 1 ×20)
= 20 mV (128 + 32 + 16 + 4 + 2 + 1)
= 20 × 183 = 3660 mV = 3.66 V
5.10. Draw the circuit diagram of flash type A/D converter.

Ans.
Analog +VR (Reference voltage)
input Va
+ X7
7V –
8 R X6
R +
3 –
4 VR
R + X5
5
8 VR –
8-line Y 2 (MSB)
R X4
+ to Y1
1 –
2V R 3-line Y 0(LSB)
+ X3 priority
3 R
8 VR – encoder
R + X2
1
4V R –
R + X1
1V –
8 R
R + X0
0V –
Fig. 5.10.1.
5.11. For a dual slope ADC, t1 is 83.33 ms and the reference

voltage is 100 mV. Calculate t2 if Vi is
i. 100 mV and
ii. 200 mV.
Ans. Given : t1 = 83.33 ms, VR = 100 mV
We know that,
t2
Vi = VR × ...(5.11.1)
t1
Vi
 t2 = t
VR 1
i. Vi = 100 mV
100
t2 =  83.33 = 83.33 ms
100
ii. Vi = 200 mV
200
t2 =  83.33 = 166.66 ms
100

SP–1 B (EC-Sem-3) Digital Logic Design
B.Tech.
(SEM. III) ODD SEMESTER THEORY
EXAMINATION, 2014-15
SWITCHING THEORY AND LOGIC DESIGN
Time : 2 Hours Max. Marks : 50
Notes : 1. Attempt all questions.

2. All questions carry equal marks.
1. Attempt any four parts of the following : (3.5 × 4 = 14)

a. Convert the following numbers into desired base :
i. (A6BF5)16 = (?)2 = (?)Gray
ii. (17 – 135) using 2’s complement
b. Simplify the following boolean expression to a minimum

number of literals.
ii. ( x y + z) + z + xy + wz
c. Simplify the following expression into product of sum

(POS) form
d. Use Quine-McCluskey (QM) method to solve the following

function :
F (A, B, C, D) = m (5, 7, 8, 9, 10, 11, 14, 15)
e. Simplify the boolean function Y together with don’t care

NAND gate circuit.
f. For the Hamming code 1001101001 received at the receiver

end, correct this code for error if any.
2. Attempt any two parts of the following : (6 × 2 = 12)

a. Design a BCD to 7 segment decoder. Assume positive logic,
minimize the function.
SP–2 B (EC-Sem-3) Solved Paper (2014-15)
b. Design the following boolean function us ing 4 × 1

multiplexer.
F(A, B, C, D) = m(0, 1, 3, 4, 8, 9, 15)
c. Design and explain the logic and circuit of 4-bit magnitude

comparator.
a. Distinguish between synchronous and asynchronous
digital sequential circuit. Design modulo-5 counter.
b. Explain race around condition and its remedy in brief.

Realise T flip-flop to SR flip-flop.
c. Write down the classification of semiconductor memories.

Draw and explain the programmable logic array (PLA).

a. Explain hazard and its types. Define critical race and
non- critical race. Also explain the elimination of hazards
in asynchronous circuits.
b. With the help of diagram, explain the operation of universal

shift register.
c. An asynchronous sequential circuit described by the

following excitation and output functions.
Y = X1 X2 + (X1 + X2)Y and Z = Y.
where X1 and X2 = input variables
Y = excitation function
Z = output function
i. Draw the logic diagram of the circuit.
ii. Derive transition table.
iii. Output map and obtain a flow table.

SOLUTION OF PAPER (2014-15)
Notes : 1. Attempt all questions.

2. All questions carry equal marks.
1. Attempt any four parts of the following : (3.5 × 4 = 14)

a. Convert the following numbers into desired base :
i. (A6BF5)16 = (?)2 = (?)Gray
ii. (17 – 135) using 2’s complement
Ans.
i. (A6BF5)16 =(10100110101111110101)2
= (11110101111000001111)Gray
ii. (17 – 135)
17 in binary form = (10001)2
135 in binary form = (10000111)2
2's complement of 135 = 01111001
Now, adding 17 in binary form = + 00010001
10001010
As there is no carry, the answer is negative and is in the 2’s
complement form. The answer is,
– (2’s complement of 10001010)
= – (01110110)2
Thus the answer is – (01110110)2, i.e., (–118)10.
b. Simplify the following boolean expression to a minimum

number of literals.
ii. ( x y + z) + z + xy + wz
Ans.
i. AC + ABC + AC + AB :
Let Y = AC  AC  AB  ABC
= C ( A  A)  A ( B  BC )
= C  A( B  C) [ A + A = 1]
= C  AC  AB
[ C  AC  (C  A) (C  C )]
= C  A  AB
= C  A(1  B)
= AC
ii. ( x y + z) + z + xy + wz
Let Y=(x y + z) + z + xy + wz
= x y + z + xy + wz
= x y + xy + z (1 + w)
= x y + xy + z = x  y + z [ 1 + w = 1]
c. Simplify the following expression into product of sum

(POS) form
Ans.
1. Let Y = ABC  ABD  BCD
= ABC ( D  D)  AB (C  C) D  ( A  A) BCD
= ABCD  ABCD  ABCD  ABCD  ABCD  ABCD
Y = m(7, 9, 11, 12, 13, 15)
2. Now for POS form we will take complement function,
Y = M(0, 1, 2, 3, 4, 5, 6, 8, 10, 14)
3. Minimization through K-map is shown in Fig. 1.
CD
C+D C+D C+D C+D
AB
A+B 0 0 0 0
0 1 3 2
A+B 0 0 0
4 5 7 6
A+B 0
12 13 15 14
A+B 0 8 9 11
0 10
Fig. 1.
Y = (A + B) (A + C)( C + D) (B + D)
1. Let, Y = ACD  CD  AB  ABCD
= ABCD  ABCD  ABCD  ABCD  ABCD
 ABCD  ABCD  ABCD  ABCD
Y = m(1, 5, 8, 9, 10, 11, 13, 14, 15)

2. Now for POS form, we have to take complement function,
Y =  M(0, 2, 3, 4, 6, 7, 12)
3. Minimization through K-map is shown in Fig. 2.
CD
AB C+D C+D C+D C+D
A+B 0 0 0
0 1 3 2
0 0 0
A+B
4 5 7 6
A+B 0
12 13 15 14
A+B
8 9 11 10
Fig. 2.
Y = (A + D) (A + C ) ( B + C + D)
d. Use Quine-McCluskey (QM) method to solve the following

function :
F (A, B, C, D) = m (5, 7, 8, 9, 10, 11, 14, 15)
Ans.
1. F (A, B, C, D) = m(5, 7, 8, 9, 10, 11, 14, 15)
1. m8 1000 8, 9 100_ 8, 9, 10, 11 10_ _
2. m5 0101 8, 10 1 0 _ 0 10, 11, 14, 15 1 _ 1_
m9 1001 5, 7 01_1
m10 1010 9, 11 10_1
3. m7 0111 10, 11 101_
m11 1011 10, 14 1_10
m14 1110 7, 15 _111
4. m15 1111 11, 15 1_11
14, 15 111_
Now, we prepare a prime implicant chart to determine essential
prime implicant is as follows :
   
Minterms Prime implicants m5 m7 m8 m9 m10 m11 m14 m15
ABD  5, 7  
BCD  7, 15  
AB  8, 9, 10, 11    
AC  10, 11, 14, 15    

Therefore, F(A, B, C, D) = AC + AB  ABD
e. Simplify the boolean function Y together with don’t care

NAND gate circuit.
Ans.
1. Given, Y = BD  BCD  ABCD
= ( A  A) B (C  C ) D  ( A  A) BCD  ABCD
= ABCD  ABCD  ABCD  ABCD  ABCD  ABCD  ABCD
Y = m(5, 6, 7, 10, 13, 14, 15)
2. As there is not given any don’t care condition so K-map as shown in
Fig. 3.
CD 00 01 11 10
AB
00 0 1 3 2
01 4 15 1 7 1 6
1 1 1
11
12 13 15 14
10 1
8 9 11 10
Fig. 3.
Y = BD + BC + ACD
3. NAND gate implementation :
B BD
D BD + BC
(BD + BC)
B BC
C
Y
A AC AC
C
D
D ACD
Fig. 4.
f. For the Hamming code 1001101001 received at the receiver

end, correct this code for error if any.
Ans. This question is out of syllabus from session 2019-20.
a. Design a BCD to 7 segment decoder. Assume positive logic,
minimize the function.
Ans.
1. The truth table for a BCD to 7 segment decoder is as given as
follows :
Digit BCD input 7-segment
A B C D a b c d e f g
0 0 0 0 0 1 1 1 1 1 1 0
1 0 0 0 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1
5 0 1 0 1 1 0 1 1 0 1 1
6 0 1 1 0 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 1 0 1 1
2. The unused BCD codes are 1010, 1011, 1100, 1101, 1110, and 1111.
So place × (don’t care condition) for these corresponding cells.
CD For a CD For b
AB 00 01 11 10 AB 00 01 11 10
1 1 1 1 1 1 1
00 0 1 3 2 00 0 1 3 2
01 1 1 1 01 1 1
4 5 7 6 4 5 7 6
11 × × × 11
× 12 13 15 14
× × × ×
12 13 15 14
10 1 1 × × 1 1 × ×
10
8 9 11 10 8 9 11 10
a = A + C + BD+ BD b = B + CD+ CD
CD For c CD For d
AB 00 01 11 10 00 01 11 10
AB
1 1 1
1 1 1 00
00 0 1 3 2 0 1 3 2
01 01 1 1
1 4 15 1 7 1 6 4 5 7 6
11 × × × × 11 × × × ×
12 13 15 14 12 13 15 14
10 1 × × 10 1 1 × ×
8 9 11 10 8 9 11 10
c=B+C+D d = BD + CD + BCD + BC + A
For e CD For f
CD
00 01 11 10 00 01 11 10
AB AB
1 1 10
00 0 1 3 2 00 1 3 2
01 4 5 7 1 6 01 14 15 7 1 6
11 × × × × 11 × × × ×
12 13 15 14 12 13 15 14
10 1 × × 10 1 1 × ×
8 9 11 10 8 9 11 10
e=BD+CD f = A + CD+ B C + B D
CD For g
00 01 11 10
AB
1 1
00 0 1 3 2
01 1 1 1
4 5 7 6
11 × × × ×
12 13 15 14
10 1 1 × ×
8 9 11 10
g = A + B C+ B C + C D
Fig. 5.
3. Fig. 6 shows the logic diagram of BCD to 7 segment display decoder.
A B C D
BD
a
BD
CD
b
CD
CD
BCD
d
BC e
BC
f
BD
g
Fig. 6.
b. Design the following boolean function us ing 4 × 1

multiplexer.
F(A, B, C, D) = m(0, 1, 3, 4, 8, 9, 15)
Ans.
1. Given, F (A, B, C, D) = m(0, 1, 3, 4, 8, 9, 15)
2. We have to design it using 4 : 1 multiplexer, so we can use two
variable (A, B) for select lines and implementation table is as follows :
I0 I1 I2 I3
CD 0 4 8 12
CD 1 5 9 13
CD 2 6 10 14
CD 3 7 11 15
C+D CD C CD
3. Now, I0 = CD  CD  CD  C  D
I1 = CD
I2 = CD  CD  C
I3 = CD
4. Logic diagram is shown in Fig. 7.
C
I0
D
I1 4 × 1
F (A, B, C, D)
MUX
I2
I3
A B
Fig. 7.
c. Design and explain the logic and circuit of 4-bit magnitude

comparator.
Ans.
A = A3 A2 A1 A0
B = B3 B2 B1 B0
2. The two numbers are equal if all pairs of significant digits are
equal, i.e., if A3 = B3, A2 = B2, A1 = B1 and A0 = B0. Equality relation
is generated by EX-NOR gate.
xi = Ai Bi  Ai Bi ; i = 0, 1, 2, 3.
xi = 1, if A = B
xi = 0, otherwise,
4. The logical implementation is shown in Fig. 8.
A3
x3
B3
A2
x2
B2
(A < B)
A1
x1
B1
A0
x0
(A > B)
B0
(A = B)
Fig. 8. 4-bit magnitude comparator using logic gates.

a. Distinguish between synchronous and asynchronous
digital sequential circuit. Design modulo-5 counter.
Ans.
A. Difference :
S. No. Synchronous sequential Asynchronous sequential
circuit circuit
1. In synchro no us circuit, In asynchronous circuit, memory
memory elements are clocked elements are either unclocked
flip-flops. flip-flop or time delay elements.
2. In synchronous circuit, the In synchronous circuit, change in
change in input signal can input signal can affect memory
affect memory element upon element at any instant of time
activation of clock signal.
3. The maximum operating Because of absence of clock,
speed of clock depends on time asynchronous circuit can operate
involved. faster than synchronous circuit.
4. Easier to design. More difficult to design.

B. Modulo - 5 counter :
Step 1 : Here 5 indicates total number of states, the count sequences
are from 0 to 4.
Step 2 : The required number of flip-flops are
2n  N
2n  5
n=3
Step 3 : Desired sequence and state diagram :
101 110 111 Unwanted
Desired sequence states
QC QB QA
000
0 0 0
0 0 1
100 001
0 1 0
0 1 1
1 0 0 011 010
Fig. 9. State diagram.
Step 4 : Excitation table for JK flip-flop :
Present states Qn Next state Qn + 1 J K
0 0 0 ×
0 1 1 ×
1 0 × 1
1 1 × 0
Step 5 : State table :

Present state Next state Flip-flop inputs
QC QB QA QC + 1 QB + 1 QA +1 JC KC JB KB JA KA
0 0 0 0 0 1 0 × 0 × 1 ×
0 0 1 0 1 0 0 × 1 × × 1
0 1 0 0 1 1 0 × × 0 1 ×
0 1 1 1 0 0 1 × × 1 × 1
1 0 0 0 0 0 × 1 0 × 0 ×
1 0 1 0 0 0 × 1 0 × × 1
1 1 0 0 0 0 × 1 × 1 0 ×
1 1 1 0 0 0 × 1 × 1 × 1
Step 6 : K-map simplification :
For J C For KC
QBQA QBQA
QC QC
00 01 11 10 00 01 11 10
0 0 0
0 1
13 0 2
0 × 0
× 1
× 3
× 2
1 × × × × 1 1 1 1 1
4 5 7 6 4 5 7 6
JC = QB QA KC = 1
For J B For KB
QBQA QBQA
QC QC
00 01 11 10 00 01 11 10
0 00 11 ×3 ×2 0 ×0 × 1 13 02
1 0 0 × × 1 × × 1 1
4 5 7 6 4 5 7 6
JB = QC QA KB = QC + QA QC
QBQA For J A QBQA For K A

QC QC
00 01 11 10 00 01 11 10
0 1 0 × 1 × 3 1 2 0 × 0 1 1 1 3 × 2
1 0 × × 0 1 × 4 1 5 1 7 × 6
4 5 7 6
JA = Q C KA = 1
Fig. 10. K-maps and simplifications.
Step 7: The logic diagram of mod-5 counter is shown in Fig. 11.
JA QA JB Q B JC QC
A B C
KA QA KB QB KC QC
CLK Logic 1 Logic 1
Fig. 11. Logic diagram of mod-5 synchronous counter.
b. Explain race around condition and its remedy in brief.

Realise T flip-flop to SR flip-flop.
Ans.
A. Race around condition :
1. A race around condition is said to exist in an asynchronous
sequential circuit when two or more binary state variables change
value in response to a change in an input variable.
2. When unequal delays are encountered, a race condition may cause
the state variables to change in an unpredictable manner.
3. It occurs in JK flip-flop when the J = K = 1 and propagation delay of
the flip-flop is less than pulse width of clock.
i.e., J= K=1
and tpdFF < tPW
B. Elimination of race around condition using master-slave
JK flip-flop :
1. The master-slave combination consists of clocked JK flip-flop as a
master and clocked SR flip-flop as a slave.
2. In this, master is positive level triggered but due to the presence of
the inverter in the clock line, the slave will be at negative level.
3. Hence, when clock (CLK) = 1, the master is active and the slave is
inactive whereas when clock (CLK) = 0, the slave is active and the
master is inactive.
Master Slave
J Y S
Q
CLK
K Q
Y R
Fig. 12. Master-slave JK filp-flop.

C. T flip-flop to SR flip-flop :
Step 1 : Truth table for SR flip flop :
S R Qn + 1
0 0 Qn
0 1 0
1 0 1
1 1 x
Step 2 : Excitation table for T flip-flop :
Qn Qn + 1 T
0 0 0
0 1 1
1 0 1
1 1 0
Step 3 : Conversion table :
Inputs Present state Next state Flip-flop input

S R Qn Qn+1 T
0 0 0 0 0
0 0 1 1 0
0 1 0 0 0
0 1 1 0 1
1 0 0 1 1
1 0 1 1 0
1 1 0 × ×
1 1 1 × ×
RQn
S 00 01 11 10
0 1
0 1 3 2
1 1 × ×
4 5 7 6
T = RQn + SQn
R T Q
S T
Flip-flop
Q
CP
Fig. 13.
c. Write down the classification of semiconductor memories.

Draw and explain the programmable logic array (PLA).
Ans.
A. Classification of semiconductor memories :
Fig. 14 shows an overview of semiconductor memory types.
Semiconductor memories
Read/write memory Read only memory

or random access memory (RAM) (ROM)
Dynamic RAM Static • Mask (Fuse) ROM

(DRAM) RAM • Programmable ROM (PROM)
(SRAM) • Erasable PROM (EPROM)
• Electrically Erasable PROM
• Flash memory
• Ferroelectric RAM (FRAM)
Fig. 14. Classification of semiconductor memories.
B. Programmable logic array (PLA) :
structures. The PLA provides the designer with a systematic and
regular way of implementing output functions of n variable in sum
of product form.
more compact in nature. Any of the logical function can be expressed
in terms of SOP or POS.
3. PLA can be implemented in several forms, i.e., NOR–NOR,
4. The structure of PLA is shown in Fig. 15, and its internal logic with
three inputs and two outputs is shown in Fig. 16.
Fig. 16, are
F2 = ( AC  BC )
· AND
·
m input · · OR
· ·
·· ·
n output lines
Fig. 15. PLA structure.
6. The programming table that specifies the PLA of Fig. 16 is listed in the
table 1. The PLA programming table consists of three sections.
A
C
×× 1 ×
× × 2 × × AC
× × 3 × BC
×× × 4 ×
C C B B A A × 0
× 1
F1
F2
Fig. 16. PLA with three inputs, four product terms, and two outputs.
7. The first section lists the product term numerically. The second
section specifies the required paths between input and AND gates.
The third section specifies the path between the AND and OR
gates.
8. For each output variable, we may have a T (true) or C
(complement) for programming the XOR gate.
9. For each product term, the inputs are marked with 1, 0
or — (dash).
10. If the variable in the product term appears in the form in which it
is true, the corresponding input variable is marked with a 1. If it
appears complemented, the corresponding input variable is marked
with a 0. If the variable is absent from the product term, it is
marked with a dash.
Table 1. PLA programming
Input Output
AB 1 1 0 — 1 —
AC 2 1 — 1 1 1
BC 3 — 1 1 — 1
ABC 4 0 1 0 1 —
11. The size of the PLA is specified by the number of inputs, the number
of product terms, and the number of outputs. A typical integrated
circuit PLA may have 16 inputs, 48 product terms and eight outputs.
12. For n inputs, k product terms, and m outputs, the internal logic of
the PLA consists of n buffer-inverter gates, k AND gates, m OR
gates, and m XOR gates.

a. Explain hazard and its types. Define critical race and
non- critical race. Also explain the elimination of hazards
in asynchronous circuits.
Ans.
A. Hazards :
1. Hazards are unwanted switching transient that may appear at the
output of a circuit because different paths exhibit different
propagation delays.
2. Hazards occur in combinational circuits, where they may cause a
temporary false-output value. When this condition occurs in
asynchronous sequential circuits, it may result in a transition to a
wrong stable state.
B. Types of hazards :
i. Static-1 hazard : In response to an input change and for some
combination of propagation delays, a logic circuit may go to 0, when
it should remain constant 1, this transient is called static-1 hazard.
ii. Static-0 hazard : In response to an input change and for some
combination of propagation delays, a logic circuit may go to 1 when it
should remain constant at 0, this transient is called static-0 hazard.
iii. Dynamic hazard : When the output of logic circuit is changed
from 0 to 1 to 0 or 1 to 0 to 1. These two outputs may change more
number of times, this transient is called dynamic hazard.
1 1 Momentarily 1 1
1 changes
Momentarily
changes
0 0 0 0 0
(a) Static-1 hazard ( b) Static-0 hazard (c) Dynamic hazard
Fig. 17.
iv. Essential hazard :
1. The static and dynamic hazards can occur in combinational as well
as sequential logic circuits. Essential hazards occur in sequential
circuits only.
2. Let there be more than one path from the input to the output of a
logic circuit as shown in Fig. 18.
3. We find that there are two output paths that contain combinational
logic gates and sequential logic circuit.
4. It may happen that certain paths may produce more delay than the
other.
Path 1 1 2
Combinational Sequential
logic circuit logic circuit Y1
3 4 5
Combinational Combinational Sequential
Y2
logic circuit logic circuit logic circuit
Path 2
Fig. 18.
C. Elimination of hazards :
1. Static and dynamic hazard can be prevented by adding extra gates
in the circuit as the redundant term. This is done by grouping the
two adjacent 1’s or 0’s which are responsible for hazard.
2. Fig. 19 shows the logic circuit with hazard problem.
x1
x2
F (x1, x2, x3) = x2x3 + x1x2
x3
Fig. 19.
3. The K-map simplification for F is shown in Fig. 20.
x2 x3
x1 00 01 11 10
0 1
0 1 3 2
1 1 1 1
4 5 7 6
Two adjacent 1’s responsible for the static-1 hazard.

Fig. 20.
4. Expression for output F is given by
F = x2 x3  x1 x2
5. Then we group the two 1’s to eliminate static-1 hazard. The modified
K-map is shown in Fig. 21.
x2 x3
x1 00 01 11 10
0 1
0 1 3 2
1 1 1 1
4 5 7 6
new pair of 1’s (x1 x3) formed

to eliminate static-1 hazard.
Fig. 21.
6. The new expression for output will be

F = x2 x3  x1 x2  x1 x3
new term
7. So, the hazard free circuit is shown in Fig. 22. Note that static-1
hazard has been eliminated due to the additional AND gate.
x1 x1x2
x2
x3 F = x1x2 + x2x3 + x1x3

x2x3
x1x3
Additional gate used to make the circuit hazard free.

Fig. 22.
D. Critical race and non-critical race :
1. If the final stable state that the circuit reaches does not depend on
the order in which the state variable changes, the race is called a
non-critical race.
2. If it is possible to end up in two or more different stable states,
depending on the order in which the state variable change, then it
is a critical race. For proper operation, critical race must be avoided.
Non-critical race :
x x
y1 y2 0 1 y 1y 2 0 1
00 00 11 00 00 11
01 11 01 01
11 11 11 01
10 11 10 11
(a) Possible transitions (b) Possible transitions

00 11 00 11  01
00 01  11 00 01
00 10  11 00 10  11  01
Fig. 23.
Critical race :
x x
0 1 0 1
y1y2 y1y2
00 00 11 00 00 11
01 01 01 11
11 11 11 11
10 10 10 10
( a) Possible transitions (b) Possible transitions

00 11 00 11
00 01 00 01  11
00 10 00 10
Fig. 24.
b. With the help of diagram, explain the operation of universal

shift register.
Ans.
1. A shift register that can shift the data in both the directions (shift
right or left) as well as load it parallely, it is called as a universal
shift register.
ii. Left shifting.
iii. Right shifting.
Fig. 25. It consists of four D flip-flop and four 4 : 1 multiplexers.
4. The four multiplexers have two common select lines S1 and S0.
Input I0 in each multiplexer is selected when S1S0 = 00, input I1 is
selected when S1S0 = 01 and so on.
5. The selection inputs (S1S0) control the mode of operation of the
register according to the function table shown in table 2.
Parallel output
A3 A2 A1 A0
FF4 Q FF 3 Q FF2 Q FF 1 Q
Clear
D D D D
CLK
S1 4×1 MUX 4×1 MUX 4×1 MUX 4×1 MUX

Serial
input
Serial
for shift
I3 I2 I1 I0 input
right
for shift
Parallel inputs
left
Fig. 25. Block diagram of 4-bit universal shift register.
Table 2. Function table
S1 S0 Function
0 0 Hold
0 1 Shift right
1 0 Shift left
1 1 Load
Operation :
1. When S1S0 = 00, the present value of the register is applied to the D
inputs of the flip-flops. This condition forms a path from the output of
each flip-flop to the binary value input of the same flip-flop.
2. The next clock edge transfers into each flip-flop the binary value it
held previously and no change of state occurs.
inputs of the flip-flops. This causes a shift right operation, with the
serial input transferred in flip-flop FF4.
input going into flip-flop FF1. In this case, Input I2 of each multiplexer
is connected to the output of each flip-flop. The data bit is shifted to left
side for every clock.
5. When S1S0 = 11, the binary information on the parallel input lines is
transferred into the register simultaneously during the next clock edge.
c. An asynchronous sequential circuit described by the

following excitation and output functions.
Y = X1 X2 + (X1 + X2)Y and Z = Y.
where X1 and X2 = input variables
Y = excitation function
Z = output function
ii. Derive transition table.
iii. Output map and obtain a flow table.
Ans.
State table :
Present state Next state Stable state Output Z
X1 X2 Y X1 X2 Y Yes/No
0 0 0 0 0 0 Yes 0
0 0 1 0 0 0 No 0
0 1 0 0 1 0 Yes 0
0 1 1 0 1 1 Yes 1
1 0 0 1 0 0 Yes 0
1 0 1 1 0 1 Yes 1
1 1 0 1 1 1 No 1
1 1 1 1 1 1 Yes 1
i. Logic diagram :
X1
X2
Y=Z
Fig. 26.
ii. Transition table :
X1X2 Unstable state
00 01 11 10
Y Stable state
0 0 0 1 0
1 0 1 1 1
iii. Output map :

X1X2
00 01 11 10
Y
0 0 0 1 0
1 1 1 1 1
Flow table : Let S0 = 0 and S1 = 1

X 1X 2
Y 00 01 11 10
S0 S0/0 S0/0 S1/1 S0/0
S1 S0/0 S1/1 S1/1 S1/1

B.Tech.
SECTION – A
1. Attempt all parts. All parts carry equal marks. Write answer of
each part in short : (2 × 10 = 20)
a. Write the difference between decoder and demultiplexer.
b. Perform the subtraction using 2’s complement 46 – 23.
c. Realize an EX-OR gate using NAND gates only.
d. How many address lines and data I/O lines are required
for a 16K × 12 memory ?
e. Simplify the following boolean expression to a minimum

f. Differentiate between asynchronous and synchronous

sequential circuits.
g. What are the required number of flip-flops in a MOD-16

MOD-16 Johnson counter ?
h. Design a half adder using multiplexer.
i. Convert the decimal number 32.57 in octal, binary,

hexadecimal and Gray.
j. Draw Master-Slave flip-flop.
SECTION – B
Attempt any five questions from this section : (10 × 5 = 50)

2. Design a 4-bit magnitude comparator using one bit
comparator modules.
3. Prepare Hamming code for the message “01001001010”

assuming even parity. Also explain error detection and
correction capabilities at the receiver by assuming an error
in any one of the received bits.
4. Us ing a decoder and external gates , des ign the

boolean functions :
F1 = xyz + zx, F 2 = xyz + zy, F3 = xyz + xy
5. Design a 3-bit binary to Gray code converter using PLA.
6. Draw and explain 4-bit universal shift register.
7. Describe the hazards in digital circuits. How are these

removed ?
8. What do you understand by state reduction ? Reduce the

following state diagram.
0/0
a
0/0
1/0
0/0 0/0
0/0
b c
1/0
1/0
g d e
0/0
1/1
1/1
0/0 1/1
f
1/1
Fig. 1.
9. Derive the state table and state diagram for the sequential
circuit shown in Fig. 2.
A x
JA QA JB QB B
A B
A
KA QA KB QB B
x x
CP
y
B
Fig. 2.
SECTION – C
Attempt any two questions from this section. (15 × 2 = 30)

10. Minimize the following using Quine-McCluskey method :
F(W, X, Y, Z) = m(0, 3, 5, 6, 7, 10, 12, 13) +d (2, 9, 15)
11. a. Design a 3-bit asynchronous up-down counter using

T flip-flop.
b. Design a full adder using two half adders.
12. Design the clocked sequential circuit for the following state
diagram using JK flip-flops.
0
1 00 1
1 01 11 0
0 10 1
0
Fig. 3.

SECTION – A
a. Write the difference between decoder and demultiplexer.
Ans.
S. No. Decoder Demultiplexer
1. It has n input line. It has 1 input line.
2. Enable line is present. There is no enable line.
3. There is no select line. Select line is present.
b. Perform the subtraction using 2’s complement 46 – 23.

Ans. (46)10  (00101110)2
(– 23)10  2’s complement of 23
= 11101001
46 = 0 0 1 0 1 1 1 0
– 23 = + 1 1 1 0 1 0 0 1
Neglect carry 1 00010111
46 – 23 = (0 0 0 1 0 1 1 1)2 = 23
c. Realize an EX-OR gate using NAND gates only.

Ans. EX-OR gate using NAND gates :
A.AB
A AB AB
B
B.AB
Fig. 1.
d. How many address lines and data I/O lines are required
for a 16K × 12 memory ?
Ans. 16K × 12 = 24 × 210 × 12
Address lines = 14, Data lines = 12
e. Simplify the following boolean expression to a minimum

Ans. Given, (xy + z) + z + xy + wz
Using De-Morgan’s theorem
(xy + z) = (x + y) z
(xy + z) + z + xy + wz = (x + y) z + z + xy + wz
= z[1 + (x + y)] + xy + wz = z + xy + wz
= z[1 + w] + xy = z + xy
f. Differentiate between asynchronous and synchronous

sequential circuits.
Ans. Difference :
S. No. Synchronous sequential Asynchronous sequential
circuit circuit
1. In synchro no us circuit, In asynchronous circuit, memory
memory elements are clocked elements are either unclocked
flip-flops. flip-flop or time delay elements.
2. In synchronous circuit, the In synchronous circuit, change in

change in input signal can input signal can affect memory
affect memory element upon element at any instant of time
activation of clock signal.
3. The maximum operating Because of absence of clock,
speed of clock depends on time asynchronous circuit can operate
involved. faster than synchronous circuit.
4. Easier to design. More difficult to design.
g. What are the required number of flip-flops in a MOD-16

MOD-16 Johnson counter ?
Ans. MOD-16 asynchronous counter : 4 flip-flops required.
MOD-16 synchronous counter : 4 flip-flops required.
MOD-16 Johnson counter : 8 flip-flops required.
h. Design a half adder using multiplexer.

Ans. For sum, S = A  B = AB  AB
0
1 4×1 Sum = A  B
1 MUX
0
A B
For carry, C = AB
0
0 4×1 Carry = AB
0 MUX
1
A B
Fig. 2. Half adder using multiplexer.
i. Convert the decimal number 32.57 in octal, binary,

hexadecimal and Gray.
Ans.
For octal : For hexadecimal :
8 32 0 16 32 0
8 4 4 16 2 2
0 0
32 = (40)8 32 = (20)16
and .57 × 8 = 4.56 4
.56 × 8 = 4.48 4
.48 × 8 = 3.84 3
and .57 × 16 = 9.12 9
.12 × 16 = 1.92 1
.92 × 16 = 14.72 E
Hence, (32.57)10 = (40.443)8
Hence, (32.57)10 = (20.91E)16
For binary : For Gray :
2 32 0
2 16 0
2 8 0
+ + + + + + +
2 4 0 1 0 0 0 0 0 1 0
2 2 0
2 1 1
1 1 0 0 0 0 1 1
0
32 = (100000)2
and .57 = .57 × 2 = 1.14
0.14 × 2 = 0.28
Hence, (32.57)10 = (100000.10)2
Hence, (32.57)10 = (110000.11)Gray
j. Draw Master-Slave flip-flop.

Ans.
Master Slave
J Qn
Q
CLK
K Q
Qn
Fig. 3. Master-Slave JK flip-flop.

SECTION – B
Attempt any five questions from this section : (10 × 5 = 50)

2. Design a 4-bit magnitude comparator using one bit
comparator modules.
Ans.
A = A3 A2 A1 A0
B = B3 B2 B1 B0
xi = Ai Bi  Ai Bi ; i = 0, 1, 2, 3.
xi = 1, if A = B
xi = 0, otherwise,
A3
x3
B3
A2
x2
B2
(A < B)
A1
x1
B1
A0
x0
(A > B)
B0
(A = B)
3. Prepare Hamming code for the message “01001001010”

assuming even parity. Also explain error detection and
correction capabilities at the receiver by assuming an error
in any one of the received bits.
4. Us ing a decoder and external gates , des ign the

boolean functions :
F1 = xyz + zx, F 2 = xyz + zy, F3 = xyz + xy
Ans. Let us consider 3 to 8 line decoder. The implementation of the
given three functions using 3 to 8 line decoder and a few OR gates
are shown as follows :
F1 = xyz + xz = xyz + xz(y + y)
= xyz + xyz + xyz =  m(2, 7, 5)
F2 = xyz + yz = xyz + (x + x)yz
= xyz + xyz + xyz =  m(2, 4, 6)
F3 = xyz + xy = xyz + xy(z + z)
= xyz + xyz + xyz= m(0, 6, 7)
Y0
Y1
x
Y2
F1
3:8 Y3
y
Decoder Y4
F2
Y5
z
Y6 F3
Y7
Fig. 5. Implementation of the given Boolean function using 3:8 decoder.
5. Design a 3-bit binary to Gray code converter using PLA.

Ans. Truth table :
Binary input Gray output
B2 B1 B0 G2 G1 G0
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0
Simplification using K-map :

The K-maps for the Gray outputs are as shown in Fig. 6.
For G2 For G1
B1B0 B1B0
B2 00 01 11 10 B2 00 01 11 10
0 0 0 0 0 0 0 0 1 1
0 1 3 2 0 1 3 2
1 1 1 1 1 1 1 1 0 0
4 5 7 6 4 5 7 6
( a) (b )
B1B0 For G0
B2 00 01 11 10
0 0 1 0 1
0 1 3 2
1 0 1 0 1
4 5 7 6
(c )
Fig. 6.
G2 = B2
G1 = B2 B1  B2 B1
G0 = B1 B0  B1 B0
Implementation :
Fig. 7 shows the implementation using PLA.
B0
× B0
× B0
Binary B1 × × B1
AND matrix
inputs × × B1
B2 × × B2
× B2
B2
B 0B 1 B 0B 1 B 2B 1 B 2B 1
× G2
× × G0
Gray
output
× × G1
OR matrix
Fig. 7.
6. Draw and explain 4-bit universal shift register.

Ans.
shift register.
ii. Left shifting.
Parallel output
A3 A2 A1 A0
Clear
D D D D
CLK
S1 4×1 MUX 4×1 MUX 4×1 MUX 4×1 MUX

Serial
input
Serial
for shift
I3 I2 I1 I0 input
right
for shift
Parallel inputs
left
S1 S0 Function
0 0 Hold
0 1 Shift right
1 0 Shift left
1 1 Load
Operation :
1. When S1S0 = 00, the present value of the register is applied to the
D inputs of the flip-flops. This condition forms a path from the
output of each flip-flop to the binary value input of the same flip-
flop.
2. The next clock edge transfers into each flip-flop the binary value
it held previously and no change of state occurs.
inputs of the flip-flops. This causes a shift right operation, with
the serial input transferred in flip-flop FF4.
input going into flip-flop FF 1 . In this case, Input I2 of each
multiplexer is connected to the output of each flip-flop. The data
bit is shifted to left side for every clock.
5. When S1S0 = 11, the binary information on the parallel input lines
is transferred into the register simultaneously during the next clock
edge.
7. Describe the hazards in digital circuits. How are these

removed ?
Ans.
A. Hazards :
propagation delays.
wrong stable state.
B. Elimination of hazards :
x1
x2
F (x1, x2, x3) = x2x3 + x1x2
x3
Fig. 9.
x2 x3
x1 00 01 11 10
0 1
0 1 3 2
1 1 1 1
4 5 7 6

Fig. 10.

F = x2 x3  x1 x2
x2 x3
x1 00 01 11 10
0 1
0 1 3 2
1 1 1 1
4 5 7 6

Fig. 11.
F = x2 x3  x1 x2  x1 x3
new term
x1 x1x2
x2
x3 F = x1x2 + x2x3 + x1x3

x2x3
x1x3

Fig. 12.
8. What do you understand by state reduction ? Reduce the

following state diagram.
0/0
a
0/0
1/0
0/0 0/0
0/0
b c
1/0
1/0
g d e
0/0
1/1
1/1
0/0 1/1
f
1/1
Fig. 13.
Ans.
A. State reduction :
1. Any logic design process must consider the problem of minimizing
the cost of the final circuit. One way to reduce the cost is, by
reducing the number of flip-flops, i.e., by reducing the number of
states.
2. The state reduction technique basically avoids the introduction of
redundant equivalent states. The reduction of redundant states
reduces the number of flip-flops and logic gates required, thus
reducing the cost of the final circuit.
3. Two states are said to be redundant or equivalent, if every possible
set of inputs generate exactly the same outputs and the same next
states.
4. When two states are equivalent one of them can be removed
without altering input-output relationship.
B. Numerical :
1. The given Fig. 13 has seven states, one input and one output. The
2. From the state table, it is clear that states e and g are equivalent.
So the state g is replaced by state e.
State table :
x=0 x=1 x= 0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
Both are equivalent
same next state and

x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
Both are
states e
f f 0 1
3. From the reduced table, states d and f are equivalent, hence f can
be replaced by d and it can be removed.
Reduced table :
x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e d 0 1
e a d 0 1
4. The state diagram of the reduced state table is shown in Fig. 14.
0/0
0/0
e a
1/0
0/0 1/1
0/0
1/0
d b
1/0 c 0/0
1/1
Fig. 14.
9. Derive the state table and state diagram for the sequential
circuit shown in Fig. 15.
A x
JA QA JB QB B
A B
A
KA QA KB QB B
x x
CP
y
B
Fig. 15.
Ans.
1. Type of circuit :
The output y of the sequential circuit depends on present state
only, so the given logic circuit is the Moore type circuit.
2. Excitation equations :
For flip-flop A : JA = B
KA = Bx
For flip-flop B : JB = x
KB = A  x
For output y : y = AB
3. We know that characteristics equation of JK flip-flop :
An+1 = JQn  KQn

4. State equation for flip-flop A :
An+1 = BA  ( Bx ) A (  Qn = A)
= BA  A( B  x)
= BA  AB  xA
An+1 = (A  B) + xA
5. State equation for flip-flop B :
Bn+1 = xB  ( A  x) B (  Qn = B)
= xB  ( Ax  Ax ) B
Bn+1 = xB  AxB  AxB
State table :
x=0 x=1 y
AB AB AB
00 01 00 0
01 11 10 1
10 11 10 1
11 00 11 0
State diagram :
1
00 State
0 Output
0
0
11 0 01
1 0 1
0 1
10
1
1
Fig. 16.
SECTION – C
Attempt any two questions from this section. (15 × 2 = 30)

10. Minimize the following using Quine-McCluskey method :
F(W, X, Y, Z) = m(0, 3, 5, 6, 7, 10, 12, 13) +d (2, 9, 15)
Ans.
1. F(W, X, Y, Z) =m(0, 3, 5, 6, 7, 10, 12, 13) +d (2, 9, 15)
First, we group the minterms according to the numbers of 1’s.
0 m0 0000 0, 2* 00_0 2*, 3, 6, 7 0_1_
1 dm2 0010 2*, 3 001_ 5, 7, 13, 15* _ 1 _ 1
2 m3 0011 2*, 6 0_10
m5 0101 2*, 10 _010
m6 0110 3, 7 0_11
m10 1010 5, 7 01_1
m12 1100 5, 13 _101
dm9 1001 6, 7 011_
3 m7 0111 12, 13 110_
m13 1101 9*, 13 1_01
4 dm15 1111 7, 15* _111
13, 15* 11_1
2. Then, we prepare the table of prime implicants.
Prime
Minterm implicant m0 m3 m5 m6 m7 m10 m12 m13
WXZ  0, 2* 
XYZ  2*, 10 
WXY  12, 13  
WYZ 9*, 13 
WY  2*, 3, 6, 7   
XZ  5, 7, 13, 15*   
F(W, X, Y, Z) = WY  XZ  WXZ  XYZ  WXY
11. a. Design a 3-bit asynchronous up-down counter using

T flip-flop.
Ans.
1. The number of flip-flop to be used is three. We shall use three
toggle flip-flop. Let, up counting takes place with M = 0 and down
counting take place for M = 1.
2. First, we write the circuit excitation table.

Table 2 : Excitation table for a 3-bit up/down synchronous counter
Mode Present state Next state Flip-flop inputs
control M QC QB QA QC+1 QB+1 QA+1 TC TB TA
0 0 0 0 0 0 1 0 0 1
0 0 0 1 0 1 0 0 1 1
0 0 1 0 0 1 1 0 0 1
0 0 1 1 1 0 0 1 1 1
0 1 0 0 1 0 1 0 0 1
0 1 0 1 1 1 0 0 1 1
0 1 1 0 1 1 1 0 0 1
0 1 1 1 0 0 0 1 1 1
1 0 0 0 1 1 1 1 1 1
1 0 0 1 0 0 0 0 0 1
1 0 1 0 0 0 1 0 1 1
1 0 1 1 0 1 0 0 0 1
1 1 0 0 0 1 1 1 1 1
1 1 0 1 1 0 0 0 0 1
1 1 1 0 1 0 1 0 1 1
1 1 1 1 1 1 0 0 0 1
For TC For T B
QBQA QBQA
MQC 00 01 11 10 MQ C 00 01 11 10
00 0 0 1 0 00 0 1 1 0
0 1 3 2 0 1 3 2
01 0 4 0 5 1 7 0 6 01 0 4 1 5 1 7 0 6
11 1 12 0 13 0 15 0 14 11 1 12 0 13 0 15 1 14
10 1 8 0 9 0 11 0 10 10 1 8
0
9
0
11
1 10
TC = MQB QA + MQB QA TB = MQA + QAM

= M Q A
QBQA For TA
MQ C 00 01 11 10
00 1 1 1 1
0 1 3 2
01 1 4
1 5
1 7
1
6
11 1 1 1 1
12 13 15 14
10 1 8 1 9 1 11 1 10
TA = 1
4. Finally, let us draw the logic diagram.
Mode
control M = 0 for up counting
(M) M = 1 for down counting
Logic 1 MQAQB
MQA
TA Q A T B QB TC Q C
A B C
QA QB QC
MQA
MQAQB
CLK
Fig. 17. Logic diagram of a 3-bit synchronous up/down counter.
b. Design a full adder using two half adders.

Ans.
1. Full adder is a circuit that performs the addition of three binary
digits. It has three inputs A, B and C with two output S and Co,
where C is the previous carry. The block diagram is shown in
Fig. 18.
A S
B Full Adder
C Co
Fig. 18. Full Adder.
2. If there are three input variables the combinations are eight
(23 = 8). Now form the truth table of the full adder.
Inputs Outputs
A B C S Co
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
For S For C0
BC BC
00 01 11 10 00 01 11 10
A A
0 1 1 0 1
0 1 3 2 0 1 3 2
1 1 1 1 1
1 1
4 5 7 6 4 5 7 6
Fig. 19.
3. Sum : S = ABC  ABC  ABC  ABC
4. A full adder can be implemented using two half adders and one OR
gate.
Sum : S = ABC + ABC  ABC  ABC

= ABC + ABC  ABC  ABC
= C ( AB  AB)  C ( AB  AB)
= C ( AB  AB)  C ( AB  AB)
= (A  B)  C
= AB + C (A + B)
= AB  C ( A  B) ( A  A) ( B  B)
= AB  C [ AB  AB  AB]
= AB  ABC  C ( AB  AB)
= AB (1 + C) + C (A  B)
= AB + C (A  B)
Half adder
A
B S
C Co
Fig. 20. Full adder circuit using 2 half adder.
12. Design the clocked sequential circuit for the following state
diagram using JK flip-flops.
0
1 00 1
1 01 11 0
0 10 1
0
Fig. 21.
Ans. The state table for the given state diagram is (Moore model) :
Input Present state Next state Flip-flop inputs
x Q1 Q0 Q1 Q0 J1 K1 J0 K0
0 0 0 0 0 0 × 0 ×
0 0 1 1 0 1 × × 1
0 1 0 1 0 × 0 0 ×
0 1 1 1 1 × 0 × 0
1 0 0 0 1 0 × 1 ×
1 0 1 0 1 0 × × 0
1 1 0 1 1 × 0 1 ×
1 1 1 0 0 × 1 × 1
Columns of J1, K1, J0, K0 are filled by the help of excitation table of JK
flip-flop.
Excitation table of JK flip-flop :
Present state Next state J K

0 0 0 ×
0 1 1 ×
1 0 × 1
1 1 × 0
K-maps for J0, K0, J1 and K1 are :
For J 1 For K1
Q1Q0 Q1Q0
x 00 01 11 10 x 00 01 11 10
0 1 × × 0 × ×
0 1 3 2 0 1 3 2
1 × × 1 × × 1
4 5 7 6 4 5 7 6
J1 = x Q 0 K1 = x Q0
Q1Q0 For J 0 Q1Q0 For K0

x 00 01 11 10 x 00 01 11 10
0 × × 0 × 1 ×
0 1 3 2 0 1 3 2
1 × × 1 × 1 ×
1 1
4 5 7 6 4 5 7 6
J0 = x K0 = x Q1 + x Q1
Fig. 22.
The boolean expressions for J1, K1, J0 and K0 are :
K0 = xQ1 + xQ1 = x  Q1 = x  Q1
J0 = x
K1 = xQ0
J1 = xQ0
J1 Q1 J0 Q0
CLK
K1 Q1 K0 Q0
Fig. 23+.

B.Tech.
SECTION – A
a. Convert (153.513)10 to an octal number.
b. Write the advantages of Gray code over the straight binary

number sequence.
c. Give the general procedure for converting a multilevel

AND-OR diagram into an all NAND diagram.
d. Draw the logic diagram of half subtractor.
e. Specify the purpose of valid bit indicator in priority encoder.
f. Give the function table of SR latch.
g. Express the characteristic equation for the JK flip-flop.
h. Compare Mealy and Moore model of finite state machine.
i. The contents of a four bit register are initially 1011. The register
is shifted six times to the right with serial input being 101111.
What are the contents of the register after each shift ?
j. Write the steps that must be taken for the purpose of

SECTION – B
2. Attempt any five questions from this section : (10 × 5 = 50)

a Simplify the boolean function.
F (w, x, y, z) = m(1, 3, 7, 11, 15)
d (w, x, y, z) = d(0, 2, 5)
b. Implement the following boolean function with NAND

gate : F(x, y, z) = (1, 2, 3, 4, 5, 7)
c. Design a full subtractor circuit with three inputs x, y, Bin

x-y-Bin, where Bin is the input borrow, Bout is the output
d. Draw the logic diagram of a two to four line decoder using

NOR gates only.
e. Construct a JK flip-flop, using a D flip-flop, a two to four

one line multiplexer and an inverter.
f. Design a hazard free circuit of the following boolean

function F (x1, x2, x3) = m(1, 5, 6, 7)
g. Describe the operation of four bit synchronous binary

h. Draw the basic configuration of three PLDs.
SECTION – C
Note : Attempt any two questions from this section. (15 × 2 = 30)
3. Minimize the following s witching function using
F(x1, x2, x3, x4, x5) = m(0, 1, 2, 8, 9, 15, 17, 21, 24, 25, 27, 31)
4. Design a combinational circuit that converts a BCD code

to excess-3 code.
5. Implement the following four boolean functions with a

PAL.
W (A, B, C, D) = m(2, 12, 13)
X (A, B, C, D) = m(7, 8, 9, 10, 11, 12, 13, 14, 15)
Y (A, B, C, D) = m(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
Z (A, B, C, D) = m(1, 2, 8, 12, 13)

SECTION – A
a. Convert (153.513)10 to an octal number.
Ans.
(153)10 to octal : (0.513)10 to octal :
8 153 1 0.513 × 8 = 4.104
0.104 × 8 = 0.832
8 19 3 0.832 × 8 = 6.656
8 2 2 0.656 × 8 = 5.248
0.248 × 8 = 1.984
0
0.984 × 8 = 7.872
(153)10 = (231)8, (0.513)10 = (0.406517......)8
So, (153.513)10 = (231.406517)8
b. Write the advantages of Gray code over the straight binary

number sequence.
Ans.
c. Give the general procedure for converting a multilevel

AND-OR diagram into an all NAND diagram.
Ans.
1. Convert all AND gates to NAND gates with AND-invert graphic
symbols.
2. Convert all OR gates to NAND gate with invert-OR graphic symbol.
3. Check all bubbles in the diagram. For every bubble that is not
compensated by another small circle along the same line, insert an
inverter (a one-input NAND gate) or complement the input literal.
d. Draw the logic diagram of half subtractor.

Ans.
A
D
B
Bo
Fig. 1.
e. Specify the purpose of valid bit indicator in priority encoder.

Ans. In priority encoder, valid bit indicator is set to 1, when one or more
inputs are equal to 1. If all inputs are 0, there is no valid input and
valid bit indicator is equal to 0. The other two outputs are not
inspected when valid bit indicator equals to 0 and are specified as
don’t care conditions.
Table 1. Truth table of a priority encoder.
Inputs Outputs
D0 D1 D2 D3 x y V
0 0 0 0 × × 0
1 0 0 0 0 0 1
× 1 0 0 0 1 1
× × 1 0 1 0 1
× × × 1 1 1 1
f. Give the function table of SR latch.

Ans.
S R Qn + 1
0 0 Qn (Present state)
0 1 0
1 0 1
1 1 ×
g. Express the characteristic equation for the JK flip-flop.

Excitation table :
inputs state state
J K Qn Qn + 1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
h. Compare Mealy and Moore model of finite state machine.

Ans.
S. No. Mealy model Moore model
1. Its output is a function of Its output is the function of

present input as well as present state only.
present state.
2. It requires less number of It requires more number of
states for implementing states for implementing same
same function. function.
i. The contents of a four bit register are initially 1011. The register
is shifted six times to the right with serial input being 101111.
What are the contents of the register after each shift ?
Ans. Given : Serial input = 101111, initial content = 1011.
CLK Din = D3 Q3 = D2 Q2 = D1 Q1 = D0 Q0
initially  1 0 1 1
st
1  1 1 1 0 1
nd
2  1 1 1 1 0
rd
3  1 1 1 1 1
th
4  1 1 1 1 1
th
5  0 0 1 1 1
th
6  1 1 0 1 1
j. Write the steps that must be taken for the purpose of

Ans. The steps that must be taken for the purpose of transferring a
new word to be stored into memory are as follows :
1. Apply the binary address of the desired word to the address lines.
2. Apply the data bits that must be stored in memory to the data
input lines.
3. Activate the write input.
SECTION – B
2. Attempt any five questions from this section : (10 × 5 = 50)

a Simplify the boolean function.
F (w, x, y, z) = m(1, 3, 7, 11, 15)
d (w, x, y, z) = d(0, 2, 5)
Ans.
1. F(w, x, y, z) = m(1, 3, 7, 11, 15)
and don’t care conditions
d(w, x, y, z) =d(0, 2, 5)
2. The minterms of F are the variable combinations that make the
function equal to 1. The minterms of d are the don’t care minterms
that may be either 0 or 1.
3. The K-map simplification is shown in Fig. 2.
yz yz
wx 00 01 11 10 wx 00 01 11 10
00 × 11 1 × × 11 1 ×
0 3 2 00 0 3 2
01 0 × 1 0 0 0
4 5 7 6 01 4 ×5 1 7 6
11 0 0 1 0 11 0 0 1 0
12 13 15 14 12 13 15 14
10 0 0 1 0 0 09 1 11 0 10
8 9 11 10 10 8
F = yz + wx F = yz + wz
(a) (b)
Fig. 2.
4. The minterms of F are marked by 1’s, those of d are marked by ×’s
and the remaining is filled with 0’s.
5. To get the simplified expression in SOP form, we must include all
five 1’s in the map, but we may or may not include any of the ×'s,
depending on the way the function is simplified.
6. In Fig. 2(a), don’t care minterms 0 and 2 are included with the 1’s,
resulting as
F = yz + wx
7. In Fig. 2(b), don’t care minterm 5 is included with the 1’s, resulting
as
F = yz + wz
8. The K-map in Fig. 2(b) is more feasible because, we have to use the
minimum don’t care.
b. Implement the following boolean function with NAND

gate : F(x, y, z) = (1, 2, 3, 4, 5, 7)
Ans.
1. The K-map simplification is shown in Fig. 3.
yz
x 00 01 11 10
0 1 1 1
0 1 3 2
1 1 1 1
4 5 7 6
Fig. 3.
2. Hence, the simplified function is
F = z  xy  xy
3. Implementation using NAND gates is shown in Fig. 4.
F = ( x  y ). ( x  y). ( z )
= z  xy  x. y
x y z
x y xy = x + y
xy = x + y
z
Fig. 4.
c. Design a full subtractor circuit with three inputs x, y, Bin

x-y-Bin, where Bin is the input borrow, Bout is the output
Ans.
1. It is a combinational circuit that performs the subtraction of three
binary digits.
x Diff
y Full subtractor
Bin Bout
Fig. 5.
2. Fig. 5 shows the block diagram approach of full subtractor. It has
three inputs x, y and Bin and two outputs ‘Diff’ and Bout produced by
subtraction of three input bits.
3. For the formation of truth table, eight possible combinations of
three input variables with their outputs are required.
Inputs Outputs
x y Bin Diff Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
4. Using the concept of K-map, reduce the truth table to a function
(algebraic or boolean).
yBin yBin
x 00 01 11 10 x 00 01 11 10
0 1 1 0 1 1 1
0 1 3 2 0 1 3 2
1 1 1 1 1
4 5 7 6 4 5 7 6
Diff = x y Bin + x y Bin + xyBin + xyB in Bout = x Bin + yBin + xy

Fig. 6.
5. A full subtractor can also be implemented using two half subtractors
and an OR gate.
Diff = xyBin  xy Bin  xy Bin  x yBin
= Bin ( xy  x y )  Bin ( x y  x y)
= Bin ( x  y)  Bin ( x  y)  ( x  y)  Bin
and Bout = x y  x Bin  yBin  x y  Bin (x  y)
= x y  Bin ( x  y) ( x  x) ( y  y)
= xy  Bin ( xy  xy  x y)  xy  xyBin  Bin ( xy  x y)
= x y( Bin  1)  Bin ( x  y)  x y  Bin ( x  y)
Half subtractor
Bin Diff
x
y
B out
Fig. 7. Full subtractor circuit using 2 half subtractor.

d. Draw the logic diagram of a two to four line decoder using

NOR gates only.
Ans. Truth table :
Enable Input Output
E A B Y3 Y2 Y1 Y0
0 × × 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
Circuit using NOR gate :
A
Y 0 = (A + B + E) = A B E
B
Y 1 = (A + B + E) = A B E
Y 2 = (A + B + E) = A B E
Y 3 = (A + B + E) = A B E
E
Fig. 8.
e. Construct a JK flip-flop, using a D flip-flop, a two to four

one line multiplexer and an inverter.
Ans. Since a two to four one line multiplexer is not possible hence the
solution is given by assuming four to one line multiplexer.
1. The circuit diagram of a JK flip-flop constructed with a D flip-flop,
4:1 MUX and gates is shown in Fig. 9.
2. The J input sets the flip-flop to 1, the K input resets it to 0, and
when both inputs are enabled, the output is complemented.
3. When J = 0, K = 0, D = Q = Qn
4. When J = 0, K = 1, 0 line is selected, the output Q = 0.
Truth table
MUX
I1 J K Qn+1
D Q
0 I2 0 0 Qn
CLK
1 I3 0 1 0
Q
I4 1 0 1
S2 S1 1 1 Qn
Circuit diagram
J K
Fig. 9.
5. When J = 1, K = 0, 1 is selected, the output Q = 1.
6. When J = 1, K = 1, D = Qn .
f. Design a hazard free circuit of the following boolean

function F (x1, x2, x3) = m(1, 5, 6, 7)
Ans. Elimination of hazards :
1. Given, F(x1, x2, x3) = m (1, 5, 6, 7)
x2 x3
x1 00 01 11 10
0 1
0 1 3 2
1 1 1 1
4 5 7 6

Fig. 10.
F = x2 x3  x1 x2
x1
x2
F (x1, x2, x3) = x2x3 + x1x2
x3
Fig. 11.
x2 x3
x1 00 01 11 10
0 1
0 1 3 2
1 1 1 1
4 5 7 6

Fig. 12.
F = x2 x3  x1 x2  x1 x3
new term
x1 x1x2
x2
x3 F = x1x2 + x2x3 + x1x3

x2x3
x1x3
Fig. 13.
g. Describe the operation of four bit synchronous binary

Ans.
1. The C inputs of all flip-flops are connected to a common clock. The
counter is enabled by count enable.
2. If the enable input is 0, all J and K inputs are equal to 0 and the
clock does not change the state of the counter.
3. The first stage A0 has its J and K equal to 1 if the counter is
enabled. The other J and K inputs are equal to 1 if all previous
least significant stages are equal to 1 and the count is enabled.
4. The chain of AND gates generates the required logic for the J and
K inputs in each stage.
5. The counter can be extended to any number of stages, with each
stage having an additional flip-flop and an AND gate that gives an
output of 1 if all previous flip-flop outputs are 1.
J A0
C
Count enable K
J A1
C
K
J A2
C
K
J A3
C
K
To next stage
CLK
Fig. 14. Four-bit synchronous binary counter.
h. Draw the basic configuration of three PLDs.

Ans.
1. The PROM is a combinational programmable logic device (PLD)-an
integrated circuit with programmable gates divided into an AND
array and an OR array to provide an AND–OR sum-of-product
implementation. Fig. 15 shows the configuration of the three PLDs.
Fixed AND Programmable

Inputs Outputs
array (decoder) OR array
(a) Programmable read-only memory (PROM)
Programmable Fixed
Inputs Outputs
AND array OR array
(b) Programmable array logic (PAL)
Programmable Programmable
Inputs Outputs
AND array OR array
(c) Programmable logic array (PLA)
Fig. 15.
2. The PROM has a fixed AND array constructed as a decoder and a

programmable OR array. The programmable OR gates implement
the boolean functions in sum-of-minterms form.
3. The PAL has a programmable AND array and a fixed OR array.
The AND gates are programmable to provide the product terms for
the boolean functions which are logically summed in each OR gate.
4. The most flexible PLD is the PLA, in which both the AND and OR
arrays can be programmed. The product terms in the AND array
may be shared by any OR gate to provide the required sum of
products implementation.
SECTION – C
Note : Attempt any two questions from this section. (15 × 2 = 30)
3. Minimize the following s witching function using
F(x1, x2, x3, x4, x5) = m(0, 1, 2, 8, 9, 15, 17, 21, 24, 25, 27, 31)
Ans. Table 1. For obtaining all the prime implicants.

0 m0 00000 0, 1  0000_ 0, 1, 8, 9 0 _ 0 0 _C
1 m1 00001 0, 2 H 0 0 0 _ 0 1, 9, 17, 25 _ _ 0 0 1 B
m2 00010 0, 8  0 _ 0 0 0 8, 9, 24, 25 _ 1 0 0 _ A
m8 01000
1, 9  0_001
2 m9 0 1 0 01 1, 17  _0001
m17 10001 8, 9  0100_
m24 11000 8, 24  _1000
3 m21 10101 9, 25  _1001

m25 11001 17, 21 G 10_01
4 m15 01111 17, 25  1_001

m27 11 011 24, 25  1100_
5 m31 11111 25, 27 F 110_1

15, 31 E _1111
27, 31 D 11 _11
Table 2. Prime-implicant
  
Minterm m0 m1 m2 m8 m9 m15 m17 m21 m24 m25 m27 m31
A    
B    
C    
D  
E  
F  
G  
H  
So the essential prime implicants are,

F(x1, x2, x3, x4, x5) = E + G + A +
H = x2 x3 x4 x5  x1 x2 x4 x5  x1 x2 x3 x5  x2 x3 x4
4. Design a combinational circuit that converts a BCD code

to excess-3 code.
Ans. Truth table :
Input BCD Output excess-3 code
A B C D w x y z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1. The maps in Fig. 16, are plotted to obtain simplified boolean functions
for the outputs.
2. A two-level logic diagram of each output may be obtained directly
from the boolean expressions derived from the maps.
For z For y
CD CD
AB 00 01 11 10 AB 00 01 11 10
00 1 0 1 3
1 2
00 1 0 1
1 3 2
01 1 4 5 7 1 6 01 1 4 5
1 7 6
11 × 12 × 13 × 15 × 14 11 × 12
×
13
×
15
×
14
10 1 8 9 × 11 × 10 10 1 8 9
×
11
× 10
z=D y = CD + CD
For x For w
CD CD
00 01 11 10 00 01 11 10
AB AB
00 1 1 1 00
0 1 3 2 0 1 3 2
01 1 4 5 7 6 01 4 1 5 1 7 16
11 × × × × 11 ×12 × 13 × 15 × 14
12 13 15 14
× 1 19 × ×
10 8 19 × 11 10 10 8 11 10
x = BC + BD + BCD w = A + BC + BD
Fig. 16. Maps for BCD to excess-3 code converter.

3. The expressions derived from the maps are :

z= D
y = CD + CD = CD + (C  D)
x = BC  BD  BCD = B(C  D)  BCD
= B (C + D) + B (C  D)
w = A + BC + BD = A +B(C + D)
4. The logic diagram that implements these expressions is shown in
Fig. 17.
D
z
D CD
y
C
C+D
(C + D)
B
x
A w
Fig. 17.
5. Implement the following four boolean functions with a

PAL.
W (A, B, C, D) = m(2, 12, 13)
X (A, B, C, D) = m(7, 8, 9, 10, 11, 12, 13, 14, 15)
Y (A, B, C, D) = m(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
Z (A, B, C, D) = m(1, 2, 8, 12, 13)
Ans.
1. Simplifying the four functions to a minimum number of terms
results in the following boolean functions :
CD For W CD For X
AB 00 01 11 10 AB 00 01 11 10
00 1 00
0 1 3 2 0 1 3 2
01 01 1
4 5 7 6 4 5 7 6
11 1 1 11 1 1 1 1
12 13 15 14 12 13 15 14
10 10 1 1 1 1
8 9 11 10 8 9 11 10
CD For Y CD For Z
AB 00 01 11 10 AB 00 01 11 10
00 1 1 1 00 1 1
0 1 3 2 0 1 3 2
01 1 1 1 1 01
4 5 7 6 4 5 7 6
11 1 11 1 1
12 13 15 14 12 13 15 14
10 1 1 1 10 1
8 9 11 10 8 9 11 10
Fig. 18.
W = ABC  ABCD
X =  + BCD
Y = AB  CD  BD
Z = ABC  ABCD  ACD  ABCD
= W  ACD  ABCD
2. Table 3 lists the PAL programming table for the four boolean
functions. The table 3 is divided into four sections with three
product terms in each section.
3. The first two sections need only two product terms to implement
the boolean function. The last section for output Z needs four
product terms. Using the output from W, we can reduce the
function to three terms.
4. The fuse map for the PAL as specified in the programming
Table 3 is shown in Fig. 19 for each 1 or 0 in the Table 3.
5. We mark the corresponding intersection in the diagram with the
symbol for an intact fuse. For each dash, we mark the diagram
with blown fuses in both the true and complement inputs.
6. If the AND gate is not used we leave all its input fuse intact. Since
the corresponding input receives both the true value and the
complement of each input variable, we have A A = 0 and the
output of the AND gate is always 0.
Table 3. PAL programming
Product Term AND Input Outputs

A B C D W
1 1 1 0 — — W = ABC  ABCD
2 0 0 1 0 —
3 — — — — —
4 1 — — — — X =  + BCD
5 — 1 1 1 —
6 — — — — —
7 0 1 — — — Y = AB  CD  BD
8 — — 1 1 —
9 — 0 — 0 —
10 — — — — 1 Z = W + ACD  ABCD
11 1 — 0 0 —
12 0 0 0 1 —
Product A A B B C C D D W W
term
1 × × ×
2 × × × × W
3 ×
A
4 ×
5 × × × X
6 ×
B All fuses intact
(always = 0)
7 × ×
8 × × Y
9 × ×
C
10 ×
11 × × × Z
12 × × × × × Fuse intact
D + Fuse blown
A A B B C C D D W W
Fig. 19. Fuse map for PAL as specified in Table 3.

B. Tech.
DIGITAL LOGIC DESIGN
Note : Attempt all sections. If require any missing data; then choose
suitably.
SECTION-A
1. Attempt all questions in brief : (2 × 7 = 14)

a. Write four advantages of digital systems over analog
system.
b. Write the excitation table and characteristic equation of

JK flip-flop.
c. Write the difference between combinational and sequential

circuits.
d. What is (33)6 + (45)6 ?
e. Implement the expression Y = ABC + BD + E using NAND

gate only.
f. Convert the following :

i. (562.13)7 = (?)10
ii. (467.342)8 = (?)10
g. What is race around condition ?
SECTION-B
2. Attempt any three of the following : (7 × 3 = 21)

a. Simplify the following Boolean function using K-map
Y = m(0, 1, 3, 5, 6, 7, 9, 11, 16, 18, 19, 20, 21, 22, 24, 26).
b. Write the steps for combinational circuit designing and

design a circuit of three input which gives an high output
whenever the sum of LSB and MSB bit is 1.
c. Implement the function F = m(0, 1, 3, 4, 7, 8, 9, 11, 14, 15)

using 8:1 mux.
d. Draw and explain the PISO, PIPO register.
e. Draw and explain 4-bit by 3-bit multiplier.
SECTION-C
3. Attempt any one part of the following : (7 × 1 = 7)

a. Design a universal shift register that performs HOLD,
SHIFT RIGHT, SHIFT LEFT, and LOAD.
b. Generate the Hamming code for the word 11011. Assume

that a single error occurs while storing the generated
Hamming code. Explain how this single error is detected.

a. Draw and explain 4-bit magnitude comparator.
b. Draw a decimal adder to add BCD numbers.

a. Draw and explain the operation of a RTL NOR gate.
b. Draw and explain the operation of a TTL NAND gate.

a. An asynchronous sequential logic circuit is described by
the following excitation and output function
y = X1X2 + (X1 + X2)Y
Z=y
Draw the logic diagram of the circuit. Also derive the
transition table and output map.
b. Design a 3-bit up/down ripple counter.

a. Write short notes on RAM and PLA
b. Derive the s tate table and s tate diagram of the

synchronous sequential circuit shown below (X is an input
to the circuit). Explain the circuit function.
A
A D Q
X CLK Q
B B
D Q
CLK Q
A CLK
Fig. 1.

Note : Attempt all sections. If require any missing data; then choose
suitably.
SECTION-A
1. Attempt all questions in brief : (2 × 7 = 14)

a. Write four advantages of digital systems over analog
system.
Ans.
1. Digital communication system is more robust than analog system
because it can resist the corruption of signal much better in
presence of channel noise.
2. Implementation of digital hardware in digital communication
system is flexible and permits the use of microprocessor, digital
switching etc.
3. In digital system, it is possible to multiplex several digital signals
that offer more efficient use of available bandwidth.
4. In digital system, it is easy to store large quantities of information.
b. Write the excitation table and characteristic equation of

JK flip-flop.
Excitation table :
inputs state state
J K Qn Qn + 1
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
c. Write the difference between combinational and sequential

circuits.
Ans.
S. No. Combinational circuits Sequential circuits.
1. It consists of interconnection It consists of storage elements
of logic gates only. and logic gates.
2. Output o f co mbinational Output of sequential circuit
circuits depends only on the depends on present and previous
present value of input. value of input and output.
d. What is (33)6 + (45)6 ?

Ans. (33)6 = 3 × 61 + 3 × 60 = (21)10
+ (45)6 = 4 × 61 + 5 × 60 = (29)10
––––––––
(50)10
Now, 6 50
6 8 2
6 1 2
0 1
So, (33)6 + (45)6 = (50)10 = (122)6
e. Implement the expression Y = ABC + BD + E using NAND

gate only.
Ans. Y = ABC + BD + E
There are five variables, A, B, C, D and E
Y = Y = ABC  BD  E = ABC · BD · E
C
C
ABC
A
B
BD
Y
D
E
E
Fig. 1.
f. Convert the following :

i. (562.13)7 = (?)10
ii. (467.342)8 = (?)10
Ans.
i. (562.13)7 = 5 × 72 + 6 × 71 + 2 × 70 + 1 × 7–1 + 3 × 7–2
= (289.20)10
ii. (467.342)8 = 4 × 82 + 6 × 81 + 7 × 80 + 3 × 8–1 +4 × 8–2 + 2 × 8–3

= (311.441)10

SECTION-B

a. Simplify the following Boolean function using K-map
Y = m(0, 1, 3, 5, 6, 7, 9, 11, 16, 18, 19, 20, 21, 22, 24, 26)
Ans. K-map :
f(C, D, E, A, B)
CDE 000 001 011 010 110 111 101 100
AB
00 1 1 1 1
0 4 12 8 24 28 20 16
01 1 1 1 1
1 5 13 9 25 29 21 17
11 1 1 1 1
3 7 15 11 27 31 23 19
10 1 1 1 1
2 6 14 10 26 30 22 18
Fig. 2.
Y = DEAB  CDB  ACDE  CDAB  CDEB  CDEB  CDEA  CDEA
= DB( EA  CA)  CB( D  DE)  DE ( AC  AC )  CE( DB  DA)

= DB( EA  CA)  CB( D  E)  DE ( A  C )  CE( DB  DA)
b. Write the steps for combinational circuit designing and

design a circuit of three input which gives an high output
whenever the sum of LSB and MSB bit is 1.
Ans. Step for designing combinational logic circuit :
1. From the specifications of the circuits, determine the required
number of inputs and outputs and assign a symbol to each.
2. Derive the truth table that defines the required relationship
between inputs and outputs.
3. Obtain the simplified boolean functions for each output as a
function of the input variables.
4. Draw the logic diagram and verify the correctness of the design
(manually or by simulation).
Let the three input be A, B and C, so according to the question, the

truth table will be as follows :
LSB MSB
A B C Output
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
So, K-map for output

BC
A 00 01 11 10
0 1 1
0 1 3 2
1 1 1
4 5 7 6
Y = AC  AC = A  C
A
Y
C
Fig. 3.
c. Implement the function F = m(0, 1, 3, 4, 7, 8, 9, 11, 14, 15)

using 8:1 mux.
Ans.
1. The given Boolean function is a four variable function. Any one
variable of the function can be taken as input to the MUX and the
remaining variables are connected to the selection lines.
2. A is assumed to be MUX input and B,C, D are used as selection
lines.
i. A is complement variable of A for the minterm 0 to 7.
ii. A is normal variable (A) for the minterm 8 to 15.
3. We enter the complement variable minterms in first row of
implementation table and enter normal variable minterm in second
row of implementation table.
Decimal A B C D
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
I0 I1 I2 I3 I4 I5 I6 I7
A 0 1 2 3 4 5 6 7
A 8 9 10 11 12 13 14 15
1 1 0 1 A 0 A 1
Logic diagram :
Logic 1
Logic 0 I0
I1
I2
I3 8:1
A I4 F(A, B, C, D)
MUX
I5
I6
I7
B C D
Fig. 4.
d. Draw and explain the PISO, PIPO register.

Ans.
A. Parallel in serial out shift register :
1. Fig. 5 shows the block diagram of a parallel in serial out shift register.
In this type, the bits are entered in parallel, i.e., simultaneously into
their respective stages on a parallel line.
2. It produces the stored information on its output, in serial form.
Parallel in
Serial out
Fig. 5. Parallel in serial out shift register.

B. Parallel in parallel out shift register :
1. All the data appear simultaneously along with all the flip-flop inputs
and outputs.
2. Fig. 6 shows the logic diagram for 4-bit parallel in parallel out shift
register.
Parallel outputs
Q3 Q2 Q1 Q0
D3 Q3 D2 Q2 D1 Q1 D0 Q0
D C B A
CLK
D C B A
Parallel inputs
Fig. 6. Logic diagram for 4-bit parallel in parallel out shift register.
e. Draw and explain 4-bit by 3-bit multiplier.

Ans.
1. Consider a multiplier circuit that multiplies a binary number of
4-bits by a number of 3-bits.
2. Let the multiplicand represented by B3B2B1B0 and the multiplier by
A2A1A0.
3. Since K = 4 and J = 3, we need 12 AND gates and two 4-bit adders
to produce a product of seven bits.
4. The logic diagram of 4-bit by 3-bit multiplier is shown in Fig. 7.
A0
B3 B2 B1 B0
A1
B3 B2 B1 B0
Addend Augend
4-bit adder
Sum and output carry
A2
B3 B2 B1 B0
Addend Augend
4-bit adder
Sum and output carry
C6 C5 C4 C3 C2 C1 C0
Fig. 7. 4-bit by 3-bit binary multiplier.
SECTION-C

a. Design a universal shift register that performs HOLD,
SHIFT RIGHT, SHIFT LEFT, and LOAD.
Ans.
shift register.
ii. Left shifting.
Parallel output
A3 A2 A1 A0
Clear
D D D D
CLK
S1 4×1 MUX 4×1 MUX 4×1 MUX 4×1 MUX

Serial
input
Serial
for shift
I3 I2 I1 I0 input
right
for shift
Parallel inputs
left
S1 S0 Function
0 0 Hold
0 1 Shift right
1 0 Shift left
1 1 Load
Operation :
1. When S1S0 = 00, the present value of the register is applied to the
D inputs of the flip-flops. This condition forms a path from the
output of each flip-flop to the binary value input of the same flip-
flop.
2. The next clock edge transfers into each flip-flop the binary value
it held previously and no change of state occurs.
inputs of the flip-flops. This causes a shift right operation, with
the serial input transferred in flip-flop FF4.
input going into flip-flop FF 1 . In this case, Input I2 of each
multiplexer is connected to the output of each flip-flop. The data
bit is shifted to left side for every clock.
5. When S1S0 = 11, the binary information on the parallel input lines
is transferred into the register simultaneously during the next clock
edge.
b. Generate the Hamming code for the word 11011. Assume

that a single error occurs while storing the generated
Hamming code. Explain how this single error is detected.

a. Draw and explain 4-bit magnitude comparator.
Ans.
A = A3 A2 A1 A0
B = B3 B2 B1 B0
xi = Ai Bi  Ai Bi ; i = 0, 1, 2, 3.
xi = 1, if A = B
xi = 0, otherwise,
A3
x3
B3
A2
x2
B2
(A < B)
A1
x1
B1
A0
x0
(A > B)
B0
(A = B)

b. Draw a decimal adder to add BCD numbers.

Ans.
1. BCD adder is circuit that adds two BCD digits in parallel and produces
a sum digit which is also BCD. BCD numbers use 10 symbols (group
of 4 bits 0000 to 1001). BCD adder circuit must be able to do the
following and it is shown in Fig. 10.
3. If 4-bit sum is equal to or less than 9, the sum is a valid BCD
number and no correction is needed.
4. If the 4-bit sum is greater than 9 or if a carry is generated from the
sum, the sum is invalid BCD number. Then the digit 6 (0110)2
should be added to the sum to produce the valid BCD symbols.

K
Z8 Z4 Z2 Z 1
Output
carry
C
C = K + Z8 Z 4 + Z 8 Z 2
0
4-bit binary adder
S8 S4 S2 S1
Fig. 10. Block diagram of a BCD adder.
Z8 Z4 Z2 Z1 C S8 S4 S2 S1
0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 1 1
0 0 1 0 0 0 0 1 0 2
0 0 1 1 0 0 0 1 1 3
0 1 0 0 0 0 1 0 0 4
0 1 0 1 0 0 1 0 1 5
0 1 1 0 0 0 1 1 0 6
0 1 1 1 0 0 1 1 1 7
1 0 0 0 0 1 0 0 0 8
1 0 0 1 0 1 0 0 1 9
1 0 1 0 1 0 0 0 0 10
1 0 1 1 1 0 0 0 1 11

a. Draw and explain the operation of a RTL NOR gate.
Ans.
1. The basic circuit of the RTL digital logic family is the NOR gate
shown in Fig. 11. Each input is associated with one resistor and
one transistor.
VCC = 3.6 V
640 
Y = (A + B +C)
450  450  450 

A B C
Fig. 11. Basic RTL NOR gate.

2. The collectors of the transistors are tied together at the output.
The voltage levels for the circuit are 0.2 V for the low level and
from 1 to 3.6 V for the high level.
3. If any input of the RTL gate is high, the corresponding transistor
is driven into saturation and the output goes low, regardless of
the states of the other transistors.
4. If all inputs are low at 0.2 V, all transistors are cut-off because
VBE < 0.6 V and the output of the circuit goes high, approaching
the value of the supply voltage VCC.
b. Draw and explain the operation of a TTL NAND gate.
Ans.
1. The circuit of the two-input TTL NAND gate is shown in Fig. 12.
The input transistor, Q1 is a multiple emitter transistor.
+VCC
RC4 130 
RB RC2 1.6 k
1 4 k
IC2
Q4
TTL
multiple
emitter
Q1 Q2 DT
A
B Vo
DA DB Q3
RE2 1 k
Fig. 12. TTL NAND gates.


3. Transistors Q3 and Q4 form a totem-pole arrangement. Diodes, DA
and DB protect transistor, Q1 from being damaged by the negative
4. When negative spikes appear at the input terminals, the diodes
conduct and bypass the spikes to ground.
5. Diode DT ensures that transistors, Q3 and Q4 do not conduct
Operation :
1. A LOW voltage at either emitter E1 or emitter E2 forward-biases
the corresponding diode D1 or D2 and reverse-biases diode D3 which
is a base-collector junction of transistor Q1. There is no flow of
current from base to collector of transistor Q1.
2. A LOW voltage on both emitters of transistor Q1 does the same
action.
3. A HIGH voltage on both emitters reverse-bias both input diodes D1 and
D2 and forward bias D3. The current flows from base to collector of
transistor Q1.
Base, B
Diode, D 1 Diode, D 3
Emitter, E1
Collector, C
Diode, D 2
Emitter, E2
Fig. 13. Diode equivalent of TTL multiple emitters.
Table 2. Operation of TTL NAND gate


Y = X1X2 + (X1 + X2)Y
Z=Y
Draw the logic diagram of the circuit. Also derive the
transition table and output map.
Ans.
State table :
0 0 0 0 0 0 Yes 0
0 0 1 0 0 0 No 0
0 1 0 0 1 0 Yes 0
0 1 1 0 1 1 Yes 1
1 0 0 1 0 0 Yes 0
1 0 1 1 0 1 Yes 1
1 1 0 1 1 1 No 1
1 1 1 1 1 1 Yes 1
i. Logic diagram :
X1
X2
Y=Z
Fig. 14.
X1X2 Unstable state
00 01 11 10
Y Stable state
0 0 0 1 0
1 0 1 1 1
iii. Output map :

X1X2
00 01 11 10
Y
0 0 0 1 0
1 1 1 1 1

X 1X 2
Y 00 01 11 10
S0 S0/0 S0/0 S1/1 S0/0
S1 S0/0 S1/1 S1/1 S1/1
b. Design a 3-bit up/down ripple counter.

Ans.
1. The 3-bit up/down ripple counter, which can count in upward
direction of sequence from 000, 001, 010, 011, 100, 101, 110, 111
and downward direction of sequence from 111, 110, 101, 100, 011,
010, 001, 000.
2. 3-bit counter consists of 3 flip-flops. In ripple counter, a flip-flop
output transition serves as a source for triggering other flip-flops.
3. The control signal M is used to select the direction of count
sequence. Fig. 15 shows the 3-bit ripple.
M = 1; counter acts as up-counter
M = 0; counter acts as down counter
M Logic 1
Logic 1 Logic 1
JA QA JB Q B JC Q C Q
CLK A B C
KA QA KB QB KC QC Q
Fig. 15. 3-bit ripple up-down.

a. Write short notes on RAM and PLA
Ans.
A. Random access memory (RAM) :
1. It is a read/write memory that permits the modification of data bits
stored in the memory array as well as their retrieval on demand.
2. The stored data is volatile, i.e., the stored data is lost when the
power supply voltage is turned off.
3. RAM’s are classified into two main categories :
a. Dynamic RAM : The DRAM cell consists of a capacitor to store
binary information ‘1’ (high voltage) or ‘0’ (low voltage) and a
transistor to access the capacitor. Due to the advantage of low cost
and high density, DRAM is widely used for main memory.
b. Static RAM : The SRAM cell consists of a latch therefore, the cell
data is kept as long as the power is turned on and refresh operation
is not required as in case of DRAM cells. SRAM is mainly used for
the cache memory in applications.
B. Programmable logic array (PLA) :
structures. The PLA provides the designer with a systematic and
regular way of implementing output functions of n variable in sum
of product form.
more compact in nature. Any of the logical function can be expressed
in terms of SOP or POS.
3. PLA can be implemented in several forms, i.e., NOR–NOR,

4. The structure of PLA is shown in Fig. 16, and its internal logic with
three inputs and two outputs is shown in Fig. 16.
Fig. 16, are
F2 = ( AC  BC )
· AND
·
m input · · OR
· ·
·· ·
n output lines
Fig. 16. PLA structure.
6. The programming table that specifies the PLA of Fig. 17 is listed in
the table 3. The PLA programming table consists of three sections.
A
C
×× 1 ×
× × 2 × × AC
× × 3 × BC
×× × 4 ×
C C B B A A × 0
× 1
F1
F2
Fig. 17. PLA with three inputs, four product terms, and two outputs.
7. The first section lists the product term numerically. The second
section specifies the required paths between input and AND gates.
The third section specifies the path between the AND and OR
gates.
8. For each output variable, we may have a T (true) or C
(complement) for programming the XOR gate.
9. For each product term, the inputs are marked with 1, 0 or

— (dash).
10. If the variable in the product term appears in the form in which it
is true, the corresponding input variable is marked with a 1. If it
appears complemented, the corresponding input variable is marked
with a 0. If the variable is absent from the product term, it is
marked with a dash.
Table 3. PLA programming
Input Output
AB 1 1 0 — 1 —
AC 2 1 — 1 1 1
BC 3 — 1 1 — 1
ABC 4 0 1 0 1 —
11. The size of the PLA is specified by the number of inputs, the number
of product terms, and the number of outputs. A typical integrated
circuit PLA may have 16 inputs, 48 product terms and eight outputs.
12. For n inputs, k product terms, and m outputs, the internal logic of
the PLA consists of n buffer-inverter gates, k AND gates, m OR
gates, and m XOR gates.
b. Derive the s tate table and s tate diagram of the

synchronous sequential circuit shown below (X is an input
to the circuit). Explain the circuit function.
B
A
A D Q
X CLK Q
B B
D Q
CLK Q
A CLK
Fig. 18.
Ans.
1. From the circuit shown in Fig. 18, the output equation can be
obtained as,
A(t + 1) = ( BX  BX )  A
B(t + 1) = ( AX  AX )  B
2. The state table for the circuit shown in Fig. 18.
Present state Input Next state

A B X A(t + 1) B(t + 1)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 0
1 0 0 1 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
3. State diagram :
0 00
1 1
1 0
11 01
1
0
10
Fig. 19.

B. Tech.
DIGITAL LOGIC DESIGN
Note : Be precise in your answer. In case of numerical problem assume

data wherever not provided.
SECTION-A
1. Attempt all of the following questions : (2 × 7 = 14)

a. What is modulus of a counter ?
b. How many flip-flops are required to design Mod-5 ring

c. Determine the value of base x, if (193)x = (623)8.
d. Write the advantage of Gray code over the straight binary

number sequence.
e. What do you mean by fan-out and fan-in ?
f. Define cyclic codes.
SECTION-B
2. Attempt any three of the following questions : (7 × 3 = 21)

a. Minimize the given boolean function using K-map.
F(A, B, C, D) = m(3, 4, 5, 7, 9, 13, 14, 15)
b. Minimize the following using Quine-McCluskey method :

F(A, B, C, D) = m(0, 1, 9, 15, 24, 29, 30) + d(8, 11, 31)
c. Write a short note on priority encoder.
d. Implement the following Boolean function.

F(A, B, C, D) = m(0, 1, 3, 4, 7, 8, 9, 11, 14, 15)
i. 4 : 1 MUX
ii. 2 : 1 MUX
e. Design Binary code to Gray code converter.
SECTION-C
3. Attempt any one part of the following questions : (7 × 1 = 7)

a. i. Draw a BCD adder circuit and explain its working.
ii. Convert the SR flip-flop to JK flip-flop.
b. What do you mean by shift register ? What is the need of

shift register ? Draw and explain bidirectional shift
register.

a. i. Design a modulo-4 UP/DOWN counter using JK flip-flop.
ii. Design a ripple decade counter using JK flip-flop.
b. i. What is critical race and non-critical race ? How can they

be avoided ?
ii. Describe the hazards in digital circuits. How are these
removed ? Design a hazards free circuit of the following
Boolean function :
F(A, B, C) = m(1, 2, 3, 5)

a. i. Describe the circuit and performance of CMOS inverter
and state the characteristics of CMOS.
ii. Differentiate between PLA and PAL. Realize the full adder
circuit using PAL.
b. i. Discuss the concept of field programmable gate array

(FPGA). Discuss the various structures of FPGA.
ii. Tabulate the truth table for 8 × 4 ROM that implements

the Boolean function :
A(x, y, z) = m(1, 2, 4, 6)
B(x, y, z) = m(0, 1, 6, 7)
C(x, y, z) = m(2, 6)
D(x, y, z) = m(1, 2, 3, 5, 7)

Y = X1X2 + (X1 + X2)Y
Z=Y
ii. Derive the transition table and output map.

iii. Describe the behavior of the circuit.
b. i. The code 101101010 is received, correct any errors. There

are four parity bits and odd parity is used.
ii. Draw a full subtractor circuit using NAND gate.

a. Derive the state table and state diagram for the sequential
A
x
DA QA A
B A A
QA A B Y
x
A DB QB
x B
B
QB B
Cp
Fig. 1.
b. Draw the reduced state table and reduced state diagram

0/0
a
1/0 0/0
0/0 0/0 0/0
b c
1/0
g 1/1 d 0/0
e
0/0 1/1
f 1/1
1/1
Fig. 2.

Note : Be precise in your answer. In case of numerical problem assume

data wherever not provided.
SECTION-A
1. Attempt all of the following questions : (2 × 7 = 14)

a. What is modulus of a counter ?
Ans. The number of states passed by the counter before going to its
initial state is called modulus of counter.
b. How many flip-flops are required to design Mod-5 ring

Ans. Mod-5 Ring counter - 5 Flip-flop.
Mod-5 Johnson counter - 3 Flip-flop.
c. Determine the value of base x, if (193)x = (623)8.
Ans. (193)x = (623)8
1 × x2 + 9 × x + 3 × x0 = 6 × 82 + 2 × 81 + 3 × 80
x2 + 9x + 3 = 403
x2 + 9x – 400 = 0
x2 + 25x – 16x – 400 = 0
(x + 25)(x – 16) = 0
x  – 25 ( Base can’t be negative)
 x = 16
d. Write the advantage of Gray code over the straight binary

number sequence.
Ans.
e. What do you mean by fan-out and fan-in ?

Ans. Fan-out : The fan-out of a logic gate is defined as the maximum
number of standard load that the output of the gate can drive
without impairing its normal operation. Fan-out is also called the
loading factor.
 I I 
Fan-out = Minimum of  OH , OL 
 I IH I IL 
Fan-in : The fan-in of a logic gate refers to the number of inputs
that the gate is designed to handle.
f. Define cyclic codes.

Ans. When a bit pattern of two consecutive numbers differ by only one
bit position, these codes are called cyclic codes.

SECTION-B
2. Attempt any three of the following questions : (7 × 3 = 21)
a. Minimize the given boolean function using K-map.
F(A, B, C, D) = m(3, 4, 5, 7, 9, 13, 14, 15)
Ans.
CD
AB CD CD CD CD
AB 1
0 1 3 2
AB 1 1 1
4 5 7 6
AB 1 1 1
12 13 15 14
AB 1
8 9 11 10
Fig. 1.
F = ABC + ACD + ACD + ABC
b. Minimize the following using Quine-McCluskey method :

F(A, B, C, D) = m(0, 1, 9, 15, 24, 29, 30) + d(8, 11, 31)
Ans.
1. Arrange minterms according to categories of 1’s as shown in table 1 :
Table 1.
No. Min- Binary Minterms Binary Min- Binary
of terms (2 cell) terms
1’s (4 cell)
A B C D E A B C D E ABCD E
0 m0 0 0 0 0 0 0, 1  0 0 0 0 – 0, 1, 8*, 9 0 – 0 0 –
m1 0 0 0 0 1 0, 8*  0 – 0 0 0
1
dm 8 0 1 0 0 0 1, 9  0 – 0 0 1
m9 0 1 0 0 1 8*, 9  0 1 0 0 –
2
m 24 1 1 0 0 0 8*, 24 – 1 0 0 0
3 dm 11 0 1 0 1 1 9, 11* 0 1 0 – 1
m15 0 1 1 1 1 11*, 15 0 1 – 1 1
4
m 29 1 1 1 0 1 15, 31* – 1 1 1 1
m 30 1 1 1 1 0 29, 31* 1 1 1 – 1
5 dm 31 1 1 1 1 1 30, 31* 1 1 1 1 –
2. List of prime implicants :

Table 2.
Prime implicants Binary representation
A B C D E
8*, 24 – 1 0 0 0
9, 11* 0 1 0 – 1
11*, 15 0 1 – 1 1
15, 31* – 1 1 1 1
29, 31* 1 1 1 – 1
30, 31* 1 1 1 1 –
0, 1, 8*, 9 0 – 0 0 –
3. Select the minimum number of prime implicants which must cover
all the minterms except don’t care minterms.
Table 3.
Prime implicant Minterm
    
0 1 9 15 24 29 30
8*, 24  
9, 11* 
11*, 15 
15, 31* 
29, 31*  
30, 31*  
0, 1, 8*, 9    
Y = BC DE  ABCE  ABCD  AC D
c. Write a short note on priority encoder.

Ans. Priority encoder : In priority encoder if two or more inputs are
equal to 1 at the same time, the input having highest priority will be
considered.
Example :
Four inputs D0, D1, D2, D3 where D3 has highest priority and D0 has
lowest priority.
Y0, Y1 : binary output
V : validity of output
Table 4. Truth table for 4-bit priority encoder.

Input Output
D0 D1 D2 D3 Y1 Y0 V
0 0 0 0 × × 0
1 0 0 0 0 0 1
× 1 0 0 0 1 1
× × 1 0 1 0 1
× × × 1 1 1 1
D2D3 For Y1 D2D3 For Y0

D0D1 00 01 11 10 D0D1 00 01 11 10
00 1 1 1 00 1 1
0 1 3 2 0 1 3 2
01 1 1 1 01 1 1 1
4 5 7 6 4 5 7 6
11 1 11 1 1
12 13 1 15 1 14 12 13 1 15 14
10 1 1 1 10 1 1
8 9 11 10 8 9 11 10
Y 1 = D 2 + D3 Y 0 = D 3 + D1D2
D2D3 For V
D0D1 00 01 11 10
00 1 1 1
0 1 3 2
01 1 1 1 1
4 5 7 6
11 1 1 1 1
12 13 15 14
10 1 1 1 1
8 9 11 10
V = D0 + D 1 + D2 + D 3
Fig. 2.
Logic diagram :
D3 D2 D1 D0
Y0
Y1
Fig. 3.
d. Implement the following Boolean function.

F(A, B, C, D) = m(0, 1, 3, 4, 7, 8, 9, 11, 14, 15)
i. 4 : 1 MUX
ii. 2 : 1 MUX
Ans.
i. 4 : 1 MUX :
AB AB AB AB
I0 I1 I2 I3
(00) C D 0 4 8 12
(01) C D 1 5 9 13
(10) C D 2 6 10 14
(11) C D 3 7 11 15
First column (I0) = C D  CD  CD

= C ( D  D)  CD = C  CD
= CD
Second column (I1)
= CD  CD = C  D [ EX-NOR]
Third column (I2)
= CD  CD  CD
= C( D  D)  CD
= C  CD = C  D
Fourth column (I3)
= CD  CD
= C( D  D) = C
Logic diagram :
C
D I0
I1
4:1 F(A, B, C, D)
I2 MUX
I3
Select
A B lines
Fig. 4.
ii. Implementation using 2 : 1 MUX :
We have to use three variables as input of MUX and one variable
as select line
D D
I0 I1
ABC 0 1
ABC 2 3
ABC 4 5
ABC 6 7
ABC 8 9
ABC 10 11
ABC 12 13
ABC 14 15
First column (I0)

= ABC  ABC  ABC  ABC
= AC ( B  B)  A( BC  BC)
= AC  A( B  C )
Second column (I1)
= ABC  ABC  ABC  ABC  ABC  ABC
= BC ( A  A)  BC ( A  A)  BC( A  A)
= BC  BC  BC
= B (C  C)  BC
= B  BC
= BC
Logic diagram :
A
C
I0
B
C
2:1
F(A, B, C, D)
MUX
A
B
I1
C
Select line
D
Fig. 5.
e. Design Binary code to Gray code converter.

Ans. Truth table :
Binary code Gray code

D C B A G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

BA BA
00 01 11 10 00 01 11 10
DC DC
0 1 3 2 0 1 3 2
00 1 1 00 1 1
4 5 7 6 4 5 7 6
01 1 1 01
1 1
12 13 15 14 12 13 15 14
11 1 1 11
1 1
8 9 11 10 8 9 11 10
10 1 1
10
1 1
G0 = BA + BA = B  A G1 = CB + CB = C  B

BA BA
00 01 11 10 00 01 11 10
DC DC
0 1 3 2 0 1 3 2
00 00
4 5 7 6 4 5 7 6
01 01
1 1 1 1
11 12 13 15 14 11 12 13 15 14
1 1 1 1
8 9 11 10 8 9 11 10
10 10
1 1 1 1 1 1 1 1
G2 = DC + DC = C  D G3 = D
We get the simplified boolean expression for the code converter of
Binary to Gray code.
G0 = BA  BA  B  A
G1 = CB  CB  C  B
G2 = DC  DC  C  D
G3 = D
Logic diagram :
D C B A  Binary code
G3 G2 G1 G0  Gray code
Fig. 6.
SECTION-C
a. i. Draw a BCD adder circuit and explain its working.
Ans.
1. BCD adder is circuit that adds two BCD digits in parallel and produces
a sum digit which is also BCD. BCD numbers use 10 symbols (group
of 4 bits 0000 to 1001). BCD adder circuit must be able to do the
following and it is shown in Fig. 7.

3. If 4-bit sum is equal to or less than 9, the sum is a valid BCD
number and no correction is needed.
4. If the 4-bit sum is greater than 9 or if a carry is generated from the
sum, the sum is invalid BCD number. Then the digit 6 (0110)2
should be added to the sum to produce the valid BCD symbols.

K
Z 8 Z4 Z 2 Z1
Output
carry
C
C = K + Z8 Z4 + Z8 Z2
0
4-bit binary adder
S8 S4 S2 S1
Fig. 7. Block diagram of a BCD adder.
Z8 Z4 Z2 Z1 C S8 S4 S2 S1
0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 1 1
0 0 1 0 0 0 0 1 0 2
0 0 1 1 0 0 0 1 1 3
0 1 0 0 0 0 1 0 0 4
0 1 0 1 0 0 1 0 1 5
0 1 1 0 0 0 1 1 0 6
0 1 1 1 0 0 1 1 1 7
1 0 0 0 0 1 0 0 0 8
1 0 0 1 0 1 0 0 1 9
1 0 1 0 1 0 0 0 0 10
1 0 1 1 1 0 0 0 1 11
ii. Convert the SR flip-flop to JK flip-flop.

Ans.
1. The JK flip-flop is constructed by using SR flip-flop.
Truth table of JK flip-flop Excitation table of SR flip-flop

Flip-flop Present Next Present Next Flip-flop
inputs state state state state inputs
J K Qn Qn + 1 Qn Qn + 1 R S
0 0 0 0 0 0 × 0
0 0 1 1 0 1 0 1
0 1 0 0 1 0 1 0
0 1 1 0 1 1 0 ×
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
2. Form the conversion table
Required flip-flop Given flip-flop
Flip-flop inputs Present state Next state Flip-flop inputs
J K Qn Qn+1 R S
0 0 0 0 × 0
0 0 1 1 0 ×
0 1 0 0 × 0
0 1 1 0 1 0
1 0 0 1 0 1
1 0 1 1 0 ×
1 1 0 1 0 1
1 1 1 0 1 0
3. K-map simplification :
For R For S
KQn KQn
J 00 01 11 10 J 00 01 11 10
0 × 1 × 0 ×
0 1 3 2 0 1 3 2
1 1 1 1 1
×
4 5 7 8 4 5 7 8
4. The obtained boolean expression :
S = JQn and R = KQn
J S Q Qn
SR
CLK
Flip-flop
K R Q Qn
Fig. 8.
b. What do you mean by shift register ? What is the need of

shift register ? Draw and explain bidirectional shift
register.
Ans.
A. Shift registers :
The binary data in a register can be moved within the register from
one flip-flop to the other or outside it with application of clock
pulses. The registers that allow such data transfers are called shift
registers.
B. Need of shift register : A register is a sequential logic circuit with
two basic functions :
i. Temporary storage.
ii. Shifting capability.
C. Bidirectional shift register :
1. It consists of four D flip-flops, four OR gates, eight AND gates and
one NOT gate as shown in Fig. 9.
M
DR DL
A3 B3 A2 B2 A1 B1 A0 B0
D3 Q3 D2 Q2 D1 Q1 D0 Q0
CLK
Fig. 9.
Operation :
1. When mode control M = 1, all the A AND gates (A3, A2, A1, A0) are
enabled and the data at DR is shifted to the right when clock
pulses are applied.
2. When M = 0, all A gates are disabled and all B gates are enabled.
These enabled B gates allow data DL to be shifted to left.
3. M should be changed only when CLK = 0, otherwise the data
stored in the register may be changed.

a. i. Design a modulo-4 UP/DOWN counter using JK flip-flop.
Ans.
1. The count sequences of a modulo-4 up counter are 00, 01, 10 and 11.
The count sequence of a modulo-4 down counter is 11, 10, 01 and 00.
2. Two flip flops are required to design modulo-4 UP/DOWN counter.
State diagram :
00
1 1
0 0
11 01
0 0
1 1
10
Fig. 10.
3. When the control input is equal to 1, the counter is working as an
UP counter. When the control input is equal to 0, the counter is
working as a DOWN counter.
State table :
Control Present Next state Flip-flop input
input state
X QA QB QA +1 QB + 1 JA KA JB KB
0 0 0 1 1 1 × 1 ×
0 0 1 0 0 0 × × 1
0 1 0 0 1 × 1 1 ×
0 1 1 1 0 × 0 × 1
1 0 0 0 1 0 × 1 ×
1 0 1 1 0 1 × × 1
1 1 0 1 1 × 0 1 ×
1 1 1 0 0 × 1 × 1
Expression for J A Expression for K A

QAQB QAQB
X 00 01 11 10 X 00 01 11 10
0 1 3 2 0 1 3 2
× ×
0 1 0 × × 1
4 5 7 6 4 5 7 6
1 1
1 × × × × 1 ×
JA = X QB + XQB = X . Q B KA = X QB + XQB = X . Q B
Expression for JB Expression for K B

QAQB QAQB
X 00 01 11 10 X 00 01 11 10
0 1 3 2 0 1 3 2
0 1 × × 1 0 1 × × 1
4 5 7 6 4 5 7 6
1 1
1 × × 1 1 × × 1
JB = 1 KB = 1
Logic diagram :
(+ VCC)
JB QB JA QA
KB QB KA QA
Clock
X
Fig. 11. Modulo-4 binary UP/DOWN counter.
ii. Design a ripple decade counter using JK flip-flop.

Ans. 4-bit binary ripple down counter :
1. The 4-bit asynchronous counter is constructed by using JK flip-flop
(asynchronous counter are also called ripple counter).
2. The output QA must be externally connected to clock input of
flip-flop B.
3. The input count pulses are applied to clock input of flip-flop A.
Simultaneous divisions of 2, 4, 8, and 16 are performed at the QA,
QB, QC, QD outputs.
Timing diagram :
CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
QA
QB
QC
QD
Fig. 12.
Logic diagram :
M
M
High
JA QA JB QB JC QC JD QD
CLK A B C D
KA QA KB QB KC QC KD QD
Fig. 13.
4-bit ripple counter needs 4 flip-flop. To work in down mode M
should be high.
b. i. What is critical race and non-critical race ? How can they

be avoided ?
Ans. Critical and non-critical Condition :
non-critical race.
Critical race and non-critical race :
non-critical race.
Non-critical race :
x x
y1 y2 0 1 y 1y 2 0 1
00 00 11 00 00 11
01 11 01 01
11 11 11 01
10 11 10 11
(a) Possible transitions (b) Possible transitions

00 11 00 11  01
00 01  11 00 01
00 10  11 00 10  11  01
Fig. 14.
Critical race :
x x
0 1 0 1
y1y2 y1y2
00 00 11 00 00 11
01 01 01 11
11 11 11 11
10 10 10 10
( a) Possible transitions (b) Possible transitions

00 11 00 11
00 01 00 01  11
00 10 00 10
Fig. 15.
Method of avoided :
1. Race may be avoided by making a proper binary assignment to the
state variable.
2. The state variable must be assigned binary numbers in such a way
that only one state variable can change at any one time when a
state transition occurs in the flow table.
3. Race may be avoided by directing the circuit through intermediate
unstable state with a unique state variable change. Race around
condition is an example of race.
ii. Describe the hazards in digital circuits. How are these
removed ? Design a hazards free circuit of the following
Boolean function : F(A, B, C) = m(1, 2, 3, 5)
Ans.
A. Hazards :
propagation delays.
wrong stable state.
Elimination of hazards :
x1
x2
F (x1, x2, x3) = x2x3 + x1x2
x3
Fig. 16.
x2 x3
x1 00 01 11 10
0 1
0 1 3 2
1 1 1 1
4 5 7 6

Fig. 17.
F = x2 x3  x1 x2
x2 x3
x1 00 01 11 10
0 1
0 1 3 2
1 1 1 1
4 5 7 6

Fig. 18.

F = x2 x3  x1 x2  x1 x3
new term
x1 x1x2
x2
x3 F = x1x2 + x2x3 + x1x3

x2x3
x1x3

Fig. 19.

a. i. Describe the circuit and performance of CMOS inverter

and state the characteristics of CMOS.
Ans.
A. CMOS inverter :
1. It consists of an NMOS transistor Q1 and a PMOS transistor Q2.
The input is connected to the gates of both the devices and the
output is at the drain of both the devices. The positive supply voltage
is connected to the sources of the PMOS transistor Q2, and the
source of transistor Q1 is grounded.
2. When A is LOW (0 V). Gate to source voltage VGS2 of transistor Q2
is – 5 V, and gate to source voltage VGS1 of transistor Q1 is 0 V. So,
transistor Q2 acts as ON and transistor Q1 acts as OFF. Therefore,
the switching circuit shown in Fig. 20(b) results in Vo as logic HIGH
that is + 5 V.
+5 V +5 V +5 V
Q 2(ON)
Q2 Q2(OFF)
A=1
A=0 Vo = 5 V Vo = 0 V
A Vo
Q 1(ON)
Q 1(OFF)
Q1
(a) (b ) A = 0 (c ) A = 1
Fig. 20. (a) CMOS as inverter, (b) and (c) equivalent circuit.
3. When A is HIGH (+ 5 V), gate to source voltage VGS2 of transistor
Q2 is 0 V, and gate to source voltage VGS1 of transistor Q1 is + 5 V.
So, transistor Q2 acts as OFF and transistor Q1 acts as ON.
Therefore, the switching circuit shown in Fig. 20(c) results with Vo
as logic LOW that is 0 V.
Table 5. Operation of CMOS inverter.
Input, A p-channel n-Channel Output, Vo
MOSFET, Q1 MOSFET, Q2
LOW (0 V) ON OFF + 5 V (HIGH)

HIGH (5 V) OFF ON 0 V (LOW)
Truth table :
A Vo
0 1
1 0
B. Characteristics of CMOS :
i. Supply voltage : The 4000 and 74C series can operate with VDD
values ranging from 3 to 15 V. The 74HC and 74HCT series can
operate with VDD values ranging from 2 to 6 V.
ii. Voltage levels : When a CMOS output drives only a CMOS input
and CMOS gate has an extremely high input resistance, the current
drawn is almost zero and, therefore, the output voltage levels will
be very close to zero for LOW state and VDD for HIGH state.
iii. Power dissipation : When a CMOS circuit is in a static state, its
power dissipation per gate is extremely small, but it increases with
increase in operating frequency and supply voltage level. For DC,
CMOS power dissipation is only 2.5 nW per gate when VDD = 5 V,
and it increases to 10 nW per gate when VDD = 10 V.
iv. Switching speed : The speed of the CMOS gate increases with
increase in VDD. The increase in VDD results in increase in power
dissipation too.
Unused inputs : The CMOS inputs should never be left
disconnected. All CMOS inputs have to be tied either to a fixed
voltage level (0 V or VDD) or to another input.
ii. Differentiate between PLA and PAL. Realize the full adder
circuit using PAL.
Ans.
A. Difference :
S. No. PAL PLA
1. It is moderately expensive It is expensive than PAL and PROM
and moderately complicated. and complicated to use.
2. In this, only the AND array In this, both AND and OR arrays
is programmable, OR array are programmable.
is fixed.
3. It is easier to program It is complicated to program because
because only the AND gates both the AND and OR gates are
are programmable. programmable.
4. It is less flexible due to fixed It is more flexible than PAL.
OR gates.
B. Full adder using PAL : There are two functions used for the
implementation of full adder :
S = ABC  ABC  ABC  ABC
C = ABC  ABC  ABC  ABC
A A B B C C
× × ×
× × × S
× × ×
× × ×
A
× × ×
× × × C
× × ×
× × ×
Fig. 21.
b. i. Discuss the concept of field programmable gate array

(FPGA). Discuss the various structures of FPGA.
Ans.
A. Field Programmable Gate Array :
1. FPGA is high capacity PLD (programmable logic device). The gate
array of FPGA has the ability to be programmed for a function by
the user instead of the manufacturer of device.
2. FPGA consists of three configurable (programmable) logic modules
(LMs) : configurable logic blocks (CLBs), input and output blocks
and switching matrix for interconnection.
3. The CLB consists of a combinational logic array, data multiplexer
(MUX) and flip-flops. The combinational array function is performed
by look-up table (LUT).
B. Structures of FPGA :
i. Programmable logic structure :
1. The programmable logic structure of FPGA consists of a two-
dimensional array of CLBs.
2. Each CLB typically contains one or two flip-flops to allow
implementation of sequential logic.
3. Large designs are partitioned and mapped to a number of CLBs
with each CLB configured (programmed) to perform a particular
function.
4. These CLBs are then connected together to fully implement the
target design.
ii. Programmable routing structure :

1. To allow for flexible interconnection of CLB, FPGA has three
programmable routing resources.
2. Vertical and horizontal routing channels which consist of different
length of wires that can be connected together if needed.
3. These channels run vertically and horizontally between columns
and rows of CLBs as shown in the Fig. 22.
Vertical
channel
Programmable Horizontal
input / output channel
Configurable
logic block(CLB)
Switch box
Horizontal
connections
Vertical channel
Fig. 22. Programmable structure of
field programmable logic array (FPGA).
4. Connection boxes, which are set of programmable links, can connect
input and output pins of the CLBs to wires of the vertical or the
horizontal routing channels.
5. Switch boxes are located at the intersection of the vertical and
horizontal channels.
6. These are a set of programmable links that can connect wire
segments in the horizontal and vertical channels.
iii. Programmable input/output :
1. These are mainly buffers that can be configured either as input
buffers or output buffers or input/output as shown in Fig. 23.
2. These allow the pins of the FPGA chip to function either as input
pins or output pins or input/output pins.
iv. Configurable logic blocks :
1. There are a number of CLBs in an FPGA organized as an array of
rows and columns. The logic blocks are connected to the I/O blocks
through common row / column programmable interconnects.
2. The common row / column interconnects are known as global
interconnects.
3. A logic block consists of a number of LMs. The LMs are the basic
logic elements in a FPGA. The LMs within a CLB are connected
through local programmable interconnects.
v. Logic module :
1. A logic module (LM) consists of a LUT, a D-type flip-flop and a
MUX. Most of the FPGAs are based on 4-input LUT. Fig. 23 shows
a block diagram of a LM with 4-input LUT.
2. Output of the LUT becomes the output of the LM either directly or
through D-type flip-flop. Thus, the output can be configured for
combinational or registered (i.e., through flip-flop).
Four-input Output
MUX
Input look-up D
table Flip-flop
(LUT) Clock
Select lines
Fig. 23. Block diagram of logic module.
ii. Tabulate the truth table for 8 × 4 ROM that implements

the Boolean function :
A(x, y, z) = m(1, 2, 4, 6)
B(x, y, z) = m(0, 1, 6, 7)
C(x, y, z) = m(2, 6)
D(x, y, z) = m(1, 2, 3, 5, 7)
Ans. Truth table for the given function :
Inputs Outputs
x y z A B C D
0 0 0 0 1 0 0
0 0 1 1 1 0 1
0 1 0 1 0 1 1
0 1 1 0 0 0 1
1 0 0 1 0 0 0
1 0 1 0 0 0 1
1 1 0 1 1 1 0
1 1 1 0 1 0 1
Logic diagram :
The ROM is programmed for truth table.
0 ×
1 × × ×
x 2 × × ×
y
Decoder 3 ×
4 ×
z 5 ×
6 × × ×
7 × ×
A B C D
Fig. 24.

Y = X1X2 + (X1 + X2)Y
Z=Y
ii. Derive the transition table and output map.
iii. Describe the behavior of the circuit.
Ans.
State table :
0 0 0 0 0 0 Yes 0
0 0 1 0 0 0 No 0
0 1 0 0 1 0 Yes 0
0 1 1 0 1 1 Yes 1
1 0 0 1 0 0 Yes 0
1 0 1 1 0 1 Yes 1
1 1 0 1 1 1 No 1
1 1 1 1 1 1 Yes 1
i. Logic diagram :
X1
X2
Y=Z
Fig. 25.

X1X2 Unstable state
00 01 11 10
Y Stable state
0 0 0 1 0
1 0 1 1 1
iii. Output map :

X1X2
00 01 11 10
Y
0 0 0 1 0
1 1 1 1 1

X 1X 2
Y 00 01 11 10
S0 S0/0 S0/0 S1/1 S0/0
S1 S0/0 S1/1 S1/1 S1/1
b. i. The code 101101010 is received, correct any errors. There

are four parity bits and odd parity is used.
ii. Draw a full subtractor circuit using NAND gate.

Ans. Full subtractor using only NAND gates
D = A  B  Bin  ( A  B)( A  B) Bin Bin ( A  B) Bin
Bout = AB  Bin ( A  B) = AB  Bin ( A  B)
= AB . Bin ( A  B)  B( A  B) Bin  Bin  ( A  B) 
Bout = B AB Bin  Bin ( A  B)

By using the above expressions for D and Bout, the full subtractor
is implemented using only NAND gates as shown in Fig. 26.
A
B D
Bin
Bout
Fig. 26. Full subtractor using only NAND gate.


a. Derive the state table and state diagram for the sequential
A
x
DA QA A
B A A
QA A B Y
x
A DB QB
x B
B
QB B
Cp
Fig. 27.
Ans.
1. The behaviour of circuit is determined by the following Boolean
expression,
Y = AB  x ...(1)
DA = Ax + Bx ...(2)
DB = Ax ...(3)
2. From eq. (1), (2) and (3) then state table will be
Table 6.

A B x=0 x=1 x=0 x=1
0 0 0 0 0 1 1 0
0 1 0 0 1 1 1 0
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 1
3. We draw state diagram with the help of state table
1/0 0/1
00
0/1 0/1
01 0/1 11
1/0 1/1
10
1/0
Fig. 28.
b. Draw the reduced state table and reduced state diagram

0/0
a
1/0 0/0
0/0 0/0 0/0
b c
1/0
g 1/1 d 0/0
e
0/0 1/1
f 1/1
1/1
Fig. 29.
Ans.
1. The given Fig. 29 has seven states, one input and one output. The
2. From the state table, it is clear that states e and g are equivalent.
So the state g is replaced by state e.
State table :
x=0 x=1 x= 0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
Both are equivalent
same next state and
x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e f 0 1
Both are
states e
f f 0 1
3. From the reduced table, states d and f are equivalent, hence f can
be replaced by d and it can be removed.
Reduced table :
x=0 x=1 x=0 x=1
a a b 0 0
b c d 0 0
c a d 0 0
d e d 0 1
e a d 0 1
4. The state diagram of the reduced state table is shown in Fig. 30.
0/0
0/0
e a
1/0
0/0 1/1
0/0
1/0
d b
1/0 c 0/0
1/1
Fig. 30. State diagram.

SP–1 B (EC-Sem-3) Digital System Design
B. Tech.
DIGITAL SYSTEM DESIGN
Note : Attempt all Section. If required any missing data; then choose
suitably.
SECTION-A
1. Attempt all questions in brief. (2 × 10 = 20)
a. The solution to the quadratic equation k2 – 11k + 22 = 0 are
x = 3 and x = 6. What is the base of the number system ?
b. Simplify the expression F (A, B, C, D) = ACD + AB + D by

K-Map.
c. Construct half subtractor using logic gates.
d. Implement a 4:1 multiplexer using 2:1 multiplexer.
e. What do you mean by race around condition in JK

Flip-Flop ?
f. Distinguish between Latch and Flip-Flop.
g. What is logic family ? Give the classification of logic families

in brief.
h. Describe figure of merit & noise immunity of TTL & CMOS

ICs.
i. What are the advantages and disadvantages of flash type

ADC ?
j. The basic step of a 9-bit DAC is 10.3 mV. If 000000000

represents 0 Volts, what is the output for an input of
101101111 ?
SECTION-B
a. Design an excess-3 to BCD code converter.
b. Implement a full adder by using 8:1 multiplexer.
c. Design a sequential circuit with two Flip-Flops, A & B and

one input x. When x = 0, the State of the circuit remains the
same when x = 1 the circuit passes through the state
transitions from 00 to 01 to 11 to 10 back to 00 and repeat.
d. Compare TTL and CMOS logic families and also draw CMOS
NOR gate.
e. Explain the operation of successive approximation ADC.

Discuss it merits and demerits.
SECTION-C
3. Attempt any one of the following : (10 × 1 = 10)
a. Minimize the logic function using Quine-McCluskey
Method
F(A, B, C, D, E) = m(8, 9, 10, 11, 13, 15, 16, 18, 21, 24, 25, 26, 27,
30, 31)
b. Simplify the logic expression using K-Map F(A, B, C, D,
E, F)
= m(0, 5, 7, 8, 9, 12, 13, 23, 24, 25, 28, 29, 37, 40, 42, 44, 46, 55, 56,
57, 60, 61)
a. Design a 4-bit parallel binary Adder/Subtractor circuit.
b. Design a 4-bit comparator circuit using logic gates.
a. Discuss Mealy and Moore FSM. What do you mean by
excitation table ?
b. For the given state diagram design the circuit using T
flip flop.
000
0/0 1/1
010
1/1
0/0 0/0 1/1
110 001
1/0
1/1
0/0 100
0/0
Fig. 1.

a. Draw three input standard TTL NAND gate circuit and
explain its operation.
b. Implement the following function using PLA

F1 = m(0, 3, 4, 7)
F2 = m(1, 2, 5, 7)

a. With a neat diagram explain the operation of R-2R DAC.
b. With a neat sketch explain the operation of Flash ADC.

Note : Attempt all Section. If required any missing data; then choose
suitably.
SECTION-A
1. Attempt all questions in brief. (2 × 10 = 20)
a. The solution to the quadratic equation k2 – 11k + 22 = 0 are
x = 3 and x = 6. What is the base of the number system ?
Ans.
1. Suppose the base of the number is b. The given quadratic equation
is
(x2 – 11x + 22)b = 0 ...(1)
2. The solution of quadratic equation is,
x = 3 and x = 6
3. The quadratic equation formed with these roots is
(x – 3) (x – 6) = x2 – (6 + 3) x + (6 × 3) ...(2)
4. Comparing eq. (2) with the given quadratic eq. (1)
(9)10 = (11)b
b1 × 1 + b0 × 1 = 9
b + 1 = 9, b=8
also, (18)10 = (22)b
b1 × 2 + b0 × 2 = 18
2(b + 1) = 18, b = 8
Hence, the base of the number system is 8.
b. Simplify the expression F (A, B, C, D) = ACD + AB + D by

K-Map.
Ans. Given, F(A, B, C, D) = ACD + AB  D
F(A, B, C, D) = A( B  B)CD  AB(C  C) ( D  D) 
( A  A) ( B  B) (C  C) D
= ABCD  ABCD  ABCD  ABCD  ABC D  ABC D  ABC D
 ABC D  ABC D  A B C D  A B C D  A B C D  A B C D
+ A BC D
= 1111 + 1011 + 0111 + 0101 + 0110 + 0100 + 1110 + 0110 + 1010 +
0010 + 1100 + 1000 + 0100 + 0000
= m15 + m11 + m7 + m5 + m6 + m4 + m14 + m10 + m2 + m12 + m8 + m0
= m(0, 2, 4, 5, 6, 7, 8, 10, 11, 12, 14, 15)
K-map :
CD
AB CD CD CD CD
AB 1 1
0 1 3 2
AB 1 1 1 1
4 5 7 6
AB 1 1 1
8 9 11 10
AB 1 1 1 14
12 13 15
F(A , B, C, D) = D + A B + A C
c. Construct half subtractor using logic gates.

Ans.
A
B D
Bo
Fig. 1. Half subtractor.
d. Implement a 4:1 multiplexer using 2:1 multiplexer.

Ans.
A
2×1
B mux
2×1 output
mux
C
2×1
mux
D
s1 s0
Fig. 2.
e. What do you mean by race around condition in JK

Flip-Flop ?
f. Distinguish between Latch and Flip-Flop.

Ans.
1. Sto rage e le me nt that Storage element that are
operates with signal levels. controlled by clock transition.
g. What is logic family ? Give the classification of logic families

in brief.
Ans. Logic family : A logic family is a circuit technology that can be
used to create many different types of gates : inverter, NAND,
NOR, etc.
Classification :
i. Bipolar logic family : In this logic family, the current flows
because of both electrons and holes being charge carriers.
ii. Unipolar logic family : It includes p-channel metal oxide
semiconductor field-effect transistor (PMOS), n-channel metal
oxide field effect transistor (NMOS) and CMOS. The current flow
due to any one types of carrier.
h. Describe figure of merit & noise immunity of TTL & CMOS

ICs.
Ans. Figure of merit : Figure of merit is a product of propagation
delay and power dissipation. It is measured in terms of Pico-Joules.
Noise immunity : The noise immunity of digital circuit is defined
as the ability of a digital circuit to tolerate the noise signal.
i. What are the advantages and disadvantages of flash type

ADC ?
Ans. Advantages :
1. It is the fastest type of ADC because the conversion is performed
simultaneously through a set of comparators, hence referred as
flash type ADC.
2. The construction is simple and easier to design.
Disadvantages :
1. It is not suitable for higher number of bits.
2. To convert the analog input voltage into a digital signal of n-bit
output, (2n – 1) comparators are required. The number of
comparators required doubles for each added bit.
j. The basic step of a 9-bit DAC is 10.3 mV. If 000000000

represents 0 Volts, what is the output for an input of
101101111 ?
Ans. The output voltage for input 101101111 is

10.3 × 10–3 × (1 × 28 + 0 × 27 + 1 × 26 + 1 × 25 + 0 × 24 + 1 × 23 + 1 × 22
+ 1 × 21 + 1 × 20) = 10.3 × 367 × 10–3 = 3.78 V
SECTION-B

a. Design an excess-3 to BCD code converter.
Ans. Truth table :
Excess-3 code BCD code

E3 E2 E1 E0 B3 B2 B1 B0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1
The unused Excess-3 codes are 0000, 0001, 0010, 1101, 1110 and
1111. So place X (Don’t Care condition) for the corresponding codes.

E1E0 E1E0
00 01 11 10 00 01 11 10
E3E2 E3E2
0 1 3 2 0 1 3 2
00 × × × 00
× × ×
4 5 7 6 4 5 7 6
01 1 1 01 1 1
12 13 15 14 12 13 15 14
11 1 × × × 11
× × ×
8 9 11 10 8 9 11 10
10 1 1 10 1 1
B0 = E0 B1 = E1 E0 + E1 E0 = E 1  E 0

E1E0 E1E0
00 01 11 10 00 01 11 10
E3E2 E3E2
0 1 3 2 0 1 3 2
00 × × × 00
× × ×
4 5 7 6 4 5 7 6
01 01
1
12 13 15 14 12 13 15 14
11 11
× × × 1 × × ×
8 9 11 10 8 9 11 10
10 10
1 1 1 1
B2 = E2 E1 + E2 E1 E0 + E3 E1 E0 B3 = E3 E2 + E3 E1 E0
Logic diagram :
E3 E2 E1 E0
B0
B1
B2
B3
Fig. 3.
b. Implement a full adder by using 8:1 multiplexer.

Ans.
Truth table
Inputs A B C S C
I0 0 0 0 0 0
I1 0 0 1 1 0
I2 0 1 0 1 0
I3 0 1 1 0 1
I4 1 0 0 1 0
I5 1 0 1 0 1
I6 1 1 0 0 1
I7 1 1 1 1 1
MUX implementation for sum MUX implementation for carry

0 I0 0 I0
I1 I1
1
I2 1 I2
I3 Sum I3
8:1 8:1 Carry
I4
MUX I4 MUX
I5
I6 I5
I7 I6
I7
A B C
Select line A B C
Select line
Fig. 4.
c. Design a sequential circuit with two Flip-Flops, A & B and

one input x. When x = 0, the State of the circuit remains the
same when x = 1 the circuit passes through the state
transitions from 00 to 01 to 11 to 10 back to 00 and repeat.
Ans.
Present state Input Next state Output
A B x A B DA DB
0 0 0 0 0 0 0
0 0 1 0 1 0 1
0 1 0 0 1 0 1
0 1 1 1 1 1 1
1 0 0 1 0 1 0
1 0 1 0 0 0 0
1 1 0 1 1 1 1
1 1 1 1 0 1 0
Bx Bx
A 00 01 11 10 A 00 01 11 10
1 1 1 1
0 0
1 1 1 1 1 1
DA = Ax + Bx DB = Ax + Bx
Fig. 5.
The circuit diagram is shown in Fig. 6.
B
x D Q A
A
A
D Q B
B
Fig. 6.
d. Compare TTL and CMOS logic families and also draw CMOS
NOR gate.
Ans.
A. Comparison :
S. No. Parameter CMOS TTL
1. Device used N channel and P Bipolar junctio n
channel MOSFET transistor
2. Noise immunity Better than TTL Less than CMOS
3. Switching speed Less than TTL Faster than CMOS
4. Power dissipation 0.1 mW 10 mW
per gate
5. Spee d powe r 0.7 pJ 100 pJ

product
6. Fan-out 50 10
7. Po we r supply 3-15 V Fixed 5 V
voltage
8. Application Portable instrument Laboratory
where batte ry instruments.
supply is used.
B. CMOS NOR gate :

1. Fig. 7 shows a CMOS two-input NOR gate. Here, p-channel
MOSFETs Q1 and Q2 are connected in series and n-channel
MOSFETs Q3 and Q4 are connected in parallel.
VDD = +5 V
A
Q1
Q2
B
Vo
Q3 Q4
Fig. 7. CMOS as NOR.
e. Explain the operation of successive approximation ADC.

Discuss it merits and demerits.
Ans.
A. Successive approximation ADC :
Start EOC
Va –
SAR CLK
+
Vd d1 d2 d8
d1(MSB)
d2
d8
DAC
Fig. 8. Functional diagram of the successive approximation ADC.
1. The successive approximation technique uses a very efficient code

strategy to provide n-bit conversion in n-clock periods.
Working :
1. With the arrival of the START command, the SAR sets the MSB
d1 = 1 with all other bits to zero so that the trial code is 10000000.
2. The output Vd of the DAC is now compared with analog input Va. If
Va is greater than the DAC output Vd then 10000000 is less than
the correct digital representation.
3. The MSB is left at ‘1’ and the next lower significant bit is made ‘1’
and further tested.
4. However, if Va is less than the DAC output, then 10000000 is greater
than the correct digital representation.
5. So reset MSB to ‘0’ and go on to the next lower significant bit. This
procedure is repeated for all subsequent bits, one at a time, until all
bit positions have been tested.
6. Whenever the DAC output crosses Va, the comparator changes
state and this can be taken as the end of conversion (EOC) command.
B. Merits of successive approximation ADC :
1. Capable of high speed and reliable.
2. Medium accuracy compared to other ADC types.
3. Good tradeoff between speed and cost.
C. Demerits of successive approximation :
1. Higher resolution successive approximation ADC’s will be slower.
2. Speed limited to ~ 5 Msps.
SECTION-C
3. Attempt any one of the following : (10 × 1 = 10)

a. Minimize the logic function using Quine-McCluskey
Method
F(A, B, C, D, E) = m(8, 9, 10, 11, 13, 15, 16, 18, 21, 24, 25, 26, 27,
30, 31)
Ans.
1. Given, F(A, B, C, D, E) = m(8, 9, 10, 11, 13, 15, 16, 18, 21, 24, 25,
26, 27, 30, 31)
2. Arrange minterms according to categories of 1’s as shown in
table 1.
Table 1.
No of 1s Minterms Binary Minterms Binary Minterm Binary Minterms Binary
(2 cell) (4 cell) (6 cell)
1. m8 01000 8, 9 0100_ 8, 9, 10, 11 010__ 8, 9, 10, 11, 24, 25, 26, 27 _10__
m 16 10000 8, 10 010_0 8, 9, 24, 25 _100_
2.
SP–13 B (EC-Sem-3)
m9 01001 8, 24 _1000
16, 18 100_0 8, 10, 24, 26 _10_0
m 10 01010
16, 24 1 _ 0 0 0  16, 18, 24, 26 1_0_0
m 18 10010
9, 11 0 1 0 _ 1  9, 11, 13, 15 01__1
m 24 11000 9, 13 0 1 _ 0 1  9, 11, 25, 27 _10_1
3. 9, 25 _ 1 0 0 1  10, 11, 26, 27 _101_
m 11 01011
10, 11 0 1 0 1 _  24, 25, 26, 27 110__
m 13 01101 10, 26 _1010
m 21 10101 18, 26 1_010
m 25 11001 24, 25 1 1 0 0 _  11, 15, 27, 31 _1_11
m 26 11010 24, 26 1 1 0 _ 0  26, 27, 30, 31 11_1_
4. m 15 01111 11, 15 01_11
11, 27 _1011
m 27 11011 13, 15 011_1
25, 27 110_1
m 30 11110 26, 27 1101_
5. m 31 11111 26, 30 11_10
15, 31 _1111
27, 31 11_11
30, 31 1111_
Digital System Design

4. Now we prepare a prime implicant chart to determine essential
prime implicant as follows :
Table 2.
Prime
Minterms Binary 8 9 10 11 13 15 16 18 21 24 25 26 27 30 31
implicant
18, 26 ACDE 1_010 × ×
26, 30 ABCD 1101_ × ×
27, 31 ABDE 11_11 × ×
16, 18, 24, 26 ACE 1_0_0 × × × ×
9, 11, 13, 15 ABE 01__1 × × × ×
11, 15, 27, 31 BDE _1_11 × × × ×

26, 27, 30, 31 ABD 11_1_ × × × ×
8, 9, 10, 11, 24, BC _10__ × × × × × × × ×
25, 26, 27
F = ABE + AC E + ABD + BC + ACDE
b. Simplify the logic expression using K-Map :

F(A, B, C, D, E, F) = m(0, 5, 7, 8, 9, 12, 13, 23, 24, 25, 28, 29, 37, 40,
42, 44, 46, 55, 56, 57, 60, 61)
Ans.
1. Group 1 and group 2 are two pairs of 1’s in the first 16-cell map.
2. Group 3 is formed by two isolated 1’s from first 16-cell map and
third 16-cell map.
3. Group 4 is a combination of two quads from first 16-cell and second
16-cell map.
4. Similarly group 5 is a combination of two quads from second 16-cell
map and fourth 16-cell map.
5. Group 6 is again a combination is isolated 1’s from second and
fourth 16-cell maps.
6. Finally group 7 is a quad within the third 16-cell map.
Group 2
AB (ABCDF) AB
EF EF
CD 00 01 11 10 CD 00 01 11 10
00 1 00
0 1 3 2 16 17 19 18
01 1 1 01 1
Group 1 4 5 7 6 20 21 23 22
ABDEF 1 1 1 1
11 11
12 13 15 14 28 29 31 30
Group 4
10 1 1 (ACE) 10 1 1
8 9 11 10 24 25 27 26
Group 3 Group 5 Group 6
(BCDEF) (BCE) (BCDEF)
EF AB EF AB
CD 00 01 11 10
CD 00 01 11 10
00 00
32 33 35 34 48 49 51 50
01 1 01 1
36 37 39 38 52 53 55 54
11 1 1 11 1 1
44 45 47 46 60 61 63 62
10 1 1 1 1
10
40 41 43 42 56 57 59 58
Group 7
(ABCF)
The expression is,
F = ABDEF  ABCDF  BCDEF
 ACE  BCE  BCDEF  ABCF

a. Design a 4-bit parallel binary Adder/Subtractor circuit.
Ans.
1. The sum of two n-bit binary numbers, A and B, can be generated
in two ways: either in a serial fashion or in parallel.
2. The series addition method uses only one full-adder circuit and a
storage device to hold the generated output carry.
3. The pair of bits in A and B are transferred serially, one at a time,
through the single full-adder to produce a string of output bits for
the sum.
4. The stored output carry from one pair of bits is used as an input
carry for the next pair of bits.
5. The parallel method uses n full-adder circuits, and all bits of A and
B are applied simultaneously.
6. A binary parallel adder is a digital function that produces the

arithmetic sum of two binary numbers in parallel.
7. It consists of full-adders connected in cascade, with the output
carry from one full-adder connected to the input carry of the next
full-adder.
B4 A4 B3 A3 B2 A2 B1 A1
C5 C4 C3 C2 C1
FA FA FA FA
S4 S3 S2 S1
Fig. 9. 4-bit full adders.
b. Design a 4-bit comparator circuit using logic gates.

Ans.
A = A3 A2 A1 A0
B = B3 B2 B1 B0
xi = Ai Bi  Ai Bi ; i = 0, 1, 2, 3.
xi = 1, if A = B
xi = 0, otherwise,
A3
x3
B3
A2
x2
B2
(A < B)
A1
x1
B1
A0
x0
(A > B)
B0
(A = B)

a. Discuss Mealy and Moore FSM. What do you mean by
excitation table ?
Ans.
A. Mealy Model :
1. When the output of the sequential network depends on both the
present state of flip-flop(s) and on the input(s), the sequential circuit
is referred to as Mealy model.
2. Fig. 11 shows the sample Mealy model.
X
X JA QA JB QB
CP A B
1 KA QA KB QB
Fig. 11. Example of Mealy model.

3. As shown in the Fig. 12, the output of the circuit is derived from the
combination of present state of flip-flops and input(X) of the circuit.
4. Looking at Fig. 12, we can easily realize that, changes in the input
within the clock pulses cannot affect the state of the flip-flop.
However, they can affect the output of the circuit.
5. If the input variations are not synchronized with the clock, the
derived output will also not be synchronized with the clock and we
get false output (as it is synchronous sequential network).
6. The false outputs can be eliminated by allowing input to change
only at the active transition of the clock (in our example HIGH-to-
LOW).
7. In general form the Mealy model can be represented with its block
schematic as shown in Fig. 12.
Output
Outputs
Inputs Next decoder
state Memory
decoder elements
Fig. 12. Mealy circuit model.

B. Moore Model :
1. When the output of the sequential network depends only on the
present state of the flip-flop, the sequential network is referred to
as Moore model.
2. Fig. 13 shows a sequential network which consists of two JK
flip-flop and AND gates.
X
X JA QA JB QB
CP A B
1 KA QA KB QB
Fig. 13. Example of Moore model.

3. The network has one input X and one output Y.
4. As shown in the Fig. 14, input is used to determine the inputs of the
flip-flops.
5. It is not used to determine the output.
6. The output is derived using only present states of the flip-flops or

combination of it (in this case QA QB ).
7. In general form the Moore model can be represented with its block
schematic as shown in Fig. 14 (a) and (b).
8. In the Moore model, as output depends only on present state of the
flip-flops, it appears only after the clock pulse is applied, i.e., it
varies in synchronism with the clock input.
Inputs Next Memory

Outputs
state elements
decoder
(a) Moore model.
Next Output
Inputs Memory
state decoder Outputs
elements (combinational
decoder
circuit)
(b) Moore circuit model with an output decoder.
Fig. 14.
C. Excitation table :
1. An excitation table is a tabular representation of X and Q at the
FFs and of Y as per F0 for the combination circuit at the output
stages.
2. It gives present states and the inputs given at the memory section.
It also gives the output that follows the excitations at the memory
section.
b. For the given state diagram design the circuit using T

flip flop.
000
0/0 1/1
010
1/1
0/0 0/0 1/1
110 001
1/0
1/1
0/0 100
0/0
Fig. 15.
Ans. Excitation table :
QA QB QC x TA TB TC QA* QB* QC* y
0 0 0 0 1 1 0 1 1 0 0
0 0 0 1 0 0 1 0 0 1 1
0 0 1 0 0 1 1 0 1 0 0
0 0 1 1 1 1 1 1 1 0 0
0 1 0 0 0 0 0 0 1 0 0
0 1 0 1 0 1 0 0 0 0 1
0 1 1 0 × × × – – – –
0 1 1 1 × × × – – – –
1 0 0 0 0 0 0 1 0 0 0
1 0 0 1 1 0 1 0 0 1 1
1 0 1 0 × × × – – – –
1 0 1 1 × × × – – – –
1 1 0 0 0 1 0 1 0 0 0
1 1 0 1 1 0 0 0 1 0 1
1 1 1 0 × × × – – – –
1 1 1 1 × × × – – – –
1. For TA(QA, QB, QC, x) = m(0, 3, 9, 13) + d (6, 7, 10, 11, 14, 15)
Qcx
QAQB 00 01 11 10
00 1 1
0 1 3 2
01
4 5 7 6
11 1
12 13 15 14
10 1
8 9 11 10
TA = Q A QBQCx + QAQBQCx + QAQCx
2. For TB(QA, QB, QC, x) = m(0, 2, 3, 5, 12) + d (6, 7, 10, 11, 14, 15)
Qcx
QAQB 00 01 11 10
00 1 1 1
0 1 3 2
01 1
4 5 7 6
11 1 12 13 15 14
10
8 9 11 10
TB = QA QBQC + QA QB x + QA QBQC x + QAQBQC x
3. For TC(QA, QB, QC, x) = m(1, 2, 3, 9) + d (6, 7, 10, 11, 14, 15)
Qcx
QAQB 00 01 11 10
00 1 1 1
0 1 3 2
01
4 5 7 6
11
12 13 15 14
10 1
8 9 11 10
TC = QA QBQC + QBQC x
x
TA QA
QA
TB QB
QB
TC QC
QC
Fig. 16.

a. Draw three input standard TTL NAND gate circuit and
explain its operation.
Ans.
1. The circuit of the two-input TTL NAND gate is shown in Fig. 17.
The input transistor, Q1 is a multiple emitter transistor.
+VCC
RC 130 
RC 4
RB 4 k 2 1.6 k
1
IC
2
Q4
TTL
multiple
emitter
Q1 Q2 DT
A
B Vo
DA DB Q3
RE 1 k
2
Fig. 17. TTL NAND gates.


3. Transistors Q3 and Q4 form a totem-pole arrangement. Diodes, DA
and DB protect transistor, Q1 from being damaged by the negative
4. When negative spikes appear at the input terminals, the diodes
conduct and bypass the spikes to ground.
5. Diode DT ensures that transistors, Q3 and Q4 do not conduct
Operation :
1. A LOW voltage at either emitter E1 or emitter E2 forward-biases
the corresponding diode D1 or D2 and reverse-biases diode D3 which
is a base-collector junction of transistor Q1. There is no flow of
current from base to collector of transistor Q1.
2. A LOW voltage on both emitters of transistor Q1 does the same
action.
3. A HIGH voltage on both emitters reverse-bias both input diodes D1 and
D2 and forward bias D3. The current flows from base to collector of
transistor Q1.
Base, B
Diode, D 1 Diode, D 3
Emitter, E1
Collector, C
Diode, D 2
Emitter, E2
Fig. 18. Diode equivalent of TTL multiple emitters.
Table 3. Operation of TTL NAND gate

b. Implement the following function using PLA

F1 = m(0, 3, 4, 7)
F2 = m(1, 2, 5, 7)
Ans. The given boolean expression is
F1 = m(0, 3, 4, 7)
F2 = m(1, 2, 5, 7)
For F1 : For F 2 :
BC BC
A 00 01 11 10 A 00 01 11 10
1 1 1 1
0 0 1 3 2 0 0 1 3 2
1 1 1 1
1 1 8
4 5 7 4 5 7 6
F1 = B C + BC F 2 = B C + ABC + A B C
Fig. 19.
PLA Table :
Product Input Output

term
A B C F1 F2
BC – 0 0 1 –
BC – 1 1 1 –
BC – 0 1 – 1
ABC 1 1 1 – 1
ABC 0 1 1 – 1
Implementation :
A B C
BC
BC
BC
ABC
ABC
F1 F2
Fig. 20.

a. With a neat diagram explain the operation of R-2R DAC.
Ans.
1. This network uses resistors of only two values R and 2R. The
inputs to the resistor network are applied through digitally controlled
switches.
RF
R R 2R
–
+ Vo
2R 2R 2R 2R
LSB
MSB
0 1 0 1 0 1
VR VR VR
Fig. 21.
2. Consider a 3 bit R-2R Ladder D/A network. Let us assume a digital
input of 001. The equivalent circuit becomes as shown in Fig. 22.
X Y Z
R R 2R
2R 2R 2R 2R
X Y Z
VR
Fig. 22.
3. Applying Thevenin’s theorem at point XX', we get
Y Z
R X R R 2R
VR
2 2R 2R
X
Y Z
Fig. 23.
4. Applying Thevenin's theorem at YY', we get
R Y R Z 2R
VR
2R
22
Y Z
Fig. 24.
5. Applying Thevenin's theorem at ZZ', we get
R Z 2R
VR
3
2
Z
Fig. 25.
6. The equivalent resistance is 3R in each case. The circuit reduces to
VR 3R RF
3
2
VR 3R
2
–
2 + Vo
VR 3R
2
Fig. 26.
7. The output voltage is given as
 Rf VR Rf VR Rf VR 
Vo =   b  b  b
 3R 23 0
3R 2 2 1
3 R 21 2 
Rf VR
=  [4 b2  2b1  b0 ]
3 R 23
8. The number of resistors required for N-bit D/A converter is 2N in
the case of R-2R ladder D/A converter.
b. With a neat sketch explain the operation of Flash ADC.

Ans. The commonly used A/D converter is parallel or flash converter. A
3-bit parallel comparator A/D converter is shown in Fig. 27.
Working :
1. Let Va is the input analog voltage to be converted into digital form.
The reference voltage like Vr1, Vr2, ….. are generated using resistor
network.
2. Va is compared simultaneously with the reference voltage by using
comparators.
V
R/2
Vo
Vr7 = 13/14 V –
+ C7
R
Vr6 = 11/14 V –
+ C6
R
Vr5 = 9/14 V – L D
+ B1
R C5 A E
Vr4 = 7/14 V – T C Digital
+ C O B2
C4 output
R H D
Vr3 = 5/14 V –
E E B0
+ C3
R S R
Vr2 = 3/14 V –
+ C2
R
Vr1 = 1/14 V –
+ C1
R/2
Fig. 27.
3. A 7-bit output is obtained from the comparator is converted to a 3-
bit output using decoder circuit.
4. The process adopted here is the simplest and it works quite fast.
5. The demerits rapidly increase in the number of comparators with
the number of bits and the corresponding complications of the
decoder circuit.
6. The analog input, comparator outputs and digital output are shown
in Table 4.
Table 4.
Analog input Comparator outputs Digital output
Va C7 C6 C5 C4 C3 C2 C1 B2 B1 B0
0  Va < Vr1 0 0 0 0 0 0 0 0 0 0
Vr1 < Va < Vr2 0 0 0 0 0 0 1 0 0 1
Vr2 < Va < Vr3 0 0 0 0 0 1 1 0 1 0
Vr3 < Va < Vr4 0 0 0 0 1 1 1 0 1 1
Vr4 < Va < Vr5 0 0 0 1 1 1 1 1 0 0
Vr5 < Va < Vr6 0 0 1 1 1 1 1 1 0 1
Vr6 < Va < Vr7 0 1 1 1 1 1 1 1 1 0
Vr7 < Va  V 1 1 1 1 1 1 1 1 1 1


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Digital System Design

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PUBLISHED BY : Apram Singh

© ALL RIGHTS RESERVED

Information contained in this work is derived from sources

Digital System Design (EC : Sem-3)

Price: Rs. 90/- only

Printed Version : e-Book.

KEC 302 : Digital System Design

UNIT-1 : LOGIC SIMPLIFICATION & COMBINATIONAL LOGIC DESIGN

UNIT-2 : MSI DEVICES (2–1 B to 2–31 B)

UNIT-3 : SEQUENTIAL LOGIC DESIGN (3–1 B to 3–40 B)

UNIT-4 : LOGIC FAMILIES & MEMORIES (4–1 B to 4–32 B)

UNIT-5 : D/A AND A/D CONVERTER (5–1 B to 5–21 B)

SHORT QUESTIONS (SQ–1 B to SQ–17 B)

SOLVED PAPERS (2014-15 TO 2019-20) (SP–1 B to SP–44 B)

Part-2 : Code Conversion ....................................... 1–3B to 1–12B

Part-3 : Review of Boolean Algebra and ........... 1–12B to 1–15B

Part-4 : Karnaugh Maps Upto 6 ......................... 1–15B to 1–22B

Part-5 : Tabulation (Quine-McCluskey) ........... 1–22B to 1–31B

Long Answer Type and Medium Answer Type Questions

Que 1.1. Describe the binary codes. Show the classification of

Weighted Reflective Alphanumeric

Long Answer Type and Medium Answer Type Questions

Que 1.3. Design Binary to BCD code converter.

Binary code BCD code

Expression for B 0 Expression for B 1

Expression for B 2 Expression for B 3

Fig. 1.3.1. Logic circuit for binary to BCD converter.

Que 1.4. Design a combinational circuit that converts a BCD

code to excess-3 code. AKTU 2016-17, Marks 15

3. The expressions derived from the maps are :

Que 1.5. Design excess-3 code to BCD code converter.

Que 1.6. Design Binary code to Gray code converter.

AKTU 2018-19, Marks 07

Binary code Gray code

Expression for G 0 Expression for G 1

Expression for G 2 Expression for G 3

Que 1.7. Design a combinational circuit that converts a 3-bit

ii. Using NAND gates :

Long Answer Type and Medium Answer Type Questions

Que 1.8. State De Morgan’s theorem.

Que 1.9. Simplify the following expression as much as possible :

Que 1.10. Simplify the following boolean equation :

Y(A, B, C, D) = ABCD + ABCD

Fm = xy + xyz + yz + xz = xy(z + z ) + xyz + (x + x )yz + xz(y + y )

Que 1.12. Simplify the following boolean expression to a minimum

Y = ( AB  AB)(C  C)  ABC  ABC  ABC  ABC

= ABC  ABC  ABC  ABC  ABC

Long Answer Type and Medium Answer Type Questions

AB m0 m1 m3 m2 00 0000 0001 0011 0010

AB m4 m5 m7 m6 01 0100 0101 0111 0110

AB m8 m9 m 11 m 10 10 1000 1001 1011 1010

Que 1.16. Simplify the boolean function.

Que 1.17. Simplify the following expression into product of sum

2. Now for POS form we will take complement function,

Que 1.18. Implement the following boolean function with NAND

gates. F(x, y, z) =m(1, 2, 3, 4, 5, 7) AKTU 2016-17, Marks 10