ACADEMY OF TECHNOLOGY

MCQs CS303

1. BIOS is
(a) a collection of I/O driver programs
(b) part of OS to perform I/O operations
(c) firmware consisting of I/O driver programs
(d) a program to control one of the I/O peripherals.

2. The basic principle of Von Neumann computer is

(a) storing program and data in separate memory
(b) using pipeline concept
(c) storing both program and data in the same memory
(d) using a large number of registers

3. What is called the von Neumann bottleneck?

(a) CPU (b) Memory (c) Single Bus (d) ALU

4. One bit Full Adder can be designed using

(a) Two half adders and one OR gate (b) Two Half adders
(c) One XOR gate and two NAND gates (d) Two XOR and four NAND gates

5. A CPU consists of
(a) ALU, Control Unit, and registers (b) ALU, Control Unit, and Hard Disk
(c) ALU, Control Unit (d) ALU, Control Unit, and Key Board

6. A single bus structure is primarily found in

(a) mini and micro computers (b) large mainframe computers
(c) super computers (d) analog computers

7. When signed numbers are used in binary arithmetic, then which one of the following
notations would have unique representation of zero?
(a) Sign magnitude (b) 2’s complement (c) 1’s complement (d) 10’s complement

8. Instruction cycle is
(a) Fetch?decode?execution (b) Fetch –execution?decode
(c) Decode?fetch?execution (d) Decode? Execution?Fetch

9. The speed of the microprocessor is usually measured by the

(a) Microprocessor’s throughput
(b) Speed with which it performs I/O operations
(c) Time required to execute a basic instruction
(d) Time required to execute a small operation.

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10. A ripple carry adder requires ……………. time.

(a) Constant time (b) O(log (N) (c) Linear time (O(N)) (d) O (N log(N))

11. The largest integer that can be represented in signed?2’s complement representation using n bits
(a) 2n?1 (b) 2n (c) 2n?1?1 (d) 2n ?1

12. With 2's complement representation, the range of values that can be represented on the data bus of an 8 bit
microprocessor is given by
(a) ? 128 to + 127 (b) ? 128 + 128
(c) ? 127 to* 128 (d) 0 ? 255.

13. A decimal number has 30 digits. Approximately how many digits would the binary representation have?
(a) 30 (b) 60 (c) 90 (d) 120

14. Equivalent hexadecimal of (76575372)8 will be

(a) FAFAFF (b) FAFAFA (c) FFFAAA (d) FAAFAF

15. Subtractor can be implemented by using

(a) Adder (b) Complement (c) Both (a) and (b) (d) none of these.

16. If a positive number is added to a negative number, then there is a possibility of

(a) Underflow (b) Overflow (c) Both a and b (d) none of these.

17. Overflow occurs when

(a) data is out of range (b) data is within range (c) None of these

18. If the multiplier Q is 1101 (?3 in decimal) and 4 bit registers are in use, then in Booth’s technique for
multiplication, the number of additions and subtractions required are
(a) 0 addition and 2 subtraction (b) 1 addition and 2 subtractions
(c) 1 addition and 1 subtraction (d) 2 addition and 1 subtraction

19. Booths algorithm gives procedure for multiplying binary integers in

(a) Signed magnitude representation (b) 2’s complement representation
(c) Unsigned representation (d) None of the above

20. The least negative value that the product of two 8?bit two’s complement numbers can take is
(a) ?214 (b) ?215 (c) ?216 (d) ?220

21. The minimum number of operands with any instruction is

(a) 0 (b) 1 (c) 2 (d) 3

22. A IEEE single precision floating point number with E’=255 and M=0 represents
(a) Exact 0 (b) +∞ (c) ?∞ (d) Not a Number

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23. A IEEE single precision floating point number with E’=255 and M≠0 represents
(a) Exact 0 (b) +∞ (c) ?∞ (d) Not a Number

24. If you convert (+46.5) into a 24 bit floating point binary number following IEEE convention, what would be
the exponent?
(a) 0011100 (b) 0000011 (c) 1100010 (d) none of these.

25. The immediate addressing mode of instruction provides the operand in the memory location
(a) pointed by PC (b) next to that opcode
(c) pointed by PC+1 (d) pointed by PC?1

26. In instruction fetch phase, the instruction is fetched from the memory location whose address is in the
(a) Program Counter (b) Instruction Register
(c) Stack register (d) Memory Address Register

27. The register that keeps track of the next instruction to be executed is
(a) Program Counter (b) Instruction Register
(c) Stack register (d) Memory Address Register

28. The operand itself is contained in an instruction of

(a) Immediate addressing mode (b) Indirect addressing mode
(c) Direct addressing mode (d) Register addressing

29. Which of the following addressing modes is used in the instruction PUSH B?
(a) Immediate (b) Register (c) Direct (d) Register Indirect

30. Which of the following addressing modes is used in instruction RAL

(a) Immediate (b) Implied (c) Direct (d) Register.

31. The accumulator is always needed in case of

(a) Zero address Instruction (b) One address Instruction
(c) Two address Instruction (d) Three address Instruction

32. Which is likely to be longer (have more instructions):

(a) a program written for a zero address architecture.
(b) a program written for a one?address architecture.
(c) a program written for a two?address architecture.
(d) a program written for a three?address architecture.

33. PUSH is a
(a) Zero address Instruction (b) One address Instruction
(c) Two address Instruction (d) Three address Instruction

34. The logic circuit in ALU is

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(a) entirely combinational (b) entirely sequential

(c) combinational cum sequential (d) none of this

35. A memory device, in which a bit is stored as charge across the stray capacitance
(a) SRAM (b) DRAM (c) ROM (d) EPROM

36. Associative memory is a

(a) Very cheap memory (b) Content addressable memory
(c) Pointer addressable memory (d) Slow memory

37. Bi?directional buses use

(a) Tri?state buffers (b) Two tri?state buffers in cascade
(c) Two back to back connected tri?state buffer in parallel
(d) Two back to back connected buffers.

38. In content addressable memories all the words in the memory are compared
(a) Sequentially (b) Simultaneously (c) Both (a) and (b) (d) parallel

39. A microprocessor has a data bus with 64 lines and an address bus with 32 lines. The maximum number of
bits that can be stored in this memory is
(a) 32 X 232 (b) 32 X 264 (c) 64 X 232 (d) 64 X 264

40. How many address line are needed to address each memory location in 2046 x 4 memory chip?
(a) 8 (b) 10 (c) 11 (d) 12

41. How many address bits are required for a 1024 X 8 memory?
(a) 1024 (b) 5 (c) 10 (d) 13

42. Maximum number of directly addressable locations in the memory of a processor having 10 bits wide
control bus, 20 bits address bus and 8 bit data bus is
(a) 1K (b) 2K (c)1M (d) None of these.

43. How many RAM chips of size (256 K x1) are required to build 1 MByte Memory?
(a) 8 (b) 10 (c) 24 (d) 32

44. What is the width of data bus and address bus for 4096 X 8 memory?
(a) 16 & 12 (b) 8 & 12 (c) 12 & 32 (d) 32 & 16

45. In the memory hierarchy, the fastest memory is

(a) SRAM (b) DRAM (c) Cache (d) CPU Registers

46. Periodic refreshing is needed

(a) SRAM (b) DRAM (c) ROM (d) EPROM.

47. Which of the following is a disadvantage of Dynamic RAMs?

(a) High Density (b) Low cost (c) High Speed (d) memory refreshing.

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48. The principle of locality of reference justifies the use of

(a) interrupts (b) DMA (c) polling (d) cache memory

49. Cache memory

(a) increases performance (b) increases machine cycle
(c) reduces performance (d) none of these
50. The major objective, in choosing page replacement policy is to
(a) Minimize the hit ratio (b) Maximize the hit ratio
(c) Reduce the size of the page (d) Increase the size of the page

51. In which cache mapping technique, the chance of thrashing is quite high
(a) Set associative mapping (b) Direct mapping
(c) associative mapping (d) All of these.

52. In which cache mapping technique, the replacement policy is very easy
(a) Set associative mapping (b) Direct mapping
(c) associative mapping (d) All of these.

53. The hit ratio for cache memories is in ascending order for
(a) associative, direct and set?associative
(b) direct, associative and set?associative
(c) set?associative, direct and associative
(d) set?associative, associative and direct.

54. In the IEEE 754 floating point representation standard, the base is
(a) 23 (b) 127 (c) 16 (d) 2

55. Octal number system is

(a) a positional system with weights 0 to 9
(b) a positional system with weights 0 to 7
(c) a non positional system with weights 0 to 7
(d) a positional system with weights 0 to 8

56. A 4 digit BCD number can be represented with the help of

(a) 8 bits (b) 10 bits (c) 12 bits (d) 16 bits

57. Which is faster?

(a) SRAM (b) DRAM (c) equal

58. TLB, in context of virtual memory, stands for

(a) Transmission Line Buffer (b) Transaction look Buffer
(c) Translation Look?aside buffer (d) Transmission Lag Behind

59. Size of virtual memory is equivalent to the size of

(a) main memory (b) cache memory (c) secondary memory (d) both (a) & (c)

60. Physical memory broken down into groups of equal size is called
(a) page (b) tag (c) block / frame (d) index.

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61. A recently executed instruction is likely to be executed again very soon, is a property called
(a) Temporal locality of reference (b) Total locality of reference
(c) Spatial Locality of reference (d) None of these

62. Which processor is easier to pipeline

(a) RISC (b) CISC

63. CISC stands for

(a) Complete instructions set computer (b) Complete input set computer
(c) Complex instruction set computer (d) Complex input set computer.

64. For RISC system design, which control unit design technique is more suited?
(a) Microprogramming (b) Hardwired (c) Mixed (d) Software.

65. Repeated occurrence of an identical interrupt during servicing of the similar interrupt will result in:
(a) A program error (b) A hardware error due to stack overflow
(c) Save stack overflow and system crash (d) None of these.

66. The feature of masking interrupt is a necessity since

(a) More than one interrupt may get recorded simultaneously
(b) To enable CPU to execute more system critical events than others
(c) While servicing one interrupt, CPU cannot accept another interrupt
(d) Prioritization of different types of interrupt is a necessity.

67. Cycle stealing is associated with

(a) Data transfer among registers (b) Pipelining
(c) DMA (d) Microprogramming.

68. In Daisy?chaining priority method, all the devices that can request an interrupt are
connected in
(a) Parallel mode (b) Serial Mode
(c) Both serial and parallel (d) Bidirectional.

69. Micro instructions are kept in

(a) main memory (b) cache memory
(c) control memory (d) secondary memory.

70. In context of parallelism

(a) the horizontal microinstructions exhibit more parallelism than vertical one
(b) the vertical microinstructions exhibit more parallelism than horizontal one
(c) both have equal capability
(d) sometimes horizontal, sometimes vertical.

71. Delayed branching are used to minimize the penalty incurred as a result of
(a) Conditional branch instructions (b) Unconditional branch instructions
(c) Both of these (d) None of these.

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72. Pipelining is
(a) used to let each processing unit work faster
(b) used to reduce branch instruction hazards
(c) used to utilize the maximum number of logic subunits in the processor
(d) used to run the maximum number of instructions in parallel.

73. Flynn’s taxonomy classifies computer architectures based on which property?

(a) the number of instructions and the number of data streams that flow into the processor
(b) the number of instructions
(c) the number of data streams that flow into the processor
(d) none of these.

74. For BIOS( Basic input / output System) and IOCS( Input Output control System) which
one of the following is true
(a) BIOS and IOCS are same
(b) BIOS controls all devices and IOCS controls only certain devices
(c) BIOS ia not a part of Operating System and IOCS is a part of Operating System
(d) BIOS is stored in ROM and IOCS is stored in RAM.

75. Memory mapped I/O scheme for the allocation of address to memories and I/O device is used for
(a) Small systems (b) Large systems
(c) Both large & small systems (d) Very large systems.

76. Which type of devices share a common clock

(a) Synchronous (b) Asynchronous (c) Both (a) and (b) (d) None of these.

77. The time required for a disk arm to position itself over the required track is called
(a) seek time (b) latency time (c) access time (d) rotational delay.

78. The time required for the required sector to position itself under a read/write head is called
(a) seek time (b) latency time (c) access time (d) rotational delay.

79. In a typical hard disk the data density

(a) at the center is more than outer edge (b) uniform throughout
(c) at the center is less than outer (d) none of these.

80. Control program memory can be reduced by

(a) horizontal format (b) vertical format micro?program
(c) hardwired control (d) none of these.

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