SN 74 LVC 1 G 04
SN 74 LVC 1 G 04
SN 74 LVC 1 G 04
SN74LVC1G04
SCES214AD–APRIL1999–REVISED OCTOBER 2014
4 Simplified Schematic
A Y
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G04
SCES214AD – APRIL 1999 – REVISED OCTOBER 2014 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.11 Typical Characteristics ............................................ 7
2 Applications ........................................................... 1 8 Parameter Measurement Information .................. 8
3 Description ............................................................. 1 9 Detailed Description ............................................ 10
4 Simplified Schematic............................................. 1 9.1 Overview ................................................................. 10
5 Revision History..................................................... 2 9.2 Functional Block Diagram ....................................... 10
9.3 Feature Description................................................. 10
6 Pin Configuration and Functions ......................... 3
9.4 Device Functional Modes........................................ 10
7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings ..................................... 4 10 Application and Implementation........................ 11
10.1 Application Information.......................................... 11
7.2 Handling Ratings....................................................... 4
10.2 Typical Application ............................................... 11
7.3 Recommended Operating Conditions ...................... 5
7.4 Thermal Information .................................................. 5 11 Power Supply Recommendations ..................... 12
7.5 Electrical Characteristics........................................... 6 12 Layout................................................................... 12
7.6 Switching Characteristics, CL = 15 pF ...................... 6 12.1 Layout Guidelines ................................................. 12
7.7 Switching Characteristics, CL = 30 pF or 50 pF, 12.2 Layout Example .................................................... 12
–40°C to 85°C ............................................................ 6 13 Device and Documentation Support ................. 13
7.8 Switching Characteristics, CL = 15 pF, –40°C to 13.1 Trademarks ........................................................... 13
125°C ......................................................................... 6 13.2 Electrostatic Discharge Caution............................ 13
7.9 Switching Characteristics, CL = 30 pF or 50 pF, 13.3 Glossary ................................................................ 13
–40°C to 125°C .......................................................... 7
14 Mechanical, Packaging, and Orderable
7.10 Operating Characteristics........................................ 7
Information ........................................................... 13
5 Revision History
Changes from Revision AC (March 2014) to Revision AD Page
Pin Functions
PIN
DBV, DCK, DESCRIPTION
NAME DSF, DRY YZP YZV DPW
DRL
NC 1 1, 5 A1, B2 – 1 No connect
A 2 2 B1 A1 2 Input
GND 3 3 C1 B1 3 Ground
Y 4 4 C2 B2 4 Output
VCC 5 6 A2 A2 5 Power terminal
7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range –0.5 6.5 V
VI Input voltage range –0.5 6.5 V
VO Voltage range applied to any output in the high-impedance or power-off state (2) –0.5 6.5 V
VO Voltage range applied to any output in the high or low state (2) (3) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6 8
TPD TPD
7
5
6
4
5
TPD - ns
TPD - ns
3 4
3
2
2
1
1
0 0
-100 -50 0 50 100 150 0 1 2 3 4 5 6
Temperature - °C D001
Vcc - V D002
Figure 1. TPD Across Temperature at 3.3-V VCC Figure 2. TPD Across VCC at 25°C
LOAD CIRCUIT
INPUTS
VCC VM VLOAD CL RL V∆
VI tr/tf
1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 15 pF 1 MΩ 0.15 V
2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 15 pF 1 MΩ 0.15 V
3.3 V ± 0.3 V 3V ≤2.5 ns 1.5 V 6V 15 pF 1 MΩ 0.3 V
5 V ± 0.5 V VCC ≤2.5 ns VCC/2 2 × VCC 15 pF 1 MΩ 0.3 V
VI
Timing Input VM
0V
tw
VI tsu th
VI
Input VM VM
Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES
VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
Output
VOH VLOAD/2
Waveform 1
Output VM VM VM
S1 at VLOAD VOL + V∆
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
VOH Output
VOH
VM VM Waveform 2 VOH − V∆
Output VM
S1 at GND
VOL
(see Note B) ≈0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING
LOAD CIRCUIT
INPUTS
VCC VM VLOAD CL RL V∆
VI tr/tf
1.8 V ± 0.15 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 1 kΩ 0.15 V
2.5 V ± 0.2 V VCC ≤2 ns VCC/2 2 × VCC 30 pF 500 Ω 0.15 V
3.3 V ± 0.3 V 3V ≤2.5 ns 1.5 V 6V 50 pF 500 Ω 0.3 V
5 V ± 0.5 V VCC ≤2.5 ns VCC/2 2 × VCC 50 pF 500 Ω 0.3 V
VI
Timing Input VM
0V
tw
VI tsu th
VI
Input VM VM
Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES
VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
Output
VOH VLOAD/2
Waveform 1
Output VM VM VM
S1 at VLOAD VOL + V∆
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
VOH Output
VOH
VM VM Waveform 2 VOH − V∆
Output VM
S1 at GND
VOL
(see Note B) ≈0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING
9 Detailed Description
9.1 Overview
The SN74LVC1G04 device contains inverter gate and performs the Boolean function Y = A. This device is fully
specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing
damaging current backflow through the device when it is powered down.
The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint saves
significant board space over other package options while still retaining the traditional manufacturing friendly lead
pitch of 0.5 mm.
A Y
Function Table
INPUT OUTPUT
A Y
H L
L H
VCC VCC
uC or Logic
uC or Logic uC or Logic
LVC1G04 LVC1G04
Icc - mA
3
0
0 20 40 60 80
Frequency - MHz D003
12 Layout
VCC Input
Unused Input Output Unused Input Output
Input
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
www.ti.com 11-Apr-2023
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
SN74LVC1G04DBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C045, C04F, C04J, Samples
C04K, C04R)
(C04H, C04P, C04S)
SN74LVC1G04DBVRE4 ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C04 Samples
C04P
SN74LVC1G04DBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (C045, C04F, C04J, Samples
C04K, C04R)
(C04H, C04P, C04S)
SN74LVC1G04DBVTE4 ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C04 Samples
C04P
SN74LVC1G04DBVTG4 ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 C04 Samples
C04P
SN74LVC1G04DCK3 ACTIVE SC70 DCK 5 3000 RoHS & SNBI Level-1-260C-UNLIM -40 to 125 (CCF, CCZ) Samples
Non-Green
SN74LVC1G04DCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CC5, CCF, CCJ, CC Samples
K, CCR)
(CCH, CCP, CCS)
SN74LVC1G04DCKRE4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 (CC5, CCF, CCJ, CC Samples
K, CCR)
(CCH, CCP, CCS)
SN74LVC1G04DCKRG4 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 (CC5, CCF, CCJ, CC Samples
K, CCR)
(CCH, CCP, CCS)
SN74LVC1G04DCKT ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 (CC5, CCF, CCJ, CC Samples
R)
(CCH, CCP)
SN74LVC1G04DCKTE4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 (CC5, CCF, CCJ, CC Samples
R)
(CCH, CCP)
SN74LVC1G04DCKTG4 ACTIVE SC70 DCK 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 (CC5, CCF, CCJ, CC Samples
R)
(CCH, CCP)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2023
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
SN74LVC1G04DPWR ACTIVE X2SON DPW 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 K4 Samples
SN74LVC1G04DRLR ACTIVE SOT-5X3 DRL 5 4000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 (CC7, CCR) Samples
SN74LVC1G04DRY2 ACTIVE SON DRY 6 5000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 CC Samples
SN74LVC1G04DRYR ACTIVE SON DRY 6 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CC Samples
SN74LVC1G04DRYRG4 ACTIVE SON DRY 6 5000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CC Samples
SN74LVC1G04DSF2 ACTIVE SON DSF 6 5000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 CC Samples
SN74LVC1G04DSFR ACTIVE SON DSF 6 5000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 CC Samples
SN74LVC1G04YZPR ACTIVE DSBGA YZP 5 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 (CC7, CCN) Samples
SN74LVC1G04YZVR ACTIVE DSBGA YZV 4 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 CC Samples
7
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2023
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
• Automotive : SN74LVC1G04-Q1
• Enhanced Product : SN74LVC1G04-EP
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Feb-2024
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Sprocket Holes
Q1 Q2 Q1 Q2
Pocket Quadrants
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 3-Feb-2024
Width (mm)
H
W
Pack Materials-Page 2
PACKAGE OUTLINE
DPW0005A SCALE 12.000
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
0.85 A
B
0.75
0.4 MAX C
SEATING PLANE
NOTE 3
(0.1)
2 0.25 0.1
4
NOTE 3
2X 3
2X (0.26)
0.48
5
1
0.27
0.239 4X
0.17
0.139
0.1 C A B
0.288
3X 0.05 C
0.188
4223102/D 03/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The size and shape of this feature may vary.
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EXAMPLE BOARD LAYOUT
DPW0005A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.78)
SYMM ( 0.1)
4X (0.42) VIA 0.05 MIN
ALL AROUND
1 TYP
5
4X (0.22)
SYMM
4X (0.26)
(0.48)
3
2 4
(R0.05) TYP
SOLDER MASK
4X (0.06) OPENING, TYP
( 0.25)
(0.21) TYP METAL UNDER
EXPOSED METAL SOLDER MASK
CLEARANCE TYP
4223102/D 03/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DPW0005A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (0.42) 4X (0.06)
5
4X (0.22) 1
( 0.24)
4X (0.26)
SYMM
(0.21) (0.48)
TYP
SOLDER MASK
EDGE 3
2
4
(R0.05) TYP
SYMM
(0.78)
EXPOSED PAD 3
92% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:100X
4223102/D 03/2022
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OUTLINE
YZP0005 SCALE 8.000
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
B E A
BALL A1
CORNER
C
0.5 MAX
SEATING PLANE
0.19
0.15 0.05 C
BALL TYP
0.5 TYP
SYMM
1
TYP
B D: Max = 1.418 mm, Min =1.358 mm
0.5
TYP E: Max = 0.918 mm, Min =0.858 mm
A
0.25
5X 1 2
0.21
0.015 C A B
SYMM
4219492/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YZP0005 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
5X ( 0.23)
1 2
(0.5) TYP
SYMM
B
SYMM
( 0.23)
METAL METAL UNDER
SOLDER MASK
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)
4219492/A 05/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YZP0005 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
5X ( 0.25)
(R0.05) TYP
1 2
(0.5)
TYP
B SYMM
METAL SYMM
TYP
4219492/A 05/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
D: Max = 0.918 mm, Min =0.858 mm
3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA
1 5
2X 0.95 (0.1)
3.05
2.75
1.9 1.9
2
(0.15)
4
3
0.5
5X
0.3
0.15
0.2 C A B NOTE 5 (1.1) TYP
0.00
1.45
0.90
0 -10
0.25
GAGE PLANE 0.22
TYP
0.08 0 -10
8
TYP 0.6
0 TYP SEATING PLANE
0.3
0 -10
0 -10
4214839/H 09/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3 4
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
4214839/H 09/2023
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
2 (1.9)
2X(0.95)
3 4
(R0.05) TYP
(2.6)
4214839/H 09/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DCK0005A SCALE 5.600
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
C
2.4
1.8 0.1 C
1.4
B A 1.1 MAX
PIN 1 1.1
INDEX AREA
1 5
2X 0.65 NOTE 4
2.15
1.3 (0.15) 1.3
2 1.85
(0.1)
4
0.33 3
5X
0.15
0.1
0.1 C A B (0.9) TYP
0.0
NOTE 5
0.15
GAGE PLANE 0.22
TYP
0.08
8 0.46
TYP TYP
0 0.26
SEATING PLANE
4214834/D 07/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
5. Lead width does not comply with JEDEC.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
2X (0.65)
3 4
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
4214834/D 07/2023
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
2X(0.65)
3 4
(R0.05) TYP
(2.2)
4214834/D 07/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DRL0005A SCALE 8.000
SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
1.7
1.5
PIN 1 A
ID AREA
1
5
2X 0.5
1.7
1.5
2X 1 NOTE 3
4
3
0.6 MAX
C
SEATING PLANE
0.18
5X 0.05 C
0.08
SYMM
SYMM
0.27
5X
0.15
0.1 C A B
0.4
5X 0.05
0.2
4220753/B 12/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-293 Variation UAAD-1
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EXAMPLE BOARD LAYOUT
DRL0005A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
5X (0.67) SYMM
1
5
5X (0.3)
SYMM
(1)
2X (0.5)
3 4
(R0.05) TYP
(1.48)
SOLDERMASK DETAILS
4220753/B 12/2020
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
DRL0005A SOT - 0.6 mm max height
PLASTIC SMALL OUTLINE
5X (0.67)
SYMM
1
5
5X (0.3)
SYMM
(1)
2X (0.5)
3 4
(R0.05) TYP
(1.48)
4220753/B 12/2020
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DRY 6 USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4207181/G
PACKAGE OUTLINE
DRY0006A SCALE 8.500
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
1.05 A
B
0.95
0.6 MAX C
SEATING PLANE
0.05
0.00 0.08 C
3X 0.6
SYMM
(0.127) TYP
(0.05) TYP
3
4
4X
0.5
SYMM
2X
1
6
1
0.25
6X
0.4 0.15
0.3 0.1 C A B
0.05 C
PIN 1 ID
(OPTIONAL) 0.35
5X
0.25
4222894/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DRY0006A USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35)
5X (0.3)
1 6
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
EXPOSED
EXPOSED
METAL
METAL
4222894/A 01/2018
NOTES: (continued)
3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DRY0006A USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35) 5X (0.3)
1 6
6X (0.2)
SYMM
4X (0.5)
4
3
4222894/A 01/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DSF0006A SCALE 10.000
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
1.05
B A
0.95
0.4 MAX C
SEATING PLANE
0.05 C
(0.11) TYP
SYMM 0.05
0.00
3
4
2X SYMM
0.7
4X
0.35
6
1
0.22
6X
0.12
(0.1)
PIN 1 ID 0.45 0.07 C B A
6X
0.35 0.05 C
4220597/B 06/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MO-287, variation X2AAF.
www.ti.com
EXAMPLE BOARD LAYOUT
DSF0006A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.6)
(R0.05) TYP
1
6X (0.17) 6
SYMM
4X (0.35)
4
3
SYMM
(0.8)
0.07 MIN
0.07 MAX EXPOSED METAL ALL AROUND
ALL AROUND
EXPOSED METAL
4220597/B 06/2022
NOTES: (continued)
4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DSF0006A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.6)
(R0.05) TYP
1
6X (0.15) 6
SYMM
4X (0.35)
4
3
SYMM
(0.8)
4220597/B 06/2022
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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