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SN54AHCT08, SN74AHCT08
SCLS237N – OCTOBER 1995 – REVISED SEPTEMBER 2015

SNx4AHCT08 Quadruple 2-Input Positive-AND Gates

1 Features 3 Description
•
1 Inputs are TTL-Voltage Compatible The SNx4AHCT08 devices are quadruple 2-input
positive-AND gates. These devices perform the
• Latch-Up Performance Exceeds 250 mA Per
Boolean function Y = A ´ B or Y = A + B in positive logic.
JESD 17
• ESD Protection Exceeds JESD 22 Device Information(1)
– 2000-V Human-Body Model (A114-A) PART NUMBER PACKAGE BODY SIZE (NOM)
– 200-V Machine Model (A115-A) SOIC (14) 8.65 mm × 3.91 mm
– 1000-V Charged-Device Model (C101) SSOP (14) 6.20 mm × 5.30 mm
• On Products Compliant to MIL-PRF-38535, SNx4AHCT08 SOP (14) 12.60 mm × 5.30 mm
All Parameters Are Tested Unless Otherwise TSSOP (14) 5.00 mm × 4.40 mm
Noted. On All Other Products, Production VQFN (14) 3.50 mm × 3.50 mm
Processing Does Not Necessarily Include Testing (1) For all available packages, see the orderable addendum at
of All Parameters. the end of the data sheet.

2 Applications
• Servers
• Network Switches
• PCs and Notebooks
• Electronic Points of Sale

4 Simplified Schematic
A
Y
B

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54AHCT08, SN74AHCT08
SCLS237N – OCTOBER 1995 – REVISED SEPTEMBER 2015 www.ti.com

Table of Contents
1 Features .................................................................. 1 9.1 Overview ................................................................... 8
2 Applications ........................................................... 1 9.2 Functional Block Diagram ......................................... 8
3 Description ............................................................. 1 9.3 Feature Description................................................... 8
9.4 Device Functional Modes.......................................... 8
4 Simplified Schematic............................................. 1
5 Revision History..................................................... 2 10 Application and Implementation.......................... 9
10.1 Application Information............................................ 9
6 Pin Configuration and Functions ......................... 3
10.2 Typical Application ................................................. 9
7 Specifications......................................................... 4
11 Power Supply Recommendations ..................... 10
7.1 Absolute Maximum Ratings ...................................... 4
7.2 ESD Ratings.............................................................. 4 12 Layout................................................................... 10
12.1 Layout Guidelines ................................................. 10
7.3 Recommended Operating Conditions....................... 4
12.2 Layout Example .................................................... 10
7.4 Thermal Information .................................................. 5
7.5 Electrical Characteristics........................................... 5 13 Device and Documentation Support ................. 11
7.6 Switching Characteristics, VCC = 5 V ± 0.5 V ........... 5 13.1 Related Links ........................................................ 11
7.7 Noise Characteristics ................................................ 6 13.2 Community Resources.......................................... 11
7.8 Operating Characteristics.......................................... 6 13.3 Trademarks ........................................................... 11
7.9 Typical Characteristics .............................................. 6 13.4 Electrostatic Discharge Caution ............................ 11
13.5 Glossary ................................................................ 11
8 Parameter Measurement Information .................. 7
9 Detailed Description .............................................. 8 14 Mechanical, Packaging, and Orderable
Information ........................................................... 11

5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision M (July 2014) to Revision N Page

• Added TJ, Junction temperature ............................................................................................................................................ 4

• Updated VIH and VIL MIN and MAX values............................................................................................................................. 4

Changes from Revision L (October 1995) to Revision M Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
• Deleted Ordering Information table. ....................................................................................................................................... 1
• Added Military Disclaimer to Features list. ............................................................................................................................. 1
• Added Applications. ............................................................................................................................................................... 1
• Added Pin Functions table...................................................................................................................................................... 3
• Added ESD Ratings table. ..................................................................................................................................................... 4
• Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ......................................... 4
• Added Thermal Information table. .......................................................................................................................................... 5
• Added Typical Characteristics section.................................................................................................................................... 6
• Added Detailed Description section........................................................................................................................................ 8
• Added Application and Implementation section...................................................................................................................... 9
• Added Power Supply Recommendations and Layout sections............................................................................................ 10

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6 Pin Configuration and Functions

SN54AHCT08 . . . J or W Package SN74AHCT08 . . .RGY Package SN54HACT08 . . . FK Package
14–Pin CDIP or CFP 14–Pin VQFN
SN74AHCT08 . . . D, DB, DGV, N, NS, or PW Package
20–Pin LCCC
14–Pin SOIC, SSOP, TVSOP, PDIP, SO, or TSSOP Top View Top View

VCC
VCC
Top View

NC
1B
1A

4B
1A
1A 1 14 VCC
1B 4B 1 14
2 13 3 2 1 20 19
1Y 3 12 4A 1B 2 13 4B 1Y 4 18 4A
2A 4 11 4Y 1Y 3 12 4A NC 5 17 NC
2B 5 10 3B 2A 4 11 4Y 2A 6 16 4Y
2Y 6 9 3A NC
2B 5 10 3B NC 7 15
GND 7 8 3Y
2Y 6 9 3A 2B 8 14 3B
9 10 11 12 13
7 8

2Y

3Y
3A
GND
NC
3Y
GND
NC − No internal connection

Pin Functions
PIN
SN74AHCT08 SN54AHCT08
I/O DESCRIPTION
NAME D, DB, DGV,
RGY J, W FK
N, NS, PW
1A 1 1 1 2 I 1A Input
1B 2 2 2 3 I 1B Input
1Y 3 3 3 4 O 1Y Output
2A 4 4 4 6 I 2A Input
2B 5 5 5 8 I 2B Input
2Y 6 6 6 9 O 2Y Output
3Y 8 8 8 12 O 3Y Output
3A 9 9 9 13 I 3A Input
3B 10 10 10 14 I 3B Input
4Y 11 11 11 16 O 4Y Output
4A 12 12 12 18 I 4A Input
4B 13 13 13 19 I 4B Input
GND 7 7 7 10 — Ground Pin
1
5
7
NC — — — — No Connection
11
15
17
VCC 14 14 14 20 — Power Pin

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage range –0.5 7 V
(2)
VI Input voltage range –0.5 7 V
VO Output voltage range (2) –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –20 mA
IOK Output clamp current VO < 0 or VO > VCC ±20 mA
IO Continuous output current VO = 0 to VCC ±25 mA
Continuous current through VCC or GND ±50 mA
Tstg Storage temperature range –65 150 °C
TJ Junction temperature 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±1000
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)
SN54AHCT08 SN74AHCT08
UNIT
MIN MAX MIN MAX
VCC Supply voltage 4.5 5.5 4.5 5.5 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VI Input voltage 0 5.5 0 5.5 V
VO Output voltage 0 VCC 0 VCC V
IOH High-level output current –8 –8 mA
IOL Low-level output current 8 8 mA
Δt/Δv Input transition rise or fall rate 20 20 ns/V
TA Operating free-air temperature –55 125 –40 125 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI Application Report,
Implications of Slow or Floating CMOS Inputs, (SCBA004).

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7.4 Thermal Information

SN74AHCT08
(1) D (SOIC) DB (SSOP) DGV N (PDIP)
THERMAL METRIC UNIT
(TVSOP)
14 PINS 14 PINS 14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 97.5 109.5 133.3 59.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 58.7 62.1 55.6 47.3 °C/W
RθJB Junction-to-board thermal resistance 51.8 56.9 66.3 39.5 °C/W
ψJT Junction-to-top characterization parameter 22.6 22.6 7.8 32.4 °C/W
ψJB Junction-to-board characterization parameter 51.6 56.3 56.6 39.4 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, (SPRA953).

7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C SN54AHCT08 SN74AHCT08
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX MIN MAX MIN MAX
IOH = –50 µA 4.4 4.5 4.4 4.4
VOH 4.5 V V
IOH = –8 mA 3.94 3.8 3.8
IOL = 50 µA 0.1 0.1 0.1
VOL 4.5 V V
IOL = 8 mA 0.36 0.44 0.44
0 V to
II VI = 5.5 V or GND ±0.1 ±1 (1) ±1 µA
5.5 V
ICC VI = VCC or GND, IO = 0 5.5 V 2 20 20 µA
One input at 3.4 V,
ΔICC (2) 5.5 V 1.35 1.5 1.5 mA
Other inputs at VCC or GND
Ci VI = VCC or GND 5V 4 10 10 pF

(1) On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
(2) This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.

7.6 Switching Characteristics, VCC = 5 V ± 0.5 V

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2)
FROM TO LOAD TA = 25°C SN54AHCT08 SN74AHCT08
PARAMETER (INPUT) (OUTPUT) UNIT
CAPACITANCE MIN TYP MAX MIN MAX MIN MAX
tPLH 5 (1) 6.9 (1) 1 (1) 8 (1) 1 8
A or B Y CL = 15 pF (1) (1) (1)
ns
tPHL 5 6.9 1 8 (1) 1 8
tPLH 5.5 7.9 1 9 1 9
A or B Y CL = 50 pF ns
tPHL 5.5 7.9 1 9 1 9

(1) On products compliant to MIL-PRF-38535, this parameter is not production tested.

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7.7 Noise Characteristics

VCC = 5 V, CL = 50 pF, TA = 25°C (1)
SN74AHCT08
PARAMETER UNIT
MIN TYP MAX
VOL(P) Quiet output, maximum dynamic VOL 0.4 0.8 V
VOL(V) Quiet output, minimum dynamic VOL –0.4 –0.8 V
VOH(V) Quiet output, minimum dynamic VOH 4.4 V
VIH(D) High-level dynamic input voltage 2 V
VIL(D) Low-level dynamic input voltage 0.8 V

(1) Characteristics are for surface-mount packages only.

7.8 Operating Characteristics

VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load, f = 1 MHz 18 pF

7.9 Typical Characteristics

4.5

3.5

3
TPD (ns)

2.5

1.5

0.5
TPD in ns
0
-100 -50 0 50 100 150
Temperature (qC) D001

Figure 1. TPD vs Temperature

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8 Parameter Measurement Information

VCC
RL = 1 kΩ S1 Open
From Output Test From Output TEST S1
Under Test Point Under Test GND tPLH/tPHL Open
CL CL tPLZ/tPZL VCC
(see Note A) (see Note A) tPHZ/tPZH GND
Open Drain VCC

LOAD CIRCUIT FOR LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS 3-STATE AND OPEN-DRAIN OUTPUTS

3V
Timing Input 1.5 V
tw 0V
th
3V tsu
3V
Input 1.5 V 1.5 V
Data Input 1.5 V 1.5 V
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

3V 3V
Output
Input 1.5 V 1.5 V 1.5 V 1.5 V
Control
0V 0V

tPLH tPHL tPZL tPLZ

Output
VOH Waveform 1 ≈VCC
In-Phase 50% VCC 50% VCC 50% VCC
Output S1 at VCC VOL + 0.3 V
VOL (see Note B) VOL
tPHL tPLH tPZH tPHZ
Output
VOH VOH
Out-of-Phase Waveform 2 VOH − 0.3 V
50% VCC 50% VCC S1 at GND 50% VCC
Output
VOL (see Note B) ≈0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.

Figure 2. Load Circuit and Voltage Waveforms

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9 Detailed Description

9.1 Overview
The SNx4AHCT08 devices are quadruple 2-input positive-AND gates with low drive that will produce slow rise
and fall times. This slow transition reduces ringing on the output signal. The device has TTL inputs that allow up
translation from 3.3 V to 5 V. The inputs are high impedance when VCC = 0 V.

9.2 Functional Block Diagram

A
Y
B

9.3 Feature Description

• Slow rise and fall time on outputs allow for low-noise outputs
• TTL inputs allow up translation from 3.3 V to 5 V

9.4 Device Functional Modes

Table 1 is the function table for the SNx4AHCT08.

Table 1. Function Table

(Each Gate)
INPUTS OUTPUT
A B Y
H H H
L X L
X L L

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10 Application and Implementation

10.1 Application Information
The SNx4AHCT08 devices are low-drive CMOS devices that can be used for a multitude of bus-interface type
applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and
undershoot on the outputs. The TTL inputs can except voltages down to 3.3 V and translate up to 5 V.

10.2 Typical Application

3.3-V Bus Driver VCC 5 V Regulated

0.1 µF

5-V Accessory

Figure 3. Typical Application Diagram

10.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads, so routing and load conditions should be considered to prevent ringing.

10.2.2 Detailed Design Procedure

1. Recommended input conditions
– Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified High and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC
2. Recommend output conditions
– Load currents should not exceed 25 mA per output and 50 mA total for the part
– Outputs should not be pulled above VCC

10.2.3 Application Curves

Figure 4. Switching Characteristics Comparison

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11 Power Supply Recommendations

The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and 1
μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.

12 Layout

12.1 Layout Guidelines

When using multiple bit logic devices inputs should not ever float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Specified in Figure 5 are the rules that must be observed under all circumstances. All unused inputs of
digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that
should be applied to any particular unused input depends on the function of the device. Generally they will be
tied to GND or VCC; whichever makes more sense or is more convenient. It is generally acceptable to float
outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs
section of the part when asserted. This will not disable the input section of the IOs, so they cannot float when
disabled.

12.2 Layout Example

Vcc
Input

Unused Input Output Output

Unused Input

Input

Figure 5. Layout Diagram

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13 Device and Documentation Support

13.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 2. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
SN54AHCT08 Click here Click here Click here Click here Click here
SN74AHCT08 Click here Click here Click here Click here Click here

13.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

13.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-9682101Q2A ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-
& Green 9682101Q2A
SNJ54AHCT
08FK
5962-9682101QCA ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9682101QC
& Green A
SNJ54AHCT08J
5962-9682101QDA ACTIVE CFP W 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9682101QD
& Green A
SNJ54AHCT08W
5962-9682101VDA ACTIVE CFP W 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9682101VD
& Green A
SNV54AHCT08W
SN74AHCT08D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT08

SN74AHCT08DBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB08

SN74AHCT08DE4 ACTIVE SOIC D 14 50 TBD Call TI Call TI -40 to 125

SN74AHCT08DG4 ACTIVE SOIC D 14 50 TBD Call TI Call TI -40 to 125

SN74AHCT08DGVR ACTIVE TVSOP DGV 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB08

SN74AHCT08DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT08

SN74AHCT08DRG4 ACTIVE SOIC D 14 2500 TBD Call TI Call TI -40 to 125

SN74AHCT08N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 125 SN74AHCT08N

SN74AHCT08NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AHCT08

SN74AHCT08PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB08

SN74AHCT08PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 HB08

SN74AHCT08PWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HB08

SN74AHCT08RGYR ACTIVE VQFN RGY 14 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 HB08

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

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Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74AHCT08RGYRG4 ACTIVE VQFN RGY 14 3000 TBD Call TI Call TI -40 to 125

SNJ54AHCT08FK ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-
& Green 9682101Q2A
SNJ54AHCT
08FK
SNJ54AHCT08J ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9682101QC
& Green A
SNJ54AHCT08J
SNJ54AHCT08W ACTIVE CFP W 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9682101QD
& Green A
SNJ54AHCT08W

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

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Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54AHCT08, SN54AHCT08-SP, SN74AHCT08 :

• Catalog : SN74AHCT08, SN54AHCT08

• Enhanced Product : SN74AHCT08-EP, SN74AHCT08-EP
• Military : SN54AHCT08
• Space : SN54AHCT08-SP

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 27-Jul-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74AHCT08DBR SSOP DB 14 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
SN74AHCT08DGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
SN74AHCT08DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74AHCT08DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74AHCT08NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74AHCT08PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74AHCT08PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74AHCT08PWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74AHCT08RGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 27-Jul-2021

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AHCT08DBR SSOP DB 14 2000 853.0 449.0 35.0
SN74AHCT08DGVR TVSOP DGV 14 2000 853.0 449.0 35.0
SN74AHCT08DR SOIC D 14 2500 853.0 449.0 35.0
SN74AHCT08DR SOIC D 14 2500 340.5 336.1 32.0
SN74AHCT08NSR SO NS 14 2000 853.0 449.0 35.0
SN74AHCT08PWR TSSOP PW 14 2000 853.0 449.0 35.0
SN74AHCT08PWR TSSOP PW 14 2000 364.0 364.0 27.0
SN74AHCT08PWRG4 TSSOP PW 14 2000 853.0 449.0 35.0
SN74AHCT08RGYR VQFN RGY 14 3000 853.0 449.0 35.0

Pack Materials-Page 2
 MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23
0,40 0,07 M
0,13
24 13

0,16 NOM
4,50 6,60
4,30 6,20

Gage Plane

0,25

0°–
8°
0,75
1 12
0,50
A

Seating Plane

0,15
1,20 MAX 0,08
0,05

PINS **
14 16 20 24 38 48 56
DIM

A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40

A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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