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1024-Bit, 1-Wire EEPROM DS28E07

General Description Benefits and Features

The DS28E07 is a 1024-bit, 1-Wire® EEPROM chip orga- ● Partitioning of Memory Provides Greater Flexibility in
nized as four memory pages of 256 bits each. Data is Programming User Data
written to an 8-byte scratchpad, verified, and then copied • 1024 Bits of EEPROM Memory Organized as Four
to the EEPROM memory. As a special feature, the four Pages of 256 Bits
user memory pages can individually be write protected • Individual Memory Pages Can Be Permanently
or put in EPROM-emulation mode, where bits can only Write Protected or Put in EPROM-Emulation Mode
be changed from a 1 to a 0 state. Each device has its (Write to 0)
own guaranteed unique 64-bit ROM identification number ● Advanced 1-Wire Protocol Minimizes Interface to
(ROM ID) that is factory programmed into the chip. The Just Single IO Reducing Required Pin Count and
communication follows the 1-Wire protocol with the ROM Enhancing Reliability
ID acting as node address in the case of a multiple-device • Unique Factory-Programmed, Unalterable 64-Bit
1-Wire network. Identification Number
• Switchpoint Hysteresis and Filtering to Optimize
Applications Performance in the Presence of Noise
● Accessory/PCB Identification • Communicates to Host with a Single Digital Signal
● Medical Sensor Calibration Data Storage at 15.4kbps or 125kbps Using 1-Wire Protocol
● Analog Sensor Calibration Including IEEE P1451.4 • Reads and Writes over a Wide Voltage Range from
Smart Sensors 3.0V to 5.25V from -40°C to +85°C
● Ink and Toner Print Cartridge Identification • ±8kV HBM ESD Protection (typ) for IO Pin
● After-Market Management of Consumables

Ordering Information appears at end of data sheet.

Typical Application Circuit

VCC

100kΩ

*BSS84
VCC 1kΩ
PIOX RPUP

µC DS28E07
BIDIRECTIONAL
PIOY IO
GND OPEN DRAIN PORT GND

*NOTE: OPTIONAL LOW-IMPEDANCE BYPASS

OR EQUALLY DRIVE LOGIC ‘1’ WITH PIOY

1-Wire is a registered trademark of Maxim Integrated Products, Inc.

19-7674; Rev 7; 4/22

© 2022 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887 U.S.A. | Tel: 781.329.4700 | © 2022 Analog Devices, Inc. All rights reserved.
DS28E07 1024-Bit, 1-Wire EEPROM

Absolute Maximum Ratings

IO Voltage Range to GND........................................-0.5V to +6V Storage Temperature Range............................. -55°C to +125°C
IO Sink Current.................................................................±10mA Lead Temperature (soldering, 10s).................................. +300°C
Operating Temperature Range............................ -40°C to +85°C Lead Temperature (reflow) TO-92....................................+250°C
Junction Temperature.......................................................+150°C Lead Temperature (reflow) TDFN, TSOC........................ +260°C

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

Package Thermal Characteristics (Note 1)

TSOC TDFN
Junction-to-Ambient Thermal Resistance (θJA).........127°C/W Junction-to-Ambient Thermal Resistance (θJA)...........55°C/W
Junction-to-Case Thermal Resistance (θJC)................37°C/W Junction-to-Case Thermal Resistance (θJC)..................9°C/W
TO-92
Junction-to-Ambient Thermal Resistance (θJA).........132°C/W
Junction-to-Case Thermal Resistance (θJC)..................4°C/W

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

Electrical Characteristics
(TA = -40°C to +85°C, unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

IO PIN: GENERAL DATA
1-Wire Pullup Voltage VPUP (Note 3) 3.0 5.25 V
1-Wire Pullup Resistance RPUP (Note 3, 4) 300 2200 Ω
Input Capacitance CIO (Notes 4, 5) 1000 pF
Input Load Current IL IO pin at VPUP 0.05 1.75 6.7 µA
High-to-Low Switching 0.65 x
VTL (Notes 6, 7, 8) V
Threshold VPUP
Input Low Voltage VIL (Notes 3, 9) 0.5 V
Low-to-High Switching 0.75 x
VTH (Notes 6, 7, 10) V
Threshold VPUP
Switching Hysteresis VHY (Notes 6, 7, 11) 0.3 V
IOL = 4mA 0.4
Output Low Voltage VOL V
IOL = 10mA, 4.75V ≤ VPUP ≤ 5.25V 0.5
Standard speed, RPUP = 2200Ω 5
Recovery Time Overdrive speed, RPUP = 2200Ω 3
tREC µs
(Notes 3, 13) Overdrive speed, directly prior to reset
5
pulse, RPUP = 2200Ω
Rising-Edge Hold-off Time Standard speed 1.3
tREH µs
(Notes 6, 14) Overdrive speed N/A (0)
Time Slot Duration Standard speed 65
tSLOT µs
(Notes 3, 15) Overdrive speed 9

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DS28E07 1024-Bit, 1-Wire EEPROM

Electrical Characteristics (continued)

(TA = -40°C to +85°C, unless otherwise noted.) (Note 2)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

IO PIN: 1-Wire RESET, PRESENSE-DETECT CYCLE
Reset Low Time Standard speed 480 640
tRSTL µs
(Note 3) Overdrive speed 48 80
Presence Detect High Standard speed 15 60
tPDH µs
Time Overdrive speed 2 6
Standard speed 60 240
Presence Detect Low Time tPDL µs
Overdrive speed 8 24
Presence-Detect Sample Standard speed 60 75
tMSP µs
Time (Notes 3, 16) Overdrive speed 6 10
IO PIN: 1-Wire WRITE
Write-Zero Low Time Standard speed 60 120
tW0L µs
(Notes 3, 17) Overdrive speed 6 15.5
Write-One Low Time Standard speed 1 15
tW1L µs
(Notes 3, 17) Overdrive speed 0.25 2
IO PIN: 1-Wire READ
Read Low Time Standard speed 5 15 - δ
tRL µs
(Notes 3, 18) Overdrive speed 0.25 2-δ
Read Sample Time Standard speed tRL + δ 15
tMSR µs
(Notes 3, 18) Overdrive speed tRL + δ 2
EEPROM
Programming Current IPROG (Notes 6, 19) 1.2 mA
Programming Time tPROG (Note 20) 12 ms
Write/Erase Cycles TA = +25°C (Notes 21, 22) ,
NCY 10000 —
(Endurance) TA = +85°C (Notes 21, 22)
Data Retention tDR TA = +85°C (Notes 23, 24, 25) 10 Years

Note 2: Limits are 100% production tested at TA = +25°C and TA = +85°C. Limits over the operating temperature range and
relevant supply voltage range are guaranteed by design and characterization. Typical values are at TA = +25°C.
Note 3: System requirement.
Note 4: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery
times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.
Note 5: Maximum value represents the internal parasite capacitance when VPUP is first applied. Once the parasite capacitance is
charged, it does not affect normal communication.
Note 6: Guaranteed by design and/or characterization only. Not production tested.
Note 7: VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of VPUP, RPUP, 1-Wire timing, and
capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of
VTL, VTH, and VHY.
Note 8: Voltage below which, during a falling edge on IO, a logic-zero is detected.
Note 9: The voltage on IO must be less than or equal to VILMAX at all times the master is driving IO to a logic-zero level.
Note 10:Voltage above which, during a rising edge on IO, a logic-one is detected.
Note 11: After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic-zero.

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DS28E07 1024-Bit, 1-Wire EEPROM

Note 13:Applies to a single device attached to a 1-Wire line.

Note 14:The earliest recognition of a negative edge is possible at tREH after VTH has been previously reached.
Note 15:Defines maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN).
Note 16:Interval after tRSTL during which a bus master can read a logic 0 on IO if there is a DS28E07 present. The power-up pres-
ence detect pulse could be outside this interval but will be complete within 2ms after power-up.
Note 17:ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual
maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively.
Note 18:δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input-high
threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.
Note 19:Current drawn from IO during the EEPROM programming interval. The pullup circuit on IO during the programming interval
should be such that the voltage at IO is greater than or equal to VPUPMIN. If VPUP in the system is close to VPUPMIN, a low
impedance bypass of RPUP, which can be activated during programming, may need to be added.
Note 20:Interval begins tREHMAX after the trailing rising edge on IO for the last time slot of the E/S byte for a valid Copy Scratchpad
sequence. Interval ends once the device’s self-timed EEPROM programming cycle is complete and the current drawn by
the device has returned from IPROG to IL.
Note 21:Write-cycle endurance is tested in compliance with JESD47G.
Note 22:Not 100% production tested; guaranteed by reliability monitor sampling.
Note 23:Data retention is tested in compliance with JESD47G.
Note 24:Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
data sheet limit at operating temperature range is established by reliability testing.
Note 25:EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated tem-
peratures is not recommended.

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DS28E07 1024-Bit, 1-Wire EEPROM

Pin Configurations

SIDE VIEW FRONT VIEW

GND 1 1

IO 2 2

N.C. 3 3

TO-92 FRONT VIEW (T&R VERSION)

TOP VIEW

TOP VIEW
+
+ N.C. 1 6 N.C.

GND 1 6 N.C.
ymrrF
2807

IO 2 5 N.C.
IO 2 DS28E07 5 N.C.

N.C. 3 4 N.C. GND 3 4 N.C.

*EP

TSOC
TDFN
(3mm x 3mm)
*EXPOSED PAD

BOTTOM VIEW BOTTOM VIEW BOTTOM VIEW

1 2

GND 2
IO GND
2 GND IO 1

DS28E07G
SFN
IO 1
(6mm x 6mm x 0.9mm)

DS28E07GB
SFN
(3.5mm x 5mm x 0.35mm) DS28E07GA
SFN
(3.5mm x 6.5mm x 0.75mm)

NOTE:THE S FN PACKAGE IS QUALIFIED FOR ELECTRO-MECHANICAL CONTACT APPLICATIONS ONLY, NOT FOR SOLDE RING. FOR MORE
INFORMATION, REFER TO APPLICATION NOTE 4132: ATTA CHMENT METHODS FOR THE ELE CTRO-MECHANICAL 1-WIRE CONTACT PACK AGE.

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DS28E07 1024-Bit, 1-Wire EEPROM

Pin Description
PIN
NAME FUNCTION
TSOC TO-92 TDFN-EP SFN
3, 4, 5, 6 3 1, 4, 5, 6 — N.C. Not Connected
2 2 2 1 IO 1-Wire Bus Interface. Open-drain signal requires an external pullup resistor.
1 1 3 2 GND Ground
Exposed Pad (TDFN Only). Solder evenly to the board’s ground plane for
— — — — EP proper operation. Refer to Application Note 3273: Exposed Pads: A Brief
Introduction for additional information.

Detailed Description
PARASITE POWER
The DS28E07 combines 1024 bits of user EEPROM, 64
bits of administrative data memory, and a 64-bit ROM
ID in a single chip. Data is transferred serially through
the 1-Wire protocol that requires only a single data lead
and a ground return. The DS28E07 has an additional
memory area called the scratchpad that acts as a buf- 1-Wire 64-BIT
IO
fer when writing to the main memory or the administra- FUNCTION CONTROL LASERED ROM
tive data memory. Data is first written to the scratchpad
from which it can be read back. After the data has been DS28E07
verified, a Copy Scratchpad command transfers the MEMORY
data to its final memory location. The user memory can FUNCTION
CONTROL UNIT
have unrestricted write access (factory default), or can
be write protected or put in EPROM emulation mode. CRC-16
Write protection prevents changes to the memory data. GENERATOR
EPROM emulation mode logically ANDs memory data 64-BIT
DATA MEMORY SCRATCHPAD
with incoming new data, which allows changing bits from
4 PAGES OF
1 to 0, but not vice versa. By changing one bit at a time 256 BITS EACH
this mode could be used to create nonvolatile nonreset-
table counters. For more details, refer to Application Note REGISTER PAGE
64 BITS
5042: Implementing Nonvolatile, Nonresettable Counters
for Embedded Systems. The device’s 64-bit ROM ID elec-
Figure 1. Block Diagram
tronically identifies the equipment in which the DS28E07
is used. The ROM ID guarantees unique identification and Figure 2 shows the hierarchical structure of the 1-Wire
is also used to address the device in a multidrop 1-Wire protocol. The bus master must first provide one of the
network environment, where multiple devices reside on a seven ROM function commands: Read ROM, Match
common 1-Wire bus and operate independently of each ROM, Search ROM, Skip ROM, Resume, Overdrive-Skip
other. DS28E07 applications include accessory/PCB ROM, or Overdrive-Match ROM. Upon completion of an
identification, medical sensor calibration data storage, Overdrive-Skip ROM or Overdrive-Match ROM command
analog sensor calibration including IEEE P1451.4 smart byte executed at standard speed, the device enters over-
sensors, ink and toner print cartridge identification, and drive mode where all subsequent communication occurs
after-market management of consumables. at a higher speed. The protocol required for these ROM
function commands is described in Figure 9. After a ROM
Overview function command is successfully executed, the memory
The block diagram in Figure 1 shows the relationships functions become accessible and the master can provide
between the major control and memory sections of the any one of the four memory function commands. The pro-
DS28E07. The DS28E07 has four main data components: tocol for these memory function commands is described
four 32-byte pages of user EEPROM, a 64-bit scratchpad, in Figure 7. All data is read and written least signifi-
64 bit of administrative data memory, and a 64-bit ROM ID. cant bit first.

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DS28E07 1024-Bit, 1-Wire EEPROM

AVAILABLE COMMANDS: DATA FIELD AFFECTED:

READ ROM [33h] 64-BIT REG. #, RC-FLAG
DS28E07 COMMAND LEVEL:
MATCH ROM [55h] 64-BIT REG. #, RC-FLAG
SEARCH ROM [F0h] 64-BIT REG. #, RC-FLAG
1-Wire ROM FUNCTION COMMANDS
SKIP ROM [CCh] RC-FLAG
(SEE FIGURE 9)
RESUME [A5h] RC-FLAG
OVERDRIVE SKIP [3Ch] RC-FLAG, OD-FLAG
OVERDRIVE MATCH [69h] 64-BIT REG. #, RC-FLAG, OD-FLAG

WRITE SCRATCHPAD [0Fh] 64-BIT SCRATCHPAD, FLAGS

DS28E07-SPECIFIC
READ SCRATCHPAD [AAh] 64-BIT SCRATCHPAD
MEMORY FUNCTION COMMANDS
COPY SCRATCHPAD [55h] DATA MEMORY, REGISTER PAGE
(SEE FIGURE 7)
READ MEMORY [F0h] DATA MEMORY, REGISTER PAGE

Figure 2. Hierarchical Structure for 1-Wire Protocol

MSB LSB

8-BIT 8-BIT FAMILY CODE

48-BIT SERIAL NUMBER
CRC CODE (2Dh)

MSB LSB MSB LSB MSB LSB

Figure 3. 64-Bit ROM ID

POLYNOMIAL = X8 + X5 + X4 + 1

1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH

STAGE STAGE STAGE STAGE STAGE STAGE STAGE STAGE

X0 X1 X2 X3 X4 X5 X6 X7 X8

INPUT DATA

Figure 4. 1-Wire CRC Generator

64-Bit ROM ID in Application Note 27: Understanding and Using Cyclic

Each DS28E07 contains a unique ROM ID that is 64 bits Redundancy Checks with Maxim iButton® Products.
long. The first 8 bits are a 1-Wire family code. The next 48 The shift register bits are initialized to 0. Then, starting
bits are a unique serial number. The last 8 bits are a cyclic with the least significant bit of the family code, one bit at
redundancy check (CRC) of the first 56 bits. See Figure 3 a time is shifted in. After the 8th bit of the family code has
for details. The 1-Wire CRC is generated using a polyno- been entered, the serial number is entered. After the last
mial generator consisting of a shift register and XOR gates bit of the serial number has been entered, the shift reg-
as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. ister contains the CRC value. Shifting in the 8 bits of the
Additional information about the 1-Wire CRC is available CRC returns the shift register to all 0s.

iButton is a registered trademark of Maxim Integrated Products.

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DS28E07 1024-Bit, 1-Wire EEPROM

Memory Resources administrative data. As a factory default, the entire user

The memory of the DS28E07 consists of user memory, memory is unprotected and its contents are undefined.
administrative data, scratchpad, and a ROM ID. Table 1 The administrative data consists of 4 protection control
shows the size, access mode, and purpose of the various bytes, a copy-protection byte, the factory byte, and 2 user
memory areas. Brackets around an access mode indicate byte/manufacture ID bytes. The manufacturer ID can
possible restrictions, such as write protection or read pro- be a customer-supplied identification code that assists
tection. User memory and administrative data are located the application software in identifying the product the
in a linear address space, as shown in Figure 5. The user DS28E07 is associated with. Contact the factory to set
memory and the administrative data have unrestricted up and register a custom manufacturer ID. Any data read
read access. Each user memory page can be individually from addresses 0088 to 00FEh is undefined. Address
set to open (unprotected), write protected, or EPROM 00FFh provides read access to a byte that tells the chip
mode by setting the associated protection byte in the revision in hexadecimal notation, e.g., A1h.

Table 1. Memory Resources

NAME SIZE(BYTES) ACCESS MODE PURPOSE
User memory (EEPROM) 128 Read, (write) Application-specific data storage
Page protection settings, factory bytes, user
Administrative data 8 Read, (write), Internal read
bytes/manufacturer ID
Scratchpad 8 Read, write, internal read Intermediate data storage
ROM ID 8 Read, internal read 1-Wire network device address

ADDRESS RANGE TYPE DESCRIPTION PROTECTION CODES

0000h to 001Fh R/(W) User memory Page 0
0020h to 003Fh R/(W) User memory Page 1
0040h to 005Fh R/(W) User memory Page 2
0060h to 007Fh R/(W) User memory Page 3
55h: Write Protect P0; AAh: EPROM mode P0; 55h
0080h* R/(W) Protection Control Byte Page 0
or AAh: Write Protect 80h
55h: Write Protect P1; AAh: EPROM mode P1; 55h
0081h* R/(W) Protection Control Byte Page 1
or AAh: Write Protect 81h
55h: Write Protect P2; AAh: EPROM mode P2; 55h
0082h* R/(W) Protection Control Byte Page 2
or AAh: Write Protect 82h
55h: Write Protect P3; AAh: EPROM mode P3; 55h
0083h* R/(W) Protection Control Byte Page 3
or AAh: Write Protect 83h
55h or AAh: Copy Protect 0080:008Fh, and any
0084h* R/(W) Copy Protection Byte
write-protected Pages
AAh:Write Protect 85h, 86h, 87h;
0085h R Factory byte. Set at Factory.
55h: Write Protect 85h, unprotect 86h, 87h
0086h R/(W) User Byte/Manufacturer ID —
0087h R/(W) User Byte/Manufacturer ID —
0088h to 00FEh R Reserved —
00FFh R Chip Revision Code —
*Once programmed to AAh or 55h this address becomes read-only. All other codes can be stored but will neither write protect
the address nor activate any function.

Figure 5. Memory Map

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DS28E07 1024-Bit, 1-Wire EEPROM

In addition to the main EEPROM array, an 8-byte volatile The copy-protection byte is used for a higher level of
scratchpad is included. Writes to the EEPROM array are security and should only be used after all other protec-
a two-step process. First, data is written to the scratch- tion control bytes, user bytes, and write-protected pages
pad and then copied into the main array. This allows the are set to their final value. If the copy-protection byte is
user to first verify the data written to the scratchpad prior set to 55h or AAh, all copy attempts to the administrative
to copying into the main array. The device supports only data are blocked. In addition, all copy attempts to write-
8-byte copy operations. For data in the scratchpad to protected user memory pages (i.e., refresh) are blocked.
be valid for a copy operation, the address supplied with
a Write Scratchpad command must start on an 8-byte Address Registers and Transfer Status
boundary, i.e., the three LS-bits of the address must be The DS28E07 employs three address registers: TA1, TA2,
000b, and 8 full bytes must be written into the scratchpad. and E/S (Figure 6). These registers are common to many
other 1-Wire devices, but operate slightly differently with
The protection control bytes determine how incoming
the DS28E07. Registers TA1 and TA2 must be loaded
data on a Write Scratchpad command is loaded into the
with the target address to which the data is written or from
scratchpad. A protection setting of 55h (write protect)
which data is read. Register E/S is a read only transfer-
causes the incoming data to be ignored and the target
status register used to verify data integrity with write com-
address main memory data to be loaded into the scratch-
mands. E/S bits E[2:0] are loaded with the incoming T[2:0]
pad. A protection setting of AAh (EPROM mode) causes
on a Write Scratchpad command and increment on each
the logical AND of incoming data and target address
subsequent data byte. This is, in effect, a byte-ending off-
user memory data to be loaded into the scratchpad. Any
set counter within the 8-byte scratchpad. Bit 5 of the E/S
other protection control byte setting leaves the associated
register, called PF, is a logic 1 if the data in the scratchpad
user memory page open for unrestricted write access.
is not valid due to a loss of power or if the master sends
Note: For the EPROM mode to function, the entire
fewer bytes than needed to reach the end of the scratch-
affected memory page must first be programmed to FFh.
pad. For a valid write to the scratchpad, T[2:0] must be 0
Protection-control byte settings of 55h or AAh also write
and the master must have sent 8 data bytes. Bits 3, 4, and
protect the protection-control byte. The protection-control
6 have no function; they always read 0. The highest val-
byte setting of 55h does not block the copy. This allows
ued bit of the E/S register, called authorization accepted
write-protected data to be refreshed (i.e., reprogrammed
(AA), acts as a flag to indicate that the data stored in the
with the current data) in the device.
scratchpad has already been copied to the target memory
address. Writing data to the scratchpad clears this flag.

BIT # 7 6 5 4 3 2 1 0

TARGET ADDRESS (TA1) T7 T6 T5 T4 T3 T2 T1 T0

TARGET ADDRESS (TA2) T15 T14 T13 T12 T11 T10 T9 T8

ENDING ADDRESS WITH

DATA STATUS (E/S) AA 0 PF 0 0 E2 E1 E0
(READ ONLY)

Figure 6. Address Registers

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DS28E07 1024-Bit, 1-Wire EEPROM

Writing with Verification Memory Function Commands

To write data to the DS28E07, the scratchpad must be Figure 7 describes the protocols necessary for accessing
used as intermediate storage. First, the master issues the the memory of the DS28E07. An example on how to use
Write Scratchpad command to specify the desired target these functions to write to and read from the device is in
address, followed by the data to be written to the scratch- the Memory Function Example section. The communica-
pad. Note that Copy Scratchpad commands must be per- tion between the master and the DS28E07 takes place
formed on 8-byte boundaries, i.e., the three LSBs of the either at standard speed (default, OD = 0) or at overdrive
target address (T2, T1, T0) must be equal to 000b. If T[2:0] speed (OD = 1). If not explicitly set into overdrive mode,
are sent with nonzero values, the copy function is blocked. the DS28E07 assumes standard speed.
Under certain conditions (see the Write Scratchpad [0Fh]
section) the master receives an inverted CRC-16 of the Write Scratchpad [0Fh]
command, address (actual address sent), and data at the The Write Scratchpad command applies to the user
end of the Write Scratchpad command sequence. Knowing memory and the writable addresses of the administra-
this CRC value, the master can compare it to the value it tive data. For the scratchpad data to be valid for copying
has calculated to decide if the communication was suc- to the array, the user must perform a Write Scratchpad
cessful and proceed to the Copy Scratchpad command. If command of 8 bytes starting at a valid row boundary. The
the master could not receive the CRC-16, it should send Write Scratchpad command accepts invalid addresses
the Read Scratchpad command to verify data integrity. As and partial rows, but subsequent Copy Scratchpad com-
a preamble to the scratchpad data, the DS28E07 repeats mands are blocked.
the target address TA1 and TA2 and sends the contents After issuing the Write Scratchpad command, the master
of the E/S register. If the PF flag is set, data did not arrive must first provide the 2-byte target address, followed by
correctly in the scratchpad, or there was a loss of power the data to be written to the scratchpad. The data is writ-
since data was last written to the scratchpad. The master ten to the scratchpad starting at the byte offset of T[2:0].
does not need to continue reading; it can start a new trial The E/S bits E[2:0] are loaded with the starting byte offset
to write data to the scratchpad. Similarly, a set AA flag and increment with each subsequent byte. Effectively,
together with a cleared PF flag indicates that the device E[2:0] is the byte offset of the last full byte written to the
did not recognize the Write command. scratchpad. Only full data bytes are accepted.
If everything went correctly, both flags are cleared. Now When executing the Write Scratchpad command, the
the master can continue reading and verifying every data CRC generator inside the DS28E07 (Figure 13) calcu-
byte. After the master has verified the data, it can send the lates a CRC of the entire data stream, starting at the com-
Copy Scratchpad command, for example. This command mand code and ending at the last data byte as sent by the
must be followed exactly by the data of the three address master. This CRC is generated using the CRC-16 polyno-
registers, TA1, TA2, and E/S. The master should obtain mial by first clearing the CRC generator and then shifting
the contents of these registers by reading the scratchpad. in the command code (0Fh) of the Write Scratchpad com-
As well, a strong pullup (i.e., low impedance bypass) turns mand, the target addresses (TA1 and TA2), and all the
on after the Copy Scratchpad sequence for the duration of data bytes. Note that the CRC-16 calculation is performed
tPROG to enhance power delivery. The strong pullup can with the actual TA1 and TA2 and data sent by the master.
comprise an external FET circuitry or by driving logic 1 on The master can end the Write Scratchpad command at
the PIO of a host system with a good low-impedance drive any time. However, if the end of the scratchpad is reached
strength. If neither option is available then the designer (E[2:0] = 111b), the master can send 16 read time slots
can size RPUP accordingly for proper power delivery as and receive the CRC generated by the DS28E07.
to not violate VPUP minimum.
If a Write Scratchpad command is attempted to a write-
protected location, the scratchpad is loaded with the data
already existing in memory rather than the data transmit-
ted. Similarly, if the target address page is in EPROM
mode, the scratchpad is loaded with the bitwise logical
AND of the transmitted data and data already existing in
memory.

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DS28E07 1024-Bit, 1-Wire EEPROM

BUS MASTER Tx MEMORY FROM ROM FUNCTIONS

FUNCTION COMMAND FLOWCHART (FIGURE 9)

0Fh N AAh N TO FIGURE 7b

WRITE SCRATCHPAD? READ SCRATCHPAD?

Y Y

BUS MASTER Tx BUS MASTER Rx

TA1 (T[7:0]), TA2 (T[15:8]) TA1 (T[7:0]), TA2 (T[15:8]),
AND E/S BYTE

DS28E07
SETS PF = 1 DS28E07 SETS
CLEARS AA = 0 SCRATCHPAD
SETS E[2:0] = T[2:0] BYTE COUNTER = T[2:0]

MASTER Tx DATA BYTE DS28E07 BUS MASTER Rx

APPLIES ONLY
TO SCRATCHPAD INCREMENTS DATA BYTE FROM
IF THE MEMORY
BYTE COUNTER SCRATCHPAD
AREA IS NOT
PROTECTED.

DS28E07 IF WRITE PROTECTED,

Y
INCREMENTS MASTER Tx RESET? THE DS28E07 COPIES
Y
E[2:0] THE DATE BYTE FROM MASTER Tx RESET?
THE TARGET ADDRESS
N INTO THE SCRATCHPAD.
N
IF IN EPROM MODE,
THE DS28E07 LOADS
N
E[2:0] = 7? THE BITWISE LOGICAL N
AND OF THE TRANSMITTED BYTE COUNTER
BYTE AND THE DATA = E[2:0]?
Y BYTE FROM THE TARGETED
ADDRESS INTO THE Y
SCRATCHPAD.
N BUS MASTER Rx CRC-16
T[2:0] = 0?
OF COMMAND, ADDRESS,
E/S BYTE, AND DATA BYTES
Y AS SENT BY THE DS28E07

PF = 0

BUS MASTER N
MASTER Tx RESET?
Rx "1"s
DS28E07 Tx CRC-16 OF
COMMAND, ADDRESS,
Y
AND DATA BYTES AS THEY
WERE SENT BY THE BUS
MASTER

BUS MASTER N
MASTER Tx RESET?
Rx "1"s

Y
FROM FIGURE 7b

TO ROM FUNCTIONS
FLOWCHART (FIGURE 9)

Figure 7a. Memory Function Flowchart

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DS28E07 1024-Bit, 1-Wire EEPROM

FROM FIGURE 7a 55h N F0h N

COPY SCRATCHPAD? READ MEMORY?

Y Y
APPLICABLE TO ALL R/W
MEMORY LOCATIONS.
BUS MASTER Tx BUS MASTER Tx
TA1 (T[7:0]), TA2 (T[15:8]) TA1 (T[7:0]), TA2 (T[15:8])
AND E/S BYTE

Y
Y Y ADDRESS < 90h?
AUTH. CODE
T[15:0] < 0090h?
MATCH?
N DS28E07 SETS MEMORY
N N ADDRESS = (T[15:0])

N
PF = 0?
DS28E07 BUS MASTER Rx
INCREMENTS DATA BYTE FROM
Y
ADDRESS MEMORY ADDRESS
COUNTER

Y
COPY PROTECTED?
Y BUS MASTER
MASTER Tx RESET?
Rx "1"s
N

N
AA = 1

N
Y MASTER Tx RESET?
DS28E07 COPIES ADDRESS < 8Fh?
DURATION: tPROG SCRATCHPAD * Y
DATA TO ADDRESS
N

BUS MASTER
Rx "1"s DS28E07 Tx "0" BUS MASTER N
MASTER Tx RESET?
Rx "1"s

Y
N Y
MASTER Tx RESET? MASTER Tx RESET?

Y N

DS28E07 Tx "1"

N
MASTER Tx RESET?

Y
TO FIGURE 7a

* 1-Wire IDLE HIGH FOR POWER.

Figure 7b. Memory Function Flowchart (continued)

www.analog.com Analog Devices │ 12

DS28E07 1024-Bit, 1-Wire EEPROM

Read Scratchpad [AAh] alternating 0s and 1s are transmitted after the data has
The Read Scratchpad command allows verifying the tar- been copied until the master issues a reset pulse. If the
get address and the integrity of the scratchpad data. After PF flag is set or the target memory is copy protected, the
issuing the command code, the master begins reading. copy does not begin and the AA flag is not set.
The first two bytes are the target address. The next byte Read Memory [F0h]
is the ending offset/data status byte (E/S) followed by the
The Read Memory command is the general function to
scratchpad data, which may be different from what the
read data from the DS28E07. After issuing the command,
master originally sent. This is of particular importance if
the master must provide the 2-byte target address. After
the target address is within the administrative data sec-
these 2 bytes, the master reads data beginning from the
tion or a page in either write-protection mode or EPROM
target address and can continue until address 00FFh. If
mode. See the Write Scratchpad [0Fh] section for details.
the master continues reading, the result is logic 1s. The
The master should read through the scratchpad (E[2:0] -
device’s internal TA1, TA2, E/S, and scratchpad contents
T[2:0] + 1 bytes), after which it receives the inverted CRC
are not affected by a Read Memory command.
based on data as it was sent by the DS28E07. If the mas-
ter continues reading after the CRC, all data is logic 1.
1-Wire Bus System
Copy Scratchpad [55h] The 1-Wire bus is a system that has a single bus master
The Copy Scratchpad command is used to copy data and one or more slaves. In all instances, the DS28E07 is
from the scratchpad to writable memory sections. After a slave device. The bus master is typically a microcon-
issuing the Copy Scratchpad command, the master must troller. The discussion of this bus system is broken down
provide a 3-byte authorization pattern, which should into three topics: hardware configuration, transaction
have been obtained by an immediately preceding Read sequence, and 1-Wire signaling (signal types and timing).
Scratchpad command. This 3-byte pattern must exactly The 1-Wire protocol defines bus transactions in terms of
match the data contained in the three address registers the bus state during specific time slots, which are initiated
(TA1, TA2, E/S, in that order). If the pattern matches, the on the falling edge of sync pulses from the bus master.
target address is valid, the PF flag is not set, and the tar-
Hardware Configuration
get memory is not copy protected, then the AA flag is set
and the copy begins. All 8 bytes of scratchpad contents The 1-Wire bus has only a single line by definition; it is
are copied to the target memory location. The duration of important that each device on the bus be able to drive
the device’s internal data transfer is tPROG during which it at the appropriate time. To facilitate this, each device
the voltage on the 1-Wire bus must not fall below VPUP attached to the 1-Wire bus must have open-drain or three-
minimum. Best practice is to generate a strong pullup state outputs. The 1-Wire port of the DS28E07 is open
that turns on after the Copy Scratchpad sequence for the drain with an internal circuit equivalent to that shown in
duration of tPROG to enhance power delivery. A pattern of Figure 8.

VPUP

BUS MASTER DS28E07 1-Wire PORT

RPUP
DATA
Rx Rx

Tx IL Tx
Rx = RECEIVE
Tx = TRANSMIT
OPEN-DRAIN
100Ω MOSFET
PORT PIN

Figure 8. Hardware Configuration

www.analog.com Analog Devices │ 13

DS28E07 1024-Bit, 1-Wire EEPROM

A multidrop bus consists of a 1-Wire bus with multiple produces a wired-AND result). The resultant family code
slaves attached. The DS28E07 supports both a standard and 48-bit serial number result in a mismatch of the CRC.
and overdrive communication speed of 15.4kbps (max)
and 125kbps (max), respectively. The value of the pullup Match ROM [55h]
resistor primarily depends on the network size and load The Match ROM command, followed by a 64-bit ROM
conditions. The DS28E07 requires a pullup resistor of sequence, allows the bus master to address a specific
2.2kΩ (max) at any speed. DS28E07 on a multidrop bus. Only the DS28E07 that
exactly matches the 64-bit ROM sequence responds to
The idle state for the 1-Wire bus is high. If for any reason
the subsequent memory function command. All other
a transaction needs to be suspended, the bus must be left
slaves wait for a reset pulse. This command can be used
in the idle state if the transaction is to resume. If this does
with a single device or multiple devices on the bus.
not occur and the bus is left low for more than 15.5μs
(overdrive speed) or more than 120μs (standard speed), Search ROM [F0h]
one or more devices on the bus could be reset. When a system is initially brought up, the bus master
Transaction Sequence might not know the number of devices on the 1-Wire bus
or their ROM ID numbers. By taking advantage of the
The protocol for accessing the DS28E07 through the
wired-AND property of the bus, the master can use a pro-
1-Wire port is as follows:
cess of elimination to identify the ID of all slave devices.
● Initialization For each bit in the ID number, starting with the least sig-
● ROM function command nificant bit, the bus master issues a triplet of time slots.
On the first slot, each slave device participating in the
● Memory function command
search outputs the true value of its ID number bit. On the
● Transaction/data second slot, each slave device participating in the search
Initialization outputs the complemented value of its ID number bit. On
the third slot, the master writes the true value of the bit
All transactions on the 1-Wire bus begin with an initializa-
to be selected. All slave devices that do not match the
tion sequence. The initialization sequence consists of a
bit written by the master stop participating in the search.
reset pulse transmitted by the bus master followed by
If both of the read bits are zero, the master knows that
presence pulse(s) transmitted by the slave(s). The pres-
slave devices exist with both states of the bit. By choos-
ence pulse lets the bus master know that the DS28E07 is
ing which state to write, the bus master branches in the
on the bus and is ready to operate. For more details, see
search tree. After one complete pass, the bus master
the 1-Wire Signaling section.
knows the ROM ID number of a single device. Additional
1-Wire ROM Function Commands passes identify the ID numbers of the remaining devices.
Once the bus master has detected a presence, it can Refer to Application Note 187: 1-Wire Search Algorithm
issue one of the seven ROM function commands that the for a detailed discussion, including an example.
DS28E07 supports. All ROM function commands are 8 Skip ROM [CCh]
bits long. A list of these commands follows. See Figure 9.
This command can save time in a single-drop bus sys-
Read ROM [33h] tem by allowing the bus master to access the memory
The Read ROM command allows the bus master to read functions without providing the 64-bit ROM ID. If more
the DS28E07’s 8-bit family code, unique 48-bit serial than one slave is present on the bus and, for example,
number, and 8-bit CRC. This command can only be used a read command is issued following the Skip ROM com-
if there is a single slave on the bus. If more than one mand, data collision occurs on the bus as multiple slaves
slave is present on the bus, a data collision occurs when transmit simultaneously (open-drain pulldowns produce a
all slaves try to transmit at the same time (open drain wired-AND result).

www.analog.com Analog Devices │ 14

DS28E07 1024-Bit, 1-Wire EEPROM

BUS MASTER Tx
RESET PULSE
FROM FIGURE 9b
FROM MEMORY FUNCTIONS
FLOWCHART (FIGURE 7)

OD N
RESET PULSE? OD = 0

BUS MASTER Tx ROM DS28E07 Tx

FUNCTION COMMAND PRESENCE PULSE

33h 55h F0h CCh

READ ROM N MATCH ROM N SEARCH ROM N SKIP ROM N
COMMAND? COMMAND? COMMAND? COMMAND? TO FIGURE 9b

Y Y Y Y

RC = 0 RC = 0 RC = 0 RC = 0

DS28E07 Tx BIT 0
DS28E07 Tx
FAMILY CODE MASTER Tx BIT 0 DS28E07 Tx BIT 0
(1 BYTE) MASTER Tx BIT 0

N N
BIT 0 MATCH? BIT 0 MATCH?

Y
Y

DS28E07 Tx BIT 1
DS28E07 Tx
SERIAL NUMBER MASTER Tx BIT 1 DS28E07 Tx BIT 1
(6 BYTES) MASTER Tx BIT 1

N N
BIT 1 MATCH? BIT 1 MATCH?

Y Y

DS28E07 Tx BIT 63
DS28E07 Tx
MASTER Tx BIT 63 DS28E07 Tx BIT 63
CRC BYTE
MASTER Tx BIT 63

N N
BIT 63 MATCH? BIT 63 MATCH?

Y Y

RC = 1 RC = 1
TO FIGURE 9b

FROM FIGURE 9b

TO MEMORY FUNCTIONS
FLOWCHART (FIGURE 7)

Figure 9a. ROM Functions Flow Chart

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DS28E07 1024-Bit, 1-Wire EEPROM

TO FIGURE 9a

FROM FIGURE 9a A5h 3Ch 69h

RESUME N OVERDRIVE- N OVERDRIVE- N
COMMAND? SKIP ROM? MATCH ROM?

Y Y Y

RC = 0; OD = 1 RC = 0; OD = 1
N
RC = 1?

Y
MASTER Tx BIT 0

MASTER Tx Y N
BIT 0 MATCH? OD = 0
RESET?

N Y

MASTER Tx BIT 1

MASTER Tx Y
RESET?
N
N BIT 1 MATCH? OD = 0

MASTER Tx BIT 63

N
BIT 63 MATCH? OD = 0

RC = 1
FROM FIGURE 9a

TO FIGURE 9a

Figure 9b. ROM Functions Flow Chart (continued)

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DS28E07 1024-Bit, 1-Wire EEPROM

Resume [A5h] Overdrive-Match ROM [69h]

To maximize the data throughput in a multidrop environ- The Overdrive-Match ROM command followed by a 64-bit
ment, the Resume command is available. This command ROM sequence transmitted at overdrive speed allows the
checks the status of the RC bit and, if it is set, directly bus master to address a specific DS28E07 on a multi-
transfers control to the memory function commands, drop bus and to simultaneously set it in overdrive mode.
similar to a Skip ROM command. The only way to set the Only the DS28E07 that exactly matches the 64-bit ROM
RC bit is through successfully executing the Match ROM, sequence responds to the subsequent memory function
Search ROM, or Overdrive-Match ROM command. Once command. Slaves already in overdrive mode from a previ-
the RC bit is set, the device can repeatedly be accessed ous Overdrive-Skip ROM or successful Overdrive-Match
through the Resume command. Accessing another device ROM command remain in overdrive mode. All overdrive-
on the bus clears the RC bit, preventing two or more capable slaves return to standard speed at the next reset
devices from simultaneously responding to the Resume pulse of minimum 480μs duration. The Overdrive-Match
command. ROM command can be used with a single device or mul-
tiple devices on the bus.
Overdrive-Skip ROM [3Ch]
On a single-drop bus this command can save time by 1-Wire Signaling
allowing the bus master to access the memory functions The DS28E07 requires strict protocols to ensure data
without providing the 64-bit ROM ID. Unlike the normal integrity. The protocol consists of four types of signaling
Skip ROM command, the Overdrive-Skip ROM command on one line: reset sequence with reset pulse and presence
sets the DS28E07 into the overdrive mode (OD = 1). All pulse, write-zero, write-one, and read-data. Except for the
communication following this command must occur at presence pulse, the bus master initiates all falling edges.
overdrive speed until a reset pulse of minimum 480μs The DS28E07 can communicate at two different speeds:
duration resets all devices on the bus to standard speed standard speed and overdrive speed. If not explicitly set
(OD = 0). into the overdrive mode, the DS28E07 communicates at
When issued on a multidrop bus, this command sets all standard speed. While in overdrive mode, the fast timing
overdrive-supporting devices into overdrive mode. To applies to all waveforms.
subsequently address a specific overdrive-supporting To get from idle to active, the voltage on the 1-Wire line
device, a reset pulse at overdrive speed must be issued needs to fall from VPUP below the threshold VTL. To get
followed by a Match ROM or Search ROM command from active to idle, the voltage needs to rise from VILMAX
sequence. This speeds up the time for the search pro- past the threshold VTH. The time it takes for the voltage
cess. If more than one slave supporting overdrive is pres- to make this rise is seen in Figure 10 as ε, and its dura-
ent on the bus and the Overdrive-Skip ROM command tion depends on the pullup resistor (RPUP) used and the
is followed by a read command, data collision occurs on capacitance of the 1-Wire network attached. The voltage
the bus as multiple slaves transmit simultaneously (open- VILMAX is relevant for the DS28E07 when determining a
drain pulldowns produce a wired-AND result). logical level, not triggering any events.

MASTER Tx "RESET PULSE" MASTER Rx "PRESENCE PULSE"

ε
tMSP
VPUP
VIHMASTER
VTH

VTL
VILMAX
0V
tPDH
tRSTL tPDL tREC
tF
tRSTH

RESISTOR MASTER DS28E07

Figure 10. Initialization Procedure: Reset and Presence Pulse

www.analog.com Analog Devices │ 17

DS28E07 1024-Bit, 1-Wire EEPROM

Figure 10 shows the initialization sequence required to Master-to-Slave

begin any communication with the DS28E07. A reset pulse For a write-one time slot, the voltage on the data line
followed by a presence pulse indicates that the DS28E07 must have crossed the VTH threshold before the write-
is ready to receive data, given the correct ROM and one low time tW1LMAX is expired. For a write-zero time
memory function command. If the bus master uses slew- slot, the voltage on the data line must stay below the VTH
rate control on the falling edge, it must pull down the line threshold until the write-zero low time tW0LMIN is expired.
for tRSTL + tF to compensate for the edge. A tRSTL dura- For the most reliable communication, the voltage on the
tion of 480μs or longer exits the overdrive mode, returning data line should not exceed VILMAX during the entire
the device to standard speed. If the DS28E07 is in over- tW0L or tW1L window. After the VTH threshold has been
drive mode and tRSTL is no longer than 80μs, the device crossed, the DS28E07 needs a recovery time tREC before
remains in overdrive mode. If the device is in overdrive it is ready for the next time slot.
mode and tRSTL is between 80μs and 480μs, the device
resets, but the communication speed is undetermined. Slave-to-Master
After the bus master has released the line it goes into A read-data time slot begins like a write-one time slot.
receive mode. Now the 1-Wire bus is pulled to VPUP The voltage on the data line must remain below VTL until
through the pullup resistor or, in the case of a special the read low time tRL is expired. During the tRL window,
driver chip, through the active circuitry. When the thresh- when responding with a 0, the DS28E07 starts pulling
old VTH is crossed, the DS28E07 waits for tPDH and then the data line low; its internal timing generator determines
transmits a presence pulse by pulling the line low for tPDL. when this pulldown ends and the voltage starts rising
To detect a presence pulse, the master must test the logi- again. When responding with a 1, the DS28E07 does not
cal state of the 1-Wire line at tMSP. hold the data line low at all, and the voltage starts rising
as soon as tRL is over.
The tRSTH window must be at least the sum of tPDH-
MAX, tPDLMAX, and tRECMIN. Immediately after tRSTH is
The sum of tRL + δ (rise time) on one side and the internal
expired, the DS28E07 is ready for data communication. In timing generator of the DS28E07 on the other side define
a mixed population network, tRSTH should be extended to the master sampling window (tMSRMIN to tMSRMAX), in
minimum 480μs at standard speed and 48μs at overdrive which the master must perform a read from the data line.
speed to accommodate other 1-Wire devices. For the most reliable communication, tRL should be as
short as permissible, and the master should read close
Read/Write Time Slots to but no later than tMSRMAX. After reading from the data
Data communication with the DS28E07 takes place in line, the master must wait until tSLOT is expired. This
time slots that carry a single bit each. Write time slots guarantees sufficient recovery time tREC for the DS28E07
transport data from bus master to slave. Read time slots to get ready for the next time slot. Note that tREC speci-
transfer data from slave to master. Figure 11 illustrates fied herein applies only to a single DS28E07 attached to a
the definitions of the write and read time slots. 1-Wire line. For multidevice configurations, tREC must be
All communication begins with the master pulling the data extended to accommodate the additional 1-Wire device
line low. As the voltage on the 1-Wire line falls below input capacitance. Alternatively, an interface that performs
the threshold VTL, the DS28E07 starts its internal timing active pullup during the 1-Wire recovery time such as the
generator that determines when the data line is sampled special 1-Wire line drivers can be used.
during a write time slot and how long data is valid during
a read time slot.

www.analog.com Analog Devices │ 18

DS28E07 1024-Bit, 1-Wire EEPROM

WRITE-ONE TIME SLOT

tW1L
VPUP
VIHMASTER
VTH

VTL
VILMAX
0V
ε
tF
tSLOT

RESISTOR MASTER

WRITE-ZERO TIME SLOT

tW0L
VPUP
VIHMASTER
VTH

VTL
VILMAX
0V
ε
tF tREC
tSLOT

RESISTOR MASTER

READ-DATA TIME SLOT

tMSR
tRL
VPUP
VIHMASTER
VTH MASTER
SAMPLING
VTL WINDOW
VILMAX
0V
δ
tF tREC
tSLOT

RESISTOR MASTER DS28E07

Figure 11. Read/Write Timing Diagrams

www.analog.com Analog Devices │ 19

DS28E07 1024-Bit, 1-Wire EEPROM

Improved Network Behavior CRC Generation

(Switchpoint Hysteresis) The DS28E07 uses two different types of CRCs. One
In a 1-Wire environment, line termination is possible only CRC is an 8-bit type and is stored in the most significant
during transients controlled by the bus master (1-Wire byte of the 64-bit ROM ID. The bus master can compute
driver). 1-Wire networks, therefore, are susceptible to a CRC value from the first 56 bits of the 64-bit ROM ID
noise of various origins. Depending on the physical size and compare it to the value stored within the DS28E07 to
and topology of the network, reflections from end points determine if the ROM data has been received error-free.
and branch points can add up or cancel each other to The equivalent polynomial function of this CRC is X8 +
some extent. Such reflections are visible as glitches or X5 + X4 + 1. This 8-bit CRC is received in the true (non-
ringing on the 1-Wire communication line. Noise coupled inverted) form.
onto the 1-Wire line from external sources can also result The other CRC is a 16-bit type, generated according to
in signal glitching. A glitch during the rising edge of a time the standardized CRC-16 polynomial function X16 + X15
slot can cause a slave device to lose synchronization with + X2 + 1. This CRC is used for fast verification of a data
the master and, consequently, result in a Search ROM transfer when writing to or reading from the scratchpad. In
command coming to a dead end or cause a device-spe- contrast to the 8-bit CRC, the 16-bit CRC is always com-
cific function command to abort. For better performance municated in the inverted form. A CRC generator inside
in network applications, the DS28E07 uses a 1-Wire front- the DS28E07 chip (Figure 13) calculates a new 16-bit
end that is less sensitive to noise. CRC, as shown in the command flowchart (Figure 7).
The DS28E07’s 1-Wire front-end has the following features: The bus master compares the CRC value read from the
device to the one it calculates from the data and decides
1) There is additional lowpass filtering in the circuit that
whether to continue with an operation or to reread the
detects the falling edge at the beginning of a time
portion of the data with the CRC error.
slot. This reduces the sensitivity to high-frequency
noise. This additional filtering does not apply at over- With the Write Scratchpad command, the CRC is gener-
drive speed. ated by first clearing the CRC generator and then shifting
in the command code, the target addresses TA1 and TA2,
2) There is a hysteresis at the low-to-high switching
and all the data bytes as they were sent by the bus master.
threshold VTH. If a negative glitch crosses VTH but
The DS28E07 transmits this CRC only if E[2:0] = 111b.
does not go below VTH - VHY, it is not recognized
(Figure 12, Case A). The hysteresis is effective at With the Read Scratchpad command, the CRC is gener-
any 1-Wire speed. ated by first clearing the CRC generator and then shifting
3) There is a time window specified by the rising edge in the command code, the target addresses TA1 and TA2,
hold-off time tREH during which glitches are ignored, the E/S byte, and the scratchpad data as they were sent
even if they extend below the VTH - VHY threshold by the DS28E07. The DS28E07 transmits this CRC only if
(Figure 12, Case B, tGL < tREH). Deep voltage drops the reading continues through the end of the scratchpad.
or glitches that appear late after crossing the VTH For more information on generating CRC values, refer to
threshold and extend beyond the tREH window can- Application Note 27.
not be filtered out and are taken as the beginning of
a new time slot (Figure 12, Case C, tGL ≥ tREH).

tREH tREH
VPUP

VTH
VHY

CASE A CASE B CASE C

0V
tGL tGL

Figure 12. Noise Suppression Scheme

www.analog.com Analog Devices │ 20

DS28E07 1024-Bit, 1-Wire EEPROM

POLYNOMIAL = X16 + X15 + X2 + 1

1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH

STAGE STAGE STAGE STAGE STAGE STAGE STAGE STAGE

X0 X1 X2 X3 X4 X5 X6 X7

9TH 10TH 11TH 12TH 13TH 14TH 15TH 16TH

STAGE STAGE STAGE STAGE STAGE STAGE STAGE STAGE

X8 X9 X10 X11 X12 X13 X14 X15 X16 CRC OUTPUT

INPUT DATA

Figure 13. CRC-16 Hardware Description and Polynomial

Command-Specific 1-Wire Communication Protocol—Color Codes

Master to Slave Slave to Master Programming

Command-Specific 1-Wire Communication Protocol—Legend

SYMBOL DESCRIPTION
RST 1-Wire Reset Pulse generated by master.
PD 1-Wire Presence Pulse generated by slave.
Select Command and data to satisfy the ROM function protocol (e.g. Skip ROM [CCh], etc…).
WS Command “Write Scratchpad [0Fh]”.
RS Command “Read Scratchpad [AAh]”.
CPS Command “Copy Scratchpad [55h]”.
RM Command “Read Memory [F0h]”.
TA Target Address TA1, TA2.
TA-E/S Target Address TA1, TA2 with E/S byte.
<8 – T2:T0 bytes> Transfer of as many bytes as needed to reach the end of the scratchpad for a given target address.
<data to EOM> Transfer of as many data bytes as are needed to reach the end of the memory.
CRC16 Transfer of an inverted CRC16.
FF loop Indefinite loop where the master reads FF bytes.
AA loop Indefinite loop where the master reads AA bytes.
Programming Data transfer to EEPROM; no activity on the 1-Wire bus permitted during this time.

www.analog.com Analog Devices │ 21

DS28E07 1024-Bit, 1-Wire EEPROM

1-Wire Communication Examples

Write Scratchpad (CANNOT FAIL)

RST PD Select WS TA <8 – T2:T0 bytes> CRC16 FF loop

Read Scratchpad (CANNOT FAIL)

RST PD Select RS TA-E/S <8 – T2:T0 bytes> CRC16 FF loop

Copy Scratchpad (success)

RST PD Select CPS TA-E/S Programming AA loop

Copy Scratchpad (invalid ADDRESS or PF = 1 or COPY protected)

RST PD Select CPS TA-E/S FF loop

Read Memory (success)

RST PD Select RM TA <data to EOM> FF loop

Read Memory (invalid address)

RST PD Select RM TA FF loop

Ordering Information Package Information

PART TEMP RANGE PIN-PACKAGE For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
DS28E07+ -40°C to +85°C 3 TO-92
that a “+”, “#”, or “-” in the package code indicates RoHS status
DS28E07+T -40°C to +85°C 3 TO-92 (2k pcs) only. Package drawings may show a different suffix character, but
DS28E07P+ -40°C to +85°C 6 TSOC the drawing pertains to the package regardless of RoHS status.
DS28E07P+T -40°C to +85°C 6 TSOC (4k pcs)
PACKAGE PACKAGE OUTLINE LAND
DS28E07Q+T -40°C to +85°C 6 TDFN-EP* (2.5k pcs) TYPE CODE NO. PATTERN NO.
2 SFN (6mm x 6mm) 3 TO-92
DS28E07G+T -40°C to +85°C Q3+1 21-0248 —
(2.5k pcs) (Bulk)
2 SFN (3.5mm x 6.5mm) 3 TO-92
DS28E07GA+T -40°C to +85°C Q3+4 21-0250 —
(2.5k pcs) (T&R)
2 SFN (3.5mm x 5mm) 6 TSOC D6+1 21-0382 90-0321
DS28E07GB+T -40°C to +85°C
(2.5k pcs)
6 TDFN-EP T633+2 21-0137 90-0058
+Denotes a lead-free/RoHS-compliant package.
T = Tape and reel. 2 SFN
G266N+1 21-0390 —
*EP = Exposed pad. (6mm x 6mm)
2 SFN
Chip Information (3.5mm x 6.5mm)
T23A6N+1 21-0575 90-0431
PROCESS: CMOS 2 SFN
S23A5N+1 21-0661 90-0398
(3.5mm x 5mm)

www.analog.com Analog Devices │ 22

DS28E07 1024-Bit, 1-Wire EEPROM

Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 9/15 Initial release —
1 5/16 Removed future product references 22
Added row to Output Low Voltage parameter and removed Note 12 (remaining
2 1/17 2, 4
Notes were not renumbered per request)
3 7/21 Updated Electrical Characteristics table 3
Updated Pin Configurations, Pin Description table, Ordering Information table,
4 9/21 5, 6, 22
and Package Information table
5 12/21 Updated Ordering Information table 22
6 1/22 Updated Electrical Characteristics table 3
7 4/22 Updated Ordering Information table 22

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is
assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that
may result from its use. Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are
the property of their respective owners.

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Mouser Electronics

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