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ISL6269 SIL or
www.i port Center FN9177
ntersil a
High-Performance Notebook PWM Controller with Bias Regulator and .com/t t Rev 3.00
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Audio-Frequency Clamp June 25, 2009

The ISL6269 IC is a Single-Phase Synchronous-Buck PWM Features

controller featuring Intersil's Robust Ripple Regulator (R3)
technology that delivers truly superior dynamic response to • High performance R3 technology
input voltage and output load transients. Integrated • Fast transient response
MOSFET drivers, 5V LDO and bootstrap diode result in • +0.6V Internal Reference
fewer components and smaller implementation area. - ±0.6% tolerance over the commercial temperature
Intersil’s R3 technology combines the best features of fixed- range (0°C to +70°C)
frequency PWM and hysteretic PWM while eliminating many - ±1.0% tolerance over the industrial temperature range
of their shortcomings. R3 technology employs an innovative (-40°C to +85°C)
modulator that synthesizes an AC ripple voltage signal VR, • Wide input voltage range: +7.0V to +25.0V
analogous to the output inductor ripple current. The AC signal • Output voltage range: +0.6V to +3.3V
VR enters a window comparator where the lower threshold is • Wide output load range: 0A to 25A
the error amplifier output VCOMP, and the upper threshold is a
• Selectable diode emulation mode for increased light load
programmable voltage reference VW, resulting in generation efficiency
of the PWM signal. The voltage reference VW sets the steady
• Programmable PWM frequency: 200kHz to 600kHz
state PWM frequency. Both edges of the PWM can be
modulated in response to input voltage transients and output • Pre-biased output start-up capability
load transients, much faster than conventional fixed frequency • Internal 5V LDO for self-biasing
PWM controllers. Unlike a conventional hysteretic converter, • Integrated MOSFET drivers and bootstrap diode
the ISL6269 has an error amplifier that provides ±1% voltage • Internal digital soft-start
regulation at the FB pin. • Power good monitor
The ISL6269 has a 1.5ms digital soft-start and can be started • PWM minimum frequency above audible spectrum
into a pre-biased output voltage. A resistor divider is used to • Fault protection
program the output voltage setpoint. The ISL6269 can be - Undervoltage protection
configured to operate in continuous-conduction-mode (CCM) - Soft crowbar overvoltage protection
or diode-emulation-mode (DEM), which improves light-load
- Low-side MOSFET rDS(ON) overcurrent protection
efficiency. In CCM the controller always operates as a
- Over-temperature protection
synchronous rectifier however, when DEM is enabled the
- Fault identification by PGOOD pull-down resistance
low-side MOSFET is permitted to stay off, blocking negative
current flow into the low-side MOSFET from the output • Pb-free (RoHS compliant)
inductor.
Applications
Pinout
• PCI express graphical processing unit
ISL6269
(16 LD 4x4 QFN) • Auxiliary power rail
TOP VIEW • VRM
PGOOD

• Network adapter
PHASE

BOOT
UG

Ordering Information
16 15 14 13
PART TEMP
VIN 1 12 PVCC NUMBER PART RANGE PACKAGE PKG.
(Note) MARKING (°C) (Pb-free) DWG. #
VCC 2 11 LG
GND ISL6269CRZ* 62 69CRZ -10 to +100 16 Ld 4x4 QFN L16.4x4
FCCM 3 10 PGND ISL6269IRZ* 62 69IRZ -40 to +100 16 Ld 4x4 QFN L16.4x4
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on
EN 4 9 ISEN
reel specifications.
5 6 7 8 NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
COMP

FSET

VO
FB

materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.

FN9177 Rev 3.00 Page 1 of 14

June 25, 2009
June 25, 2009
FN9177 Rev 3.00

Block Diagram

ISL6269
VIN
VO
GND
PACKAGE BOTTOM
5V LDO
PWM FREQUENCY
FSET
CONTROL
VCC

VREF  

EN gmVIN VW

 
R
 PWM
Q
OVP
S

 VR 
gmVO
   VCOMP

CR


UVP 
BOOT


EA DRIVER UG
FB

POR DIGITAL SOFT-START

PWM CONTROL
COMP PHASE
SHOOT THROUGH
ISEN  PROTECTION
OCP PVCC
IOC 
30 90 60
DRIVER LG

150°OT
Page 2 of 14

PGOOD PGND

FCCM

FIGURE 1. SCHEMATIC BLOCK DIAGRAM

ISL6269

Typical Application

ISL6269
VIN
7V TO 25V
PGOOD VIN

CIN
RPGOOD

QHIGH_SIDE
PVCC UG

RPVCC

VCC BOOT

CPVCC CVCC
CBOOT LOUT VOUT
0.6V TO 3.3V
GND PHASE

RSEN COUT

FCCM ISEN

QLOW_SIDE

EN LG

RCOMP
COMP PGND

CCOMP1

FB FSET
VO
CCOMP2 RFSET CFSET

RBOTTOM RTOP

FIGURE 2. ISL6269 TYPICAL APPLICATION SCHEMATIC

FN9177 Rev 3.00 Page 3 of 14

June 25, 2009
ISL6269

Absolute Voltage Ratings Thermal Information

ISEN, VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V Thermal Resistance (Typical, Notes 1, 2) JA (°C/W) JC (°C/W)
VCC, PGOOD to GND . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V QFN Package. . . . . . . . . . . . . . . . . . . . 48 11.5
PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7.0V Junction Temperature Range. . . . . . . . . . . . . . . . . .-55C to +150C
GND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EN, FCCM . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to GND, VCC +3.3V ISL6269CRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10C to +100C
VO, FB, COMP, FSET . . . . . . . . . . . . . . . -0.3V to GND, VCC +0.3V ISL6269IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
PHASE to GND (DC) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C
(<100ns Pulse Width, 10µJ) . . . . . . . . . . . . . . . . . . . . . . . . . -5.0V Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
BOOT to GND, or PGND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V http://www.intersil.com/pbfree/Pb-FreeReflow.asp
BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
UG (DC) . . . . . . . . . . . . . . . . . . . . . . .-0.3V to PHASE, BOOT +0.3V
Recommended Operating Conditions
(<200ns Pulse Width, 20µJ) . . . . . . . . . . . . . . . . . . . . . . . . -4.0V
LG (DC) . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to PGND, PVCC +0.3V Ambient Temperature Range
(<100ns Pulse Width, 4µJ) . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V ISL6269CRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
ISL6269IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Supply Voltage (VIN to GND) . . . . . . . . . . . . . . . . . . . . . . 7V to 25V
PVCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±5%

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

NOTES:
1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications These specifications apply for TA = -40°C to +100°C, unless otherwise stated. All typical specifications TA = +25°C,
PVCC = 5V, VIN = 15V. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production tested.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
VIN
VIN Input Voltage Range VVIN 7.0 - 25 V
VIN Input Bias Current IVIN EN = 5V, VIN = 25V - 2.2 3.0 mA
VIN Shutdown Current IVIN_SHDN EN = GND, VIN= 25V - 0.1 1.0 µA
VCC LDO
VCC Output Voltage Range VVCC VIN = 7V to 25V, IVCC = 0mA to 80mA 4.75 5.00 5.25 V
Rising VCC POR Threshold Voltage VVCC_THR TA = -10°C to +100°C 4.35 4.45 4.55 V
4.33 4.45 4.55 V
Falling VCC POR Threshold Voltage V TA = -10°C to +100°C 4.10 4.20 4.30 V
VCC_THF
4.08 4.20 4.30 V
PVCC
PVCC Shutdown Current IPVCC_SHDN EN = GND, PVCC = 5V - 0.1 1.0 µA
REGULATION
Reference Voltage VREF - 0.6 - V
Voltage Regulation Accuracy V FB connected to COMP, TA = -10°C to +100°C -0.6 - +0.6 %
REG
FB connected to COMP, TA = -40°C to +100°C -1.0 - +1.0 %
PWM
Frequency Range fSW FCCM = 5V 200 - 600 kHz
fAUDIO FCCM = GND, TA = -10°C to +100°C 19 28 - kHz
FCCM to GND 18 28 - kHz
Frequency-Set Accuracy fSW = 300kHz -12 - +12 %
VO Range VVO 0.60 - 3.30 V

FN9177 Rev 3.00 Page 4 of 14

June 25, 2009
ISL6269

Electrical Specifications These specifications apply for TA = -40°C to +100°C, unless otherwise stated. All typical specifications TA = +25°C,
PVCC = 5V, VIN = 15V. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production tested. (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
VO Input Leakage IVO VO = 0.60V - 1.3 - µA
VO = 3.30V - 7.0 - µA
ERROR AMPLIFIER
FB Input Bias Current IFB FB = 0.60V -0.5 - +0.5 µA
COMP Source Current ICOMP_SRC FB = 0.40V, COMP = 3.20V - 2.5 - mA
COMP Sink Current ICOMP_SNK FB = 0.80V, COMP = 0.30V - 0.3 - mA
COMP High Clamp Voltage VCOMP_HC FB = 0.40V, Sink 50µA 3.10 3.40 3.65 V
COMP Low Clamp Voltage VCOMP_LC FB = 0.80V, Source 50µA 0.09 0.15 0.21 V
POWER GOOD
PGOOD Pull-down Impedance RPG_SS PGOOD = 5mA Sink, TA = -10°C to +100°C 75 95 125 
PGOOD = 5mA Sink 67 95 125 
RPG_UV PGOOD = 5mA Sink, TA = -10°C to +100°C 75 95 125 
PGOOD = 5mA Sink 67 95 125 
RPG_OV PGOOD = 5mA Sink, TA = -10°C to +100°C 50 63 85 
PGOOD = 5mA Sink 45 63 85 
RPG_OC PGOOD = 5mA Sink, TA = -10°C to +100°C 25 32 45 
PGOOD = 5mA Sink 22 32 45 
PGOOD Leakage Current IPGOOD PGOOD = 5V - 0.1 1.0 µA
PGOOD Maximum Sink Current - 5.0 - mA
PGOOD Soft-Start Delay tSS EN High to PGOOD High, TA = -10°C to +100°C 2.20 2.75 3.30 ms
EN High to PGOOD High 2.20 2.75 3.50 ms
GATE DRIVER
UG Pull-Up Resistance RUGPU 200mA Source Current - 1.0 1.5 
UG Source Current IUGSRC UG - PHASE = 2.5V - 2.0 - A
UG Sink Resistance RUGPD 250mA Sink Current - 1.0 1.5 
UG Sink Current IUGSNK UG - PHASE = 2.5V - 2.0 - A
LG Pull-Up Resistance RLGPU 250mA Source Current - 1.0 1.5 
LG Source Current ILGSRC LG - PGND = 2.5V - 2.0 - A
LG Sink Resistance RLGPD 250mA Sink Current - 0.5 0.9 
LG Sink Current ILGSNK LG - PGND = 2.5V - 4.0 - A
UG to LG Deadtime tUGFLGR UG falling to LG rising, no load - 21 - ns
LG to UG Deadtime tLGFUGR LG falling to UG rising, no load - 14 - ns
BOOTSTRAP DIODE
Forward Voltage VF PVCC = 5V, IF = 2mA - 0.58 - V
Reverse Leakage IR VR = 25V - 0.2 - µA
CONTROL INPUTS
EN High Threshold VENTHR 2.0 - - V
EN Low Threshold VENTHF - - 0.5 V
FCCM High Threshold VFCCMTHR 2.0 - - V
FCCM Low Threshold VFCCMTHF - - 1.0 V
EN Leakage IENL EN = 0V - 0.1 1.0 µA
IENH EN = 5.0V - 20 - µA

FN9177 Rev 3.00 Page 5 of 14

June 25, 2009
ISL6269
Electrical Specifications These specifications apply for TA = -40°C to +100°C, unless otherwise stated. All typical specifications TA = +25°C,
PVCC = 5V, VIN = 15V. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production tested. (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
FCCM Leakage IFCCML FCCM = 0V - 0.1 1.0 µA
IFCCMH FCCM = 5.0V - 2.0 - µA
PROTECTION
ISEN OCP Threshold IOC ISEN sourcing, TA = -10°C to +100°C 19 26 33 µA
ISEN sourcing 17 26 33 µA
ISEN Short-Circuit Threshold ISC ISEN sourcing - 50 - µA
UVP Threshold VUV 81 84 87 %
OVP Rising Threshold VOVR 113 116 119 %
OVP Falling Threshold VOVF 100 103 106 %
OTP Rising Threshold TOTR - 150 - °C
OTP Hysteresis TOTHYS - 25 - °C

Functional Pin Descriptions FB (Pin 6)

The FB pin is the inverting input of the control-loop error
VIN (Pin 1)
amplifier. The converter output voltage regulates to 600mV
The VIN pin measures the converter input voltage which is a from the FB pin to the GND pin. Program the desired output
required input to the R3 PWM modulator. The VIN pin is also voltage with a resistor network connected across the VO,
the input source for the integrated +5V LDO regulator. FB, and GND pins. Select the resistor values such that FB to
Connect across the drain of the high-side MOSFET to the GND is 600mV when the converter output voltage is at the
GND pin. programmed regulation value.
VCC (Pin 2) FSET (Pin 7)
The VCC pin is the output of the integrated +5V LDO The FSET pin programs the PWM switching frequency.
regulator, which provides the bias voltage for the IC. The Program the desired PWM frequency with a resistor and a
VCC pin delivers regulated +5V whenever the EN pin is capacitor connected across the FSET and GND pins.
pulled above VENTHR. For best performance the LDO
requires at least a 1µF MLCC decouple capacitor to the VO (Pin 8)
GND pin. The VO pin measures the converter output voltage and is
used exclusively as an input to the R3 PWM modulator.
FCCM (Pin 3)
Connect at the physical location where the best output
The FCCM pin configures the controller to operate in forced- voltage regulation is desired.
continuous-conduction-mode (FCCM) or diode-emulation-
mode (DEM). DEM is disabled when the FCCM pin is pulled ISEN (Pin 9)
above the rising threshold voltage VFCCMTHR, conversely The ISEN pin programs the threshold of the OCP
DEM is enabled when the FCCM pin is pulled below the overcurrent fault protection. Program the desired OCP
falling threshold voltage VFCCMTHF. threshold with a resistor connected across the ISEN and
PHASE pins. The OCP threshold is programmed to detect
EN (Pin 4)
the peak current of the output inductor. The peak current is
The EN pin is the on/off switch of the IC. When the EN pin is the sum of the DC and AC components of the inductor
pulled above the rising threshold voltage VENTHR, the VCC current.
5V LDO ramps and begins regulating. The soft-start
sequence begins after VVCC is above the power-on reset PGND (Pin 10)
(POR) rising threshold voltage VVCC_THR . When the EN pin The PGND pin conducts the turn-off transient current
is pulled below the falling threshold voltage VENTHF, PWM through the LG gate driver. The PGND pin must be
immediately stops and VVCC decays below the POR falling connected to complete the pull-down circuit of the LG gate
threshold voltage VVCC_THF, at which time the IC turns off. driver. The PGND pin should be connected to the source of
the low-side MOSFET through a low impedance path,
COMP (Pin 5)
preferably in parallel with the trace connecting the LG pin to
The COMP pin is the output of the control-loop error the gate of the low-side MOSFET. The adaptive shoot-
amplifier. Compensation components for the control-loop through protection circuit, measures the low-side MOSFET
connect across the COMP and FB pins. gate-source voltage from the LG pin to the PGND pin.

FN9177 Rev 3.00 Page 6 of 14

June 25, 2009
ISL6269

LG (Pin 11) The negative slope of VR can be written as:

The LG pin is the output of the low-side MOSFET gate driver. V RNEG = g m  V OUT (EQ. 2)
Connect to the gate of the low-side MOSFET.
Where gm is the gain of the transconductance amplifier.
PVCC (Pin 12)
A window voltage VW is referenced with respect to the error
The PVCC pin is the input voltage bias for the LG low-side amplifier output voltage VCOMP, creating an envelope into
MOSFET gate driver. Connect +5V from the PVCC pin to the which the ripple voltage VR is compared. The amplitude of VW
PGND pin. Decouple with at least 1µF of an MLCC capacitor is set by a resistor connected across the FSET and GND pins.
across the PVCC and PGND pins. The VCC output may be The VR, VCOMP, and VW signals feed into a window
used for the PVCC input voltage source. comparator in which VCOMP is the lower threshold voltage and
BOOT (Pin 13) VW is the higher threshold voltage. Figure 3 shows PWM
pulses being generated as VR traverses the VW and VCOMP
The BOOT pin stores the input voltage for the UG high-side
thresholds . The PWM switching frequency is proportional to
MOSFET gate driver. Connect an MLCC capacitor across the
the slew rates of the positive and negative slopes of VR; the
BOOT and PHASE pins. The boot capacitor is charged through
PWM switching frequency is inversely proportional to the
an internal boot diode connected from the PVCC pin to the
voltage between VW and VCOMP.
BOOT pin, each time the PHASE pin drops below PVCC minus
the voltage dropped across the internal boot diode.

UG (Pin 14)
Ripple Capacitor Voltage CR Window Voltage VW
The UG pin is the output of the high-side MOSFET gate driver.
Connect to the gate of the high-side MOSFET.

PHASE (Pin 15)

The PHASE pin detects the voltage polarity of the PHASE
node and is also the current return path for the UG high-side Error Amplifier Voltage VCOMP
MOSFET gate driver. Connect the PHASE pin to the node
consisting of the high-side MOSFET source, the low-side
MOSFET drain, and the output inductor.

PGOOD (Pin 16) PWM

The PGOOD pin is an open-drain output that indicates when

the converter is able to supply regulated voltage. Connect the
PGOOD pin to +5V through a pull-up resistor. FIGURE 3. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
GND (Bottom Pad)
EN, LDO, and POR
Signal common of the IC. Unless otherwise stated, signals are
The VCC LDO regulates by pulling up towards the voltage at
referenced to the GND pin, not the PGND pin.
the VIN pin; the LDO has no pull-down capability. The LDO is
Theory of Operation enabled when the EN pin surpasses the rising EN threshold
voltage VENTHR. The ISL6269 is enabled once VVCC has
Modulator increased above the rising power-on reset (POR) VVCC_THR
The ISL6269 is a hybrid of fixed frequency PWM control, and threshold voltage. The controller immediately stops generating
variable frequency hysteretic control. Intersil’s R3 technology PWM and disables the LDO when the EN pin is pulled below
can simultaneously affect the PWM switching frequency and the falling EN threshold voltage VENTHF . The IC completely
PWM duty cycle in response to input voltage and output load shuts off when VVCC decreases below the falling POR
transients. The term “Ripple” in the name “Robust-Ripple- VVCC_THF threshold voltage.
Regulator” refers to the converter output inductor ripple
Soft-Start, and PGOOD
current, not the converter output ripple voltage. The R3
modulator synthesizes an AC signal VR, which is an ideal The ISL6269 uses a digital soft-start circuit to ramp the output
representation of the output inductor ripple current. The duty- voltage of the converter to the programmed regulation setpoint
cycle of VR is the result of charge and discharge current at a predictable slew rate. The slew rate of the soft-start
through a ripple capacitor CR. The current through CR is sequence has been selected to limit the inrush current through
provided by a transconductance amplifier gm that measures the output capacitors as they charge to the desired regulation
the VIN and VO pin voltages. The positive slope of VR can be voltage. When the EN pin is pulled above the rising EN
written as: threshold voltage VENTHR and VVCC has ramped above the
rising POR VVCC_THR threshold voltage, the PGOOD Soft-Start
V RPOS =  g m    V IN – V OUT  (EQ. 1)
Delay tSS starts and the output voltage begins to rise. The

FN9177 Rev 3.00 Page 7 of 14

June 25, 2009
ISL6269

output voltage enters regulation in approximately 1.5ms and the gate-driver output voltage is measured across the LG and
PGOOD pin goes to high impedance once tSS has elapsed. PGND pins. The power for the LG gate-driver is sourced
directly from the PVCC pin. The power for the UG gate-driver is
1.5ms sourced from a “boot” capacitor connected across the BOOT
VOUT
and PHASE pins. The boot capacitor is charged from a 5V bias
supply through a “boot diode” each time the low-side MOSFET
VCC
turns on, pulling the PHASE pin low. The ISL6269 has an
integrated boot diode connected from the PVCC pin to the
BOOT pin.
EN

tLGFUGR tUGFLGR

50%
PGOOD
UG
2.75ms

FIGURE 4. SOFT-START SEQUENCE

LG

The PGOOD pin indicates when the converter is capable of 50%

supplying regulated voltage. The PGOOD pin is an undefined

impedance if VVCC has not reached the rising POR threshold
VVCC_THR, or if VVCC is below the falling POR threshold
VVCC_THF. The ISL6269 features a unique fault-identification
FIGURE 5. LG AND UG DEAD-TIME
capability that can drastically reduce trouble-shooting time and
effort. The pull-down resistance of the PGOOD pin
Diode Emulation
corresponds to the fault status of the controller. During soft-
start or if an undervoltage fault occurs, the PGOOD pulldown The ISL6269 normally operates in continuous-conduction-
resistance is 95, or 30 for an overcurrent fault, or 60 for an mode (CCM), minimizing conduction losses by forcing the low-
overvoltage fault. side MOSFET to operate as a synchronous rectifier. An
improvement in light-load efficiency is achieved by allowing the
TABLE 1. PGOOD PULL-DOWN RESISTANCE converter to operate in diode-emulation-mode (DEM), where
CONDITION PGOOD RESISTANCE the low-side MOSFET behaves as a smart-diode, forcing the
device to block negative inductor current flow. The ISL6269
VCC Below POR Undefined
can be configured to operate in DEM by setting the FCCM pin
Soft Start or Undervoltage 95 low. Setting the FCCM pin high will disable DEM.
Overvoltage 60 Positive-going inductor current flows from either the source of
Overcurrent 30 the high-side MOSFET, or the drain of the low-side MOSFET.
Negative-going inductor current usually flows into the drain of
MOSFET Gate-Drive Outputs LG and UG the low-side MOSFET. When the low-side MOSFET conducts
The ISL6269 has internal gate-drivers for the high-side and positive inductor current, the phase voltage will be negative
low-side N-Channel MOSFETs. The LG gate-driver is with respect to the GND and PGND pins. Conversely, when the
optimized for low duty-cycle applications where the low-side low-side MOSFET conducts negative inductor current, the
MOSFET conduction losses are dominant, requiring a low phase voltage will be positive with respect to the GND and
rDS(ON) MOSFET. The LG pulldown resistance is small in PGND pins. Negative inductor current occurs when the output
order to clamp the gate of the MOSFET below the VGS(th) at load current is less than ½ the inductor ripple current. Sinking
turnoff. The current transient through the gate at turnoff can be negative inductor current through the low-side MOSFET lowers
considerable because the switching charge of a low rDS(ON) efficiency through unnecessary conduction losses. Efficiency
MOSFET can be large. Adaptive shoot-through protection can be further improved with a reduction of unnecessary
prevents a gate-driver output from turning on until the opposite switching losses by reducing the PWM frequency. It is
gate-driver output has fallen below approximately 1V. The characteristic of the R3 architecture for the PWM frequency to
dead-time shown in Figure 5 is extended by the additional decrease while in diode emulation. The extent of the frequency
period that the falling gate voltage stays above the 1V reduction is proportional to the reduction of load current. The
threshold. The high-side gate-driver output voltage is ISL6269 features an audio filter that clamps the minimum
measured across the UG and PHASE pins while the low-side

FN9177 Rev 3.00 Page 8 of 14

June 25, 2009
ISL6269

PWM frequency to a level beyond human hearing when the Where:

output load current becomes low enough. - RSEN () is the resistor used to program the overcurrent
setpoint
With FCCM pulled low, the converter will automatically enter
DEM after the PHASE pin has detected positive voltage, while - ISEN is the current sense current that is sourced from the
ISEN pin
the LG gate-driver pin is high, for eight consecutive PWM
pulses. The converter will return to CCM on the following cycle - IOC is the ISEN threshold current sourced from the ISEN
pin that will activate the OCP circuit
after the PHASE pin detects negative voltage, indicating that
the body diode of the low-side MOSFET is conducting positive - IFL is the maximum continuous DC load current
inductor current. - IPP is the inductor peak-to-peak ripple current
- OCSP is the desired overcurrent setpoint expressed as a
Overcurrent and Short-Circuit Protection multiplier relative to IFL
The overcurrent protection (OCP) and short circuit protection
Overvoltage Protection
(SCP) setpoint is programmed with resistor RSEN that is
connected across the ISEN and PHASE pins. The PHASE pin is When an OVP fault is detected, the PGOOD pin will pull-down
connected to the drain terminal of the low-side MOSFET. to 60and latch-off the converter. The OVP fault will remain
latched until the VVCC has decayed below the falling POR
The SCP setpoint is internally set to twice the OCP setpoint. threshold voltage VVCC_THF.
When an OCP or SCP fault is detected, the PGOOD pin will
pulldown to 30and latch off the converter. The fault will The OVP fault detection circuit triggers after the voltage across
remain latched until the EN pin has been pulled below the the FB and GND pins has increased above the rising
falling EN threshold voltage VENTHF or if VVCC has decayed overvoltage threshold VOVR. Although the converter has
below the falling POR threshold voltage VVCC_THF. latched-off in response to an OVP fault, the LG gate-driver
output will retain the ability to toggle the low-side MOSFET on
The OCP circuit does not directly detect the DC load current and off, in response to the output voltage transversing the
leaving the converter. The OCP circuit detects the peak of VOVR and VOVF thresholds.
positive-flowing output inductor current. The low-side MOSFET
drain current ID is assumed to be equal to the positive output Undervoltage Protection
inductor current when the high-side MOSFET is off. The When a UVP fault is detected, the PGOOD pin will pull down to
inductor current develops a negative voltage across the 95and latch-off the converter. The fault will remain latched
rDS(ON) of the low-side MOSFET that is measured shortly after until the EN pin has been pulled below the falling EN threshold
the LG gate-driver output goes high. The ISEN pin sources the voltage VENTHF or if VVCC has decayed below the falling POR
OCP sense current ISEN, through the OCP programming threshold voltage VVCC_THF. The UVP fault detection circuit
resistor RSEN, forcing the ISEN pin to zero volts with respect to triggers after the voltage across the FB and GND pins has
the GND pin. The negative voltage across the PHASE and fallen below the undervoltage threshold VUV.
GND pins is nulled by the voltage dropped across RSEN as
Over-Temperature
ISEN conducts through it. An OCP fault occurs if ISEN rises
above the OCP threshold current IOC while attempting to null When the temperature of the ISL6269 increases above the
the negative voltage across the PHASE and GND pins. ISEN rising threshold temperature TOTR, the IC will enter an OTP
must exceed IOC on all the PWM pulses that occur within state that suspends the PWM , forcing the LG and UG
20µs. If ISEN falls below IOC on a PWM pulse before 20µs has gate-driver outputs low. The status of the PGOOD pin does not
elapsed, the timer will be reset. An SCP fault will occur within change nor does the converter latch-off. The PWM remains
10µs when ISEN exceeds twice IOC. The relationship between suspended until the IC temperature falls below the hysteresis
ID and ISEN is written as: temperature TOTHYS at which time normal PWM operation
resumes. The OTP state can be reset if the EN pin is pulled
I SEN  R SEN = I D  r DS  ON  (EQ. 3)
below the falling EN threshold voltage VENTHF or if VVCC
The value of RSEN is then written as: decays below the falling POR threshold voltage VVCC_THF. All
other protection circuits function normally during OTP. It is
I PP likely that the IC will detect an UVP fault because in the
 I + -------- -  OC SP  r DS  ON 
 FL 2  absence of PWM, the output voltage immediately decays
R SEN = ---------------------------------------------------------------------------- (EQ. 4)
I OC below the undervoltage threshold VUV; the PGOOD pin will
pull-down to 95and latch-off the converter. The UVP fault will
remain latched until the EN pin has been pulled below the
falling EN threshold voltage VENTHF or if VVCC has decayed
below the falling POR threshold voltage VVCC_THF.

FN9177 Rev 3.00 Page 9 of 14

June 25, 2009
ISL6269

Programming the Output Voltage

When the converter is in regulation there will be 600mV from
R2 C1
the FB pin to the GND pin. Connect a two-resistor voltage C2
divider across the VO pin and the GND pin with the output
node connected to the FB pin. Scale the voltage-divider
network such that the FB pin is 600mV with respect to the GND
COMP R1
pin when the converter is regulating at the desired output
voltage. The output voltage can be programmed from 600mV
- FB

to 3.3V. EA

Programming the output voltage is written as: +

R BOTTOM
V REF = V OUT  --------------------------------------------------
- (EQ. 5)
R TOP + R BOTTOM REF

Where: FSET

- VOUT is the desired output voltage of the converter

- VREF is the voltage that the converter regulates to RFSET CFSET
between the FB pin and the GND pin
- RTOP is the voltage-programming resistor that connects R3 MODULATOR
from the FB pin to the VO pin. In addition to setting the
output voltage, this resistor is part of the loop
VO
compensation network
VOUT
- RBOTTOM is the voltage-programming resistor that
connects from the FB pin to the GND pin
VIN
Beginning with RTOP between 1k to 5kcalculating VIN
RBOTTOM is written as:
V REF  R
TOP
R BOTTOM = ------------------------------------- (EQ. 6) QHIGH_SIDE
V OUT – V REF
UG
Programming the PWM Switching Frequency PHASE
The ISL6269 does not use a clock signal to produce PWM. LOUT DCR
The PWM switching frequency fSW is programmed by the
resistor RFSET that is connected from the FSET pin to the GATE DRIVERS
QLOW_SIDE COUT
GND pin. The approximate PWM switching frequency is written
LG
as:
CESR
1 (EQ. 7)
f SW = --------------------------- GND
K  R FSET

Estimating the value of RFSET is written as: ISL6269

1 (EQ. 8)
R FSET = ------------------
K  f SW

Where:
FIGURE 6. COMPENSATION REFERENCE CIRCUIT
- fSW is the PWM switching frequency
- RFSET is the fSW programming resistor Your local Intersil representative can provide a PC-based tool
that can be used to calculate compensation network
- K = 75 x 10-12
component values and help simulate the loop frequency
It is recommended that whenever the control loop response. The compensation network consists of the internal
compensation network is modified, fSW should be checked for error amplifier of the ISL6269 and the external components R1,
the correct frequency and if necessary, adjust RFSET. R2, C1, and C2 as well as the frequency setting components
Compensation Design RFSET, and CFSET, are identified in the schematic Figure 6.
The LC output filter has a double pole at its resonant frequency
that causes the phase to abruptly roll downward. The R3
General Application Design Guide
modulator used in the ISL6269 makes the LC output filter This design guide is intended to provide a high-level explanation
resemble a first order system in which the closed loop stability can of the steps necessary to create a single-phase power
be achieved with a Type II compensation network. converter. It is assumed that the reader is familiar with many of
the basic skills and techniques referenced below. In addition to

FN9177 Rev 3.00 Page 10 of 14

June 25, 2009
ISL6269

this guide, Intersil provides complete reference designs that Selection of the Input Capacitor
include schematics, bills of materials, and example board The important parameters for the bulk input capacitance are
layouts. the voltage rating and the RMS current rating. For reliable
Selecting the LC Output Filter operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and capable of
The duty cycle of an ideal buck converter is a function of the
supplying the RMS current required by the switching circuit.
input and the output voltage. This relationship is written as:
Their voltage rating should be at least 1.25 times greater than
V OUT
D = ---------------- (EQ. 9) the maximum input voltage, while a voltage rating of 1.5 times
V IN
is a preferred rating. Figure 7 is a graph of the input RMS ripple
The output inductor peak-to-peak ripple current is written as: current, normalized relative to output load current, as a function
V OUT   1 – D  of duty cycle that is adjusted for converter efficiency. The ripple
I PP = -------------------------------------- (EQ. 10) current calculation is written as:
f SW  L OUT
2 2 2 D
A typical step-down DC/DC converter will have an IPP of 20%  I MAX   D – D   +  x  I MAX  ------ 
 12 
I IN_RMS = ----------------------------------------------------------------------------------------------------- (EQ. 14)
to 40% of the maximum DC output load current. The value of I MAX
IPP is selected based upon several criteria such as MOSFET
switching loss, inductor core loss, and the resistive loss of the Where:
inductor winding. The DC copper loss of the inductor can be - IMAX is the maximum continuous ILOAD of the converter
estimated by: - x is a multiplier (0 to 1) corresponding to the inductor
P COPPER = I LOAD
2
 DCR (EQ. 11) peak-to-peak ripple amplitude expressed as a percentage
of IMAX (0% to 100%)
Where ILOAD is the converter output DC current. - D is the duty cycle that is adjusted to take into account the
The copper loss can be significant so attention has to be given efficiency of the converter which is written as:
to the DCR selection. Another factor to consider when V OUT
D = --------------------------
choosing the inductor is its saturation characteristics at V IN  EFF (EQ. 15)
elevated temperature. A saturated inductor could cause
In addition to the bulk capacitance, some low ESL ceramic
destruction of circuit components, as well as nuisance OCP
capacitance is recommended to decouple between the drain of
faults.
the high-side MOSFET and the source of the low-side
A DC/DC buck regulator must have output capacitance COUT MOSFET.
into which ripple current IPP can flow. Current IPP develops a
NORMALIZED INPUT RMS RIPPLE CURRENT

0.60
corresponding ripple voltage VPP across COUT, which is the
0.55
sum of the voltage drop across the capacitor ESR and of the
0.50
voltage change stemming from charge moved in and out of the
0.45
capacitor. These two voltages are written as:
0.40
V ESR = I PP  E SR (EQ. 12) 0.35
0.30
and 0.25 x=1
x = 0.75
I PP 0.20 x = 0.50
V C = ------------------------------------- (EQ. 13) x = 0.25
8  C OUT  f 0.15 x=0
SW
0.10
If the output of the converter has to support a load with high 0.05
pulsating current, several capacitors will need to be paralleled to 0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
reduce the total ESR until the required VPP is achieved. The
inductance of the capacitor can cause a brief voltage dip if the DUTY CYCLE

load transient has an extremely high slew rate. Low inductance FIGURE 7. NORMALIZED RMS INPUT CURRENT FOR x = 0.8
capacitors constructed with reverse package geometry are
available. A capacitor dissipates heat as a function of RMS
current and frequency. Be sure that IPP is shared by a sufficient
quantity of paralleled capacitors so that they operate below the
maximum rated RMS current at fSW. Take into account that the
rated value of a capacitor can fade as much as 50% as the DC
voltage across it increases.

FN9177 Rev 3.00 Page 11 of 14

June 25, 2009
ISL6269

MOSFET Selection and Considerations As an example, suppose the high-side MOSFET has a total
Typically, a MOSFET cannot tolerate even brief excursions gate charge Qg, of 25nC at VGS = 5V, and a VBOOT of
beyond their maximum drain to source voltage rating. The 200mV. The calculated bootstrap capacitance is 0.125µF; for a
MOSFETs used in the power stage of the converter should comfortable margin select a capacitor that is double the
have a maximum VDS rating that exceeds the sum of the upper calculated capacitance, in this example 0.22µF will suffice. Use
voltage tolerance of the input power source and the voltage an X7R or X5R ceramic capacitor.
spike that occurs when the MOSFET switches off. Layout Considerations
There are several power MOSFETs readily available that are As a general rule, power should be on the bottom layer of the
optimized for DC/DC converter applications. The preferred PCB and weak analog or logic signals are on the top layer of
high-side MOSFET emphasizes low switch charge so that the the PCB. The ground-plane layer should be adjacent to the top
device spends the least amount of time dissipating power in layer to provide shielding. The ground plane layer should have
the linear region. Unlike the low-side MOSFET which has the an island located under the IC, the compensation components,
drain-source voltage clamped by its body diode during turn off, and the FSET components. The island should be connected to
the high-side MOSFET turns off with VIN - VOUT - VLacross it. the rest of the ground plane layer at one point.
The preferred low-side MOSFET emphasizes low rDS(ON)
when fully saturated to minimize conduction loss. VIAS TO GND
GROUND OUTPUT
For the low-side MOSFET, (LS), the power loss can be PLANE CAPACITORS
assumed to be conductive only and is written as: SCHOTTKY
VOUT DIODE
2
P CON_LS  I LOAD  r DS  ON _LS   1 – D  (EQ. 16) PHASE
INDUCTOR NODE LOW-SIDE
MOSFETS
HIGH-SIDE
For the high-side MOSFET, (HS), its conduction loss is written MOSFETS INPUT
as: VIN CAPACITORS
2
P CON_HS = I LOAD  r DS  ON _HS  D (EQ. 17)
FIGURE 8. TYPICAL POWER COMPONENT PLACEMENT
For the high-side MOSFET, its switching loss is written as:
Signal Ground and Power Ground
V IN  I VALLEY  t ON  f V IN  I PEAK  t OFF  f The bottom of the ISL6269 QFN package is the signal ground
SW SW
P SW_HS = ----------------------------------------------------------------- + ------------------------------------------------------------- (GND) terminal for analog and logic signals of the IC. Connect
2 2
(EQ. 18) the GND pad of the ISL6269 to the island of ground plane
under the top layer using several vias, for a robust thermal and
Where: electrical conduction path. Connect the input capacitors, the
- IVALLEY is the difference of the DC component of the output capacitors, and the source of the lower MOSFETs to the
inductor current minus 1/2 of the inductor ripple current power ground plane.
- IPEAK is the sum of the DC component of the inductor
PGND (PIN 10)
current plus 1/2 of the inductor ripple current
- tON is the time required to drive the device into saturation This is the return path for the pull-down of the LG low-side
MOSFET gate driver. Ideally, PGND should be connected to
- tOFF is the time required to drive the device into cut-off
the source of the low-side MOSFET with a low-resistance, low-
Selecting The Bootstrap Capacitor inductance path.
The selection of the bootstrap capacitor is written as:
VIN (PIN 1)
Qg
C BOOT = ------------------------ (EQ. 19) The VIN pin should be connected close to the drain of the high-
V BOOT side MOSFET, using a low resistance and low inductance path.

Where: VCC (PIN 2)

- Qg is the total gate charge required to turn on the For best performance, place the decoupling capacitor very
high-side MOSFET close to the VCC and GND pins.
- VBOOT, is the maximum allowed voltage decay across
PVCC (PIN 12)
the boot capacitor each time the high-side MOSFET is
switched on For best performance, place the decoupling capacitor very
close to the PVCC and PGND pins, preferably on the same
side of the PCB as the ISL6269 IC.

FN9177 Rev 3.00 Page 12 of 14

June 25, 2009
ISL6269

FCCM (PIN 3), EN (PIN 4), AND PGOOD (PIN 16) LG (PIN 11)
These are logic inputs that are referenced to the GND pin. The signal going through this trace is both high dv/dt and
Treat as a typical logic signal. high di/dt, with high peak charging and discharging current.
Route this trace in parallel with the trace from the PGND pin.
COMP (PIN 5), FB (PIN 6), AND VO (PIN 8)
These two traces should be short, wide, and away from
For best results, use an isolated sense line from the output other traces. There should be no other weak signal traces in
load to the VO pin. The input impedance of the FB pin is proximity with these traces on any layer.
high, so place the voltage programming and loop
compensation components close to the VO, FB, and GND BOOT (PIN 13), UG (PIN 14), AND PHASE (PIN 15)
pins keeping the high impedance trace short. The signals going through these traces are both high dv/dt
and high di/dt, with high peak charging and discharging
FSET (PIN 7)
current. Route the UG and PHASE pins in parallel with short
This pin requires a quiet environment. The resistor RFSET and wide traces. There should be no other weak signal
and capacitor CFSET should be placed directly adjacent to traces in proximity with these traces on any layer.
this pin. Keep fast moving nodes away from this pin.
Copper Size for the Phase Node
ISEN (PIN 9)
The parasitic capacitance and parasitic inductance of the
Route the connection to the ISEN pin away from the traces phase node should be kept very low to minimize ringing. It is
and components connected to the FB pin, COMP pin, and best to limit the size of the PHASE node copper in strict
FSET pin. accordance with the current and thermal management of the
application. An MLCC should be connected directly across
the drain of the upper MOSFET and the source of the lower
MOSFET to suppress the turn-off voltage spike.

Package Outline Drawing

L16.4x4
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

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For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com

FN9177 Rev 3.00 Page 13 of 14

June 25, 2009
 ISL6269

Rev 6, 02/08

4X 1.95
4.00 A 12X 0.65
B 6
13 16 PIN #1 INDEX AREA

6
PIN 1
INDEX AREA 1
12

4.00
2 . 10 ± 0 . 15

9
4

(4X) 0.15
8 5
TOP VIEW +0.15 0.10 M C A B
16X 0 . 60
-0.10 4 0.28 +0.07 / -0.05
BOTTOM VIEW

SEE DETAIL "X"

0.10 C C
1.00 MAX
BASE PLANE

( 3 . 6 TYP ) SEATING PLANE

0.08 C
SIDE VIEW
( 2 . 10 ) ( 12X 0 . 65 )

( 16X 0 . 28 ) C 0 . 2 REF 5

( 16 X 0 . 8 )
0 . 00 MIN.
0 . 05 MAX.

TYPICAL RECOMMENDED LAND PATTERN DETAIL "X"

NOTES:

1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05

4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.

5. Tiebar shown (if present) is a non-functional feature.

6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.

FN9177 Rev 3.00 Page 14 of 14

June 25, 2009