Alif E7 Datasheet v2.5-1
Alif E7 Datasheet v2.5-1
Alif E7 Datasheet v2.5-1
ENSEMBLE™ FAMILY
E7 SERIES
EMBEDDED FUSION PROCESSORS
Datasheet
Alif Semiconductor www.alifsemi.com
ADTS0005 v2.5—October 2023
E7 Series
EXTREME LOW POWER FUSION PROCESSOR: DUAL CORTEX-A32, DUAL CORTEX-M55 CPU, DUAL
ETHOS-U55 NPU, DEEP SECURITY, 2D GPU, MIPI-DSI/CSI, UP TO 13.5MB SRAM, 5.5MB MRAM
Features
High-Performance Quad-Core Fusion Processor l As Low as 27 µA/MHz Dynamic Consumption for
l Dual Arm® Cortex®-A32 Cores with Arm Neon™ High-Efficiency Cortex-M55
SIMD Extension up to 800 MHz, 512KB Shared l Multiple Power Domains, Dynamic Power
L2, 32KB L1 Instruction and Data Caches, MMU, Gating, Voltage and Clock Scaling, DC-DC
Armv8-A ISA with Arm TrustZone® Converter
l High-Performance Arm® Cortex®-M55 Core, up
On-Chip Application Memory
to 400 MHz, with Helium™ Vector Processing l High Endurance MRAM Non-Volatile Memory
Extension, Double-Precision FPU, 1.25MB SRAM l Up to 5.5MB
0-wait State Tightly- Coupled Memory, 32KB l SRAM
with Arm TrustZone®, and 4.37 CoreMark®/MHz l Optional Data Retention of 256KB or 512KB
Data Caches, Armv8.1-M ISA with Arm 100 MB/s SDR, 200 MB/s DDR, with Inline AES
TrustZone®, and 4.37 CoreMark®/MHz Decryption, XIP Mode Support, HyperBus
Performance Benchmark Protocol Support, Enabling External Memory
l High-Performance 400-MHz 64-bit AXI Bus Expansion
Fabric Common Across All CPUs l 1× SD® v4.2, eMMC™ v5.1 Channel with DMA
Inference Time (Source: Arm. MobileNet V2 1.0 l Crypto Accelerators—AES (up to AES-256), ECC
Model for Object Classification) (up to 384 bits), SHA (up to SHA-256), RSA (up to
l 76× Less Energy Consumed when Using Ethos- RSA-3072), and NIST compliant TRNG
U55 Together with Cortex-M55 (Source: Arm. l Secure Debugging with Certificate
l 1× 2-Lane MIPI CSI-2® l 1.08 V to 1.98 V I/O Supply Range (1.8 V I/O)
l 1× Camera Parallel Interface (CPI), up to 16 bits l 3.0 V to 4.2 V I/O Supply Range (3.3 V Flex I/O)
Audio Interfaces
E7
l 4× I2S Synchronous Stereo Audio Interfaces
Peripherals)
l Up to 8× Selectable 1.8-V to 3.3-V GPIOs (Shared
with Peripherals)
1 Preface
This document contains fundamental technical information for the Alif Semiconductor E7 series devices.
Device information herein includes features description, electrical and mechanical characteristics with
specifications, and ordering information.
There are references to third-party technical documents as noted within this document.
For more information on processors, peripheral functions, and programming settings, refer to the
corresponding device series-specific Hardware Reference Manual.
For managing software configurations of device resources, power, pins, clocks, DMA requests, interrupts, and
various other additional settings, refer to the Alif Conductor tool.
2 Device Overview
E7 Series
Applica�on Processor Subsystem High-Speed Camera Secure Debug High-Performance High-Efficiency
Communica�on and Enclave Real-Time Processor Subsystem Real-Time Processor Subsystem
GIC Memory Expansion MIPI CSI-2
LPSPI LPI2C Camera Ba�ery Backed
MHU CPI
Debug LPCPI
LPUART
WDT Authen�ca�on NVIC DMA
Display NVIC DMA Audio LPGPIO
Cortex-A32 Cortex-A32 MIPI DSI MHU WDT EVTRTR LPI2S LPPDM
System and MHU WDT LPTIMER
+ Neon + Neon Ethernet
DPI Firewall Control Cortex-M55 AI/ML Cortex-M55 EVTRTR
+ Crypto Extension + Crypto Extension LPCMP
+ Helium + Helium
(A32-0) (A32-1) JTAG AI/ML
SDMMC and CDC Security (M55-HP) (M55-HE) LPRTC
Ethos-U55 Ethos-U55
L1 Instr L1 Data L1 Instr L1 Data SDIO Unit SWD TCM LFXO LFRC
Graphics (NPU-HP) TCM (NPU-HE)
Cache Cache Cache Cache (SRAM2, SRAM3) (SRAM4, SRAM5)
NPU POR BOD
Shared D/AVE 2D CPU and CoreSight Instr Data NPU Instr Data
USB Memory Backup SRAM
L2 Cache (GPU2D) SERAM Mul�core Cache Cache Memory Cache Cache
intro-001
Color Key: High-Performance Region High-Efficiency Region Always-On Region
Feature Definition
SPI 4
Serial Peripheral Interface
LPSPI 1
UART 8
Universal Asynchronous Receiver/Transmitter
LPUART 1
Universal Serial Bus USB USB 2.0 HS/FS Host/Device
Secure Digital Input Output SDIO SDIO v4.1 (1)
External Memory Interfaces
Octal SPI OSPI 2
Secure Digital Multimedia Card SDMMC SD v4.2, eMMC v5.1 (1)
Camera Subsystem
CPI Up to 16-bit
Camera Parallel Interface
LPCPI Up to 8-bit
MIPI Camera Serial Interface 2 CSI 2-Lane
Display Subsystem
Graphics LCD Controller CDC 1
Display Parallel Interface DPI Up to 24-bit RGB
MIPI Display Serial Interface DSI 2-Lane
Analog Peripherals
3 × 12-bit
ADC12
(Up to 18 inputs)
Analog-to-Digital Converter
1 × 24-bit
ADC24
(Up to 4 differential inputs)
Digital-to-Analog Converter DAC12 2 × 12-bit
4
High-Speed Comparator CMP
(16 inputs)
1
Low Power Comparator LPCMP
(4 inputs)
Temperature Sensor TSENS Yes
1. SDIO, SD, and eMMC are functions of memory card controller. There is only one memory card controller in the device.
2. For devices supporting optional features, refer to Section 7 Ordering Information.
3 Functional Overview
l Trace infrastructure
achieves high compute performance across scalar and vector operations, operating up to 400 MHz.
The device includes a single M55-HP processor that resides in the High-Performance Real-Time Subsystem
(RTSS-HP). The RTSS-HP also includes various memories and peripherals.
The M55-HP processor supports the following main features:
n CPU revision: r1p0
n CPU core logic that includes:
l In-order, four-stage integer pipeline with early completion of common arithmetic instructions
l Instruction Fetch Unit (IFU) with 32-bit instruction fetch data width
n Extension Processing Unit (EPU) that works closely with the CPU core to support:
l Scalar floating-point (VFPv5) operations: half-, single-, and double-precision
o Integer
o 128-bit SIMD floating-point: half- and single-precision
n Double-Precision FPU
n Support for other Extensions such as:
l Armv8.1-M Main Extension (16-bit and 32-bit Thumb® instruction set)
l DSP Extension
l Memory system:
n Interrupt control:
l Nested Vectored Interrupt Controller (NVIC) for low-latency interrupt processing:
o Supports 480 external interrupts, with 256 priority levels per interrupt
(PMU)
l Trace infrastructure
l Instruction Fetch Unit (IFU) with 32-bit instruction fetch data width
n Extension Processing Unit (EPU) that works closely with the CPU core to support:
l Scalar floating-point (VFPv5) operations: half-, single-, and double-precision
o Integer
o 128-bit SIMD floating-point: half- and single-precision
n Double-Precision FPU
n Support for other Extensions such as:
l Armv8.1-M Main Extension (16-bit and 32-bit Thumb instruction set)
l DSP Extension
l Memory system:
o32KB L1 Instruction Cache (IRAM)
o 32KB L1 Data Cache (DRAM)
o 256KB Instruction TCM (ITCM); access to ITCM is over a single interface
o 256KB Data TCM (DTCM); access to DTCM is over four interfaces
o Master AXI (M-AXI) interface for high latency memory or peripheral access
n Interrupt control:
l Nested Vectored Interrupt Controller (NVIC) for low-latency interrupt processing:
o Supports 480 external interrupts, with 256 priority levels per interrupt
(PMU)
l Trace infrastructure
l Tanh
l Sigmoid
l None or bypass
n Element-wise operations:
l Element-wise ADD and SUB
l Element-wise Multiplication (MUL)
l Element-wise ABS
l Tanh
l Sigmoid
l None or bypass
n Element-wise operations:
l Element-wise ADD and SUB
l Element-wise ABS
l Convex polygon
l Line
o Supported caps:
o Butt
o Round
o Square
o Supported line joins:
o Bevel
o Miter
o Round
o Supporting different start and end widths
l Quad
l Triangle
l Triangle fan
l Triangle list
l Triangle stripe
l Wedge-filled or empty
l Blend modes
l Color
l Edge blur
l Pattern
l Texture
o ARGB8888, RGB565, ARGB4444, ARGB1555, ALPHA8, AI44, RGBA8888, RGBA4444, RGBA5551, I8,
bootloader. It is loaded to the SE SRAM (SERAM) and the flow of execution is transferred to it. This
mechanism enables the secure update of the Second Stage bootloader on the field. The boot process
continues with processing of the application-specific device configuration. The SE applies configuration
settings that partition the system resources (memory and peripherals) between the different application
cores. Next, the SE bootloader performs a signature verification of the installed application binaries. If
needed, it copies the specified binaries to their designated SRAM regions. Finally, a designated core is
released from Reset to run its application. This completes the secure boot procedure. The remaining cores
can be booted by the SE in response to a service request.
The SE is also involved in the process of waking up from STOP mode. When a wakeup event is triggered, the
SE CPU boots first. It checks if the SERAM is retained and continues the execution flow there. The SERAM
code maps the wakeup event to an application core and promptly boots it. If the SERAM is not retained, then
the SE validates the wakeup source and boots the RTSS-HE core. The retention of SERAM in the Secure
Enclave or the SRAM (M55-HE TCM) in the RTSS-HE offers trade-off options between the leakage current and
the wakeup time of the device.
The SE provides traditional security functions such as:
n Secure boot
n Secure device configuration
n HW Root-of-Trust (RoT)
n Key management
n Signature validation
n Crypto operations
n Life cycle management
The Supervisor is responsible to:
n Manage the OEM provisioning process and the Life Cycle State (LCS)
n Apply the system configuration settings to the security firewalls and security HW in the system
n Securely boot the Application core (A32) / Real-time cores (M55-HP and M55-HE) as defined by the
user's configuration file
3.6 Interconnect
The system interconnect provides the means of connecting bus masters (CPU cores, DMA controllers) to
memory modules and peripherals. It is based on the Arm AMBA bus architecture utilizing a mix of AXI, AHB
Debug SRAM0
Interconnect-001
LPGPIO, LPTIMER, LPUART, LPI2S, PINMUX, Clock Power Firewall
MHU IRQRTR
LPCMP LPRTC LPSPI, LPI2C LPPDM Reset Control Control Control
NOTE
For managing software configurations of device resources, power, pins, clocks, DMA requests,
interrupts, and various other additional settings, refer to the Alif Conductor tool.
1. If VDD_BATT is connected to a battery, the PD-0 domain and the AON Region are Always-On.
2. The PD-2 domain is first to power up.
3. The next order of powering up the domains depends on whether the device executes an initial boot
(cold), or a wake up (warm).
PDs in each of the three device regions are defined as follows:
n AON Region
l PD-0, AON power and control
n HE Region
l PD-2, High Efficiency Region power and control
n HP Region
l PD-5, Secure Enclave Subsystem (SESS)
High-Performance Region
PD-9
APSS
USB PHY Analog MIPI PHY
Enable
PPU-9
PD-5 PD-6 PD-7 PD-8
SESS SYST RTSS-HP DBSS
High-Efficiency Region
Enable Enable
PSC-STBY
PD-2 (HE Region Power and Control)
PSM
PWR-001
PSC-STOP PD-1 (SRAM6 and SRAM7 Reten�on Control)
PD-0 (AON Region Power and Control)
Reten�on
Enable
Backup
PWR-001
SRAM
For more details about PDs power-up and transitions, see the device series-specific Hardware Reference
Manual.
Table 3-1 illustrates which specific resources are available within each of the power domains, and how the
power domains are related to the three operational regions.
VREG_MIPI_1V8
For more information about power supply voltage ranges and general operating conditions, see Section 5.2.1
General Operating Conditions.
Table 3-2 presents power supply signals and provides descriptions to their functions.
For more information about power supply voltage ranges and general operating conditions, see Section 5.2.1
General Operating Conditions.
For more details about specific power consumption and wake-up times per power mode, see Section 5.2.2
Device Power Modes.
Device
BOR
Threshold
Debug +3.3 V
Main SoC
VDD_BATT
VBAT Domain VDD_MAIN
(PD-0)
3.0 V
RST-001
POR_N NSRST
Table 3-6 lists the main reset sources along with their types and functions.
Table 3-6 Device Main Reset Sources
Reset Source Hardware/Software Description
System cold Reset pin.
Asserting this pin is equivalent to turning the device power
POR_N pin
HW off. After deasserting the signal, the device completes a full
(active-low)
power on cycle, which is equivalent to a cold start.
No logic or memory retains its state.
System warm Reset pin.
NSRST pin Typically, an external debugger asserts this reset pin.
HW
(active-low) It resets all logic in the device except for PD-0 peripherals,
debug logic, and the JTAG interface.
Fundamental POR.
VBAT_POR keeps the entire device in reset during a power-
VBAT_POR monitor HW
on ramp-up until VDD_BATT reaches the operational
threshold.
Brown-out reset.
BOR monitor HW and SW BOR monitor asserts a reset to the main SoC when VDD_
MAIN falls below a programmable threshold.
Table 3-7 presents Reset signals and provides descriptions to their functions.
Table 3-7 Reset Signal Descriptions
Signal Name Pin Name Type Description
NSRST NSRST I JTAG reset (system reset) active low
POR_N POR_N I Power-On-Reset (cold reset) active low
0 Hz
SYST_ACLK
SYSPLL_CLK (Bulk SRAM, NIC-400 AXI bus, peripherals)
MUX 1/1 MUX
400 MHz
SYST_HCLK
HFXO_OUT (AHB buses, peripherals)
1/2
SYST_PCLK
(APB buses, peripherals)
1/4
HFRC/X
50 MHz
ETH_REFCLK
ETH_CLK
50 MHz MUX
1/16
100M_CLK
38.4 MHz
19.2 MHz
9.6 MHz 100 MHz
1/8
4.8 MHz
PLL_CLK1 200 MHz
2.4 MHz 1/4
MUX RTSS_HP_CLK
1.2 MHz PLL_CLK2 300 MHz (M55-HP, U55-HP)
600 kHz PLL 1/2 MUX
38.4 MHz
160M_CLK
HFRC/X
HFRC/X/2
1/2
HFXO/Z x2 MUX
HFXO/Z
20 MHz USB_CLK
1/24
128K_CLK 10M_CLK
1/48
76M8_CLK
32.7 kHz
LFRC S32K_CLK
LFXO_P/EXT CLK MUX
32.768 kHz
LFXO
LFXO_N
NOTE
For managing software configurations of device resources, power, pins, clocks, DMA requests,
interrupts, and various other additional settings, refer to the Alif Conductor tool.
Table 3-8 presents clock interface signals and provides descriptions to their functions.
Table 3-8 Clock Signal Descriptions
Signal Name Pin Name Type Description
HFXO_OUT_A P3_6 O High-frequency clock output to external devices
HFXO_OUT_B P9_3 O High-frequency clock output to external devices
HFXO_P HFXO_P I High-frequency oscillator input
HFXO_N HFXO_N O High-frequency oscillator output
LFXO_P LFXO_P I Low-frequency oscillator input
LFXO_N LFXO_N O Low-frequency oscillator output
GPIO0_0
GPIO0 0
OSPI0_D0
OSPI0 1
UART0_RX
UART0 2
OUT
MUX/DEMUX
I3C_SDA
I3C 3
Digital
IN P0_0
UT0_0 I/O Buffer
UTIMER 4 OEN
LPCAM_HSYNC
LPCAM 5
CAM_HSYNC
CAM 6
ADC120_IN0 ANA_S0
ADC120 7
Configura�on
ADC24_IN0_P
ADC24
Selec�on
CMP0_IN0
CMP0
pinmux-002
Analog
P0_0 Register
Figure 3-7 shows the LPGPIO pin sharing. Because Port 15 is located in the always-on domain (VBAT
powered), here pin sharing is achieved differently. That is, there is no multiplexing as such. In this example,
LPTIMER0 gets access to P15_0 via the LPGPIO module. LPGPIO controls the pin direction depending on the
value written to its Data Direction register.
Figure 3-7 LPGPIO/LPTIMER Pin Sharing (P15_0 Example)
VDD_IO_FLEX
OUT
LPTMR0_OUT
IN Digital
LPTIMER0 LPTMR0_CLK LPGPIO P15_0
OEN I/O Buffer
Configura�on
pinmux-003
LPGPIO_CTRL_0 Register
Driver Config
Receiver Config
IN
(to peripheral)
Receiver
Weak
Pullup
Pull Config
Bus Keeper
Weak
Pulldown
PINMUX-001
The I/O buffer has the following main features:
n Configurable direction (input, output or both)
n Selectable driver-disabled state:
l No pull (Hi-Z, floating)
l Weak pull-up
l Weak pull-down
NOTE
For more information on configuration registers, refer to the corresponding device series-specific
Hardware Reference Manual.
For managing software configurations of device resources, power, pins, clocks, DMA requests,
interrupts, and various other additional settings, refer to the Alif Conductor tool.
3.12 Memories
l M55-HE TCM: SRAM4 (M55-HE ITCM) and SRAM5 (M55-HE DTCM), with optional retention
The embedded bulk SRAM is a general-purpose memory to be shared among all applications. It is partitioned
into two blocks, each having 64-bit wide data bus and providing read/write operation at 400 MHz. The bulk
memory blocks can be accessed in parallel over the main 64-bit AXI bus running at 400 MHz.
The TCM is an SRAM block providing high-bandwidth and low latency access. The TCM is primarily used by
the M55 core it is attached to. Alternatively, it can be shared with other bus masters in the device.
The cache memory is a high-performance SRAM accelerating the CPU access to frequently used instructions
and data. A32 Level 1 cache memory is dedicated to an individual A32 core. The Level 2 cache is shared
between the two A32 cores. The M55 processors have Level 1 cache memories dedicated to each M55 core.
The data retention of SRAM is used for context saving during low power modes.
The device includes the following quantities of SRAM with their performance characteristics:
n User SRAM available to all bus masters:
l Up to 13.5MB:
SRAM9_B
l 400 MHz parallel read/write access
n Backup SRAM:
l 4KB in power domain PD-0
l Optional data retention by VDD_BATT (see Section 3.7.2 Voltage Supplies for details)
NOTE
User SRAM size and availability is device part number dependent. For more information on SRAM
blocks enabled for each part number and their sizes, see Section 7 Ordering Information.
n M55-HP:
l 256KB of ITCM and 4 × 256KB of DTCM (total of 1.25MB)
l 1 × 32-bit ITCM and 4 × 32-bit DTCM memory buses
l Concurrent share of TCM with the other processing entities via AHB slave port
n M55-HE:
l 256KB of ITCM and 4 × 64KB of DTCM (total of 512KB)
l Concurrent share of TCM with the other processing entities via AHB slave port
l Group 1 (non-secure)
n Interrupt virtualization
n AMBA 4 AXI configuration interface
The function of the EVTRTR is similar to the shared Interrupt Router (IRQRTR), which targets an interrupt
controller and ultimately a CPU core. Unlike the IRQRTR, the EVTRTR is connecting the event signal to a
peripheral that executes an action without involving any CPU core.
Modules generating such event signals include: GPIO, UTIMER, I2C, SPI, UART, and others. The EVTRTR passes
the signals through edge-detection circuits and gating logic before routing them to specific targets.
The device includes three Event Routers, each dedicated to a specific target:
n EVTRTR0, dedicated to DMA0 controller and UTIMER
n EVTRTR1, dedicated to DMA1 controller
n EVTRTR2, dedicated to DMA2 controller
Each EVTRTR provides the following main features:
n Software generated events
n Zero wait state for event routing between peripherals in the same clock domain
n Automatic synchronization of events and triggers between peripherals in different clock domains
n DMA channel enable, handshake status and type selection
Figure 3-9 provides a high-level overview of the EVTRTR implementation in the device.
Figure 3-9 EVTRTR Overview
Device
EVTRTR0 DMA0 Controller
(DMA0_MUX)
MUX Config:
DMA_CTRLn[SEL]
(n = 0 to 31)
UT_EVENT[0-15] UTIMER
16 UTIMER Events
EVTRTR-001a
Device
EVTRTR1
EVTRTR DMA1
DMA0 Controller
(DMA0_MUX)
4-to-1 CH1
MUX CH1
...
4-to-1CH31
MUX CH31
EVTRTR2
EVTRTR DMA2
DMA0 Controller
(DMA0_MUX)
4-to-1 CH1
MUX CH1
...
4-to-1CH31
MUX CH31
EVTRTR-001b
EVTRTR0 is also referred to as DMA0_MUX and expands the available 32 inputs of DMA0 by exposing the
DMA channels to 128 different peripheral events via 32 × 4-to-1 multiplexers. The first 16 multiplexed DMA0
requests are also routed as input triggers to the Universal Timer (UTIMER). This mechanism enables the
implementation of complex state machines involving the use of peripheral or time-based events that trigger
data transfers and/or timer triggers.
EVTRTR1 and EVTRTR2 support 32 input events/output DMA channels each, without implementing events
multiplexing.
DMA Requests
DMA Requests
DMA Requests
M55-HP M55-HE
TCM TCM
AXI
OSPI Peripherals
SRAM NVM Memory (UART, I2C, SPI, etc.)
DMA_ARCH-001
The high-speed interface peripherals (USB, ETH, and SDMMC) have their own, embedded DMA controllers.
They are optimized for the specific needs of these interfaces.
DMA0, DMA1 and DMA2 are general-purpose, programmable, multi-channel, and TrustZone-aware DMA
controllers (DMACs). Each of them has 32 inputs for accepting DMA requests from various device peripherals
and triggers (for example, UART Tx and Rx, ADC conversion done, etc). The Event Routers positioned in front
of the DMA controllers provide support for DMA handshaking between peripherals and DMACs. Additionally,
EVTRTR0 provides 32 × 4-to-1 programmable multiplexers, which expose the 32 DMA0 inputs to 128 possible
DMA requests from peripherals, thus providing an increased flexibility. Each DMA controller supports 8
internal data channels (FIFOs). All channels can perform independently programmed transactions including
different data lengths, source and destination addresses, single or burst transfers.
DMA0 controller can be shared by all of the CPU cores. The security privilege of each channel is run-time
programmable. DMA0 initiates transactions on the main AXI bus with its unique Stream ID. Each of the 32
request interfaces can generate an interrupt request signal. The interrupts are shared over the Interrupt
Router (IRQRTR) with all of the CPU cores.
DMA1 and DMA2 controllers are assigned to the M55-HP and M55-HE CPU cores, respectively. They reside in
their domains and share their AXI-bus Stream IDs (and security policy). The DMA1 and DMA2 request
interfaces can generate individual interrupt requests, attached locally to their respective M55 cores.
l Memory-to-peripheral
l Peripheral-to-memory
l Scatter-gather
Pin
Signal Name Type Description
Name
LPTIMER0_OUT: LPTIMER0 toggle output. Changes state each time the
timer counter reloads. The output is disabled to 0 each time the timer
is disabled.
LPTIMER1
LPTIMER1_CLK: LPTIMR1 input clock from pin.
LPTIMER1_OUT: LPTIMER1 toggle output. Changes state each time the
LPTMR1_CLK_IO P15_1 IO
timer counter reloads. The output is disabled to 0 each time the timer
is disabled.
LPTIMER2
LPTIMER2_CLK: LPTIMR2 input clock from pin.
LPTIMER2_OUT: LPTIMER2 toggle output. Changes state each time the
LPTMR2_CLK_IO P15_2 IO
timer counter reloads. The output is disabled to 0 each time the timer
is disabled.
LPTIMER3
LPTIMER3_CLK: LPTIMR3 input clock from pin.
LPTIMER3_OUT: LPTIMER3 toggle output. Changes state each time the
LPTMR3_CLK_IO P15_3 IO
timer counter reloads. The output is disabled to 0 each time the timer
is disabled.
Table 3-11 presents UTIMER QEC interface signals and provides descriptions to their functions.
Table 3-11 UTIMER QEC Signal Descriptions
Signal Name Pin Name Type Description
QEC0 A/B/C
QEC0_X_A P3_0
QEC0_X_B P8_4 I QEC0 input event on channel A
QEC0_X_C P13_0
QEC0_Y_A P3_1
QEC0_Y_B P8_5 I QEC0 input event on channel B
QEC0_Y_C P13_1
QEC0_Z_A P3_2
QEC0_Z_B P8_6 I QEC0 input for zero signal
QEC0_Z_C P13_2
QEC1 A/B/C
QEC1_X_A P3_3
QEC1_X_B P8_7 I QEC1 input event on channel A
QEC1_X_C P13_3
QEC1_Y_A P3_4
QEC1_Y_B P9_0 I QEC1 input event on channel B
QEC1_Y_C P13_4
QEC1_Z_A P3_5 I QEC1 input for zero signal
Table 3-12 presents UTIMER common interface signals and provides descriptions to their functions.
Table 3-12 UTIMER Common Signal Descriptions
Signal Name Pin Name Type Description
Common A/B/C
FAULT0_A P4_4
FAULT0_B P8_0 I Fault signal 0. Used to trigger automatic shut-off of the output drivers.
FAULT0_C P14_4
FAULT1_A P4_5
FAULT1_B P8_1 I Fault signal 1. Used to trigger automatic shut-off of the output drivers.
FAULT1_C P14_5
FAULT2_A P4_6
FAULT2_B P8_2 I Fault signal 2. Used to trigger automatic shut-off of the output drivers.
FAULT2_C P14_6
FAULT3_A P4_7
FAULT3_B P8_3 I Fault signal 3. Used to trigger automatic shut-off of the output drivers.
FAULT3_C P14_7
detect errant system behavior and recover from an unknown state by causing non-maskable interrupt of the
system if the count period elapses without intervention.
The device includes up to two WDT_RTSS modules:
n WDT_HP: Dedicated to the Arm Cortex-M55 High-Performance (M55-HP) processor
n WDT_HE: Dedicated to the Arm Cortex-M55 High-Efficiency (M55-HE) processor
The WDT_RTSS module supports the following main features:
n 32-bit down-counter
n Counter decrements by one on each positive watchdog clock edge
n Configurable NMI generation upon watch period expiration
l WDT_AP_S provides one NMI routed to the A32 GIC and a second interrupt routed to the Secure
Enclave
n Configurable CPU reset upon watch period expiration
n CAN specifications:
l CAN 2.0B (up to 8 bytes payload, verified by Bosch reference model)
l CAN FD (up to 64 bytes payload, ISO 11898-1:2015 or non-ISO Bosch)
l CAN FD rates are limited by the transceiver and the clock frequency of the CAN controller
l Listen-Only mode
l CRC-16-CCITT
l CRC-32
l CRC-32C
n MAC features:
l 10 and 100 Mbps data transfer rates with RMII interface to communicate with an external fast
Ethernet PHY
l Full-duplex operation:
o IEEE 802.3x flow control automatic transmission of zero-quanta pause frame on flow control input
de-assertion
o Forwarding of received pause frames to the user application
l Half-duplex operation:
l Preamble and Start Frame Delimiter (SFD) deletion in the receive path
l Receive module for checksum off-load for received IPv4 and TCP packets encapsulated by the
l Programmable burst length for starting a burst up to half the size of the MTL Rx and Tx FIFO
l Insertion of receive status vectors into the receive FIFO after the EOF transfer
l Automatic generation of pause frame control or backpressure signal to the MAC based on receive
l Discard frames on late collision, excessive collisions, excessive deferral, and under-run conditions
n DMA features:
l Exchanges data between the MTL block and system memory
l Descriptor architecture to allow large blocks of data transfer with minimum CPU intervention (each
l Individual programmable burst size for transmit and receive DMA engines for optimal system bus
utilization
l Programmable interrupt options for different operational conditions
l Status registers that give status of FSMs in transmit and receive data-paths and FIFO fill levels
Table 3-15 presents Ethernet interface signals and provides descriptions to their functions.
Table 3-15 Ethernet Signal Descriptions
Signal Name Pin Name Type Description
ETH A/B/C
ETH_RXD0_A P5_5
ETH_RXD0_B P11_3 I ETH PHY receive data bit 0
ETH_RXD0_C P1_0
ETH_TXD0_A P6_0
ETH_TXD0_B P10_4 O ETH PHY transmit data bit 0
ETH_TXD0_C P1_3
ETH_RXD1_A P5_6
ETH_RXD1_B P11_4 I ETH PHY receive data bit 1
ETH_RXD1_C P1_1
ETH_TXD1_A P6_1 O ETH PHY transmit data bit 1
n 4× 2-channel PDM microphone inputs for total support of up to 8 PDM channels (mono DMICs) for
LPPDM module
n Audio signal bandwidth of up to 96 kHz
n DMA controller interface for storing audio samples
n 16-bit PCM output per channel
n Selection between 9 modes of PDM clock frequencies from 512 kHz to 4.8 MHz (oversampling). The
mode applies to all channels.
n Microphone sleep mode when at 128 kHz PDM clock
n Independent phase adjustment per channel to allow beam forming
n Independent gain adjustment per channel
n Independent peak detector per channel with programmable thresholds
n Peak detection interrupt per channel producing wake-up event
n Independent programmable DC blocking Infinite Impulse Response (IIR) filter per channel
n Independent programmable Finite Impulse Response (FIR) filter per channel
n FIFO with a capability to store up to 8 PCM samples for each channel for CPU to read
n Programmable FIFO watermark level to generate data available interrupt
n FIFO overrun error interrupt
Table 3-19 presents PDM interface signals and provides descriptions to their functions.
Table 3-19 PDM Signal Descriptions
Signal Name Pin Name Type Description
PDM A/B/C
AUDIO_CLK_A P8_0
AUDIO_CLK_B P9_6 I PDM and I2S clock input
AUDIO_CLK_C P12_0
PDM_C0_A P0_5
PDM_C0_B P3_1 O PDM clock output 0 to DMIC (shared by channels 0 and 1)
PDM_C0_C P6_1
PDM_C1_A P0_7
PDM_C1_B P3_3 O PDM clock output 1 to DMIC (shared by channels 2 and 3)
PDM_C1_C P6_3
PDM_C2_A P6_7
O PDM clock output 2 to DMIC (shared by channels 4 and 5)
PDM_C2_B P11_4
PDM_C3_A P5_2
O PDM clock output 3 to DMIC (shared by channels 6 and 7)
PDM_C3_B P11_5
PDM_D0_A P0_4
PDM_D0_B P3_0 I PDM data input 0 from DMIC (shared by channels 0 and 1)
PDM_D0_C P6_0
PDM_D1_A P0_6
PDM_D1_B P3_2 I PDM data input 1 from DMIC (shared by channels 2 and 3)
PDM_D1_C P6_2
PDM_D2_A P5_0
I PDM data input 2 from DMIC (shared by channels 4 and 5)
PDM_D2_B P5_4
PDM_D3_A P5_1
I PDM data input 3 from DMIC (shared by channels 6 and 7)
PDM_D3_B P5_5
LPPDM A/B
LPPDM_C0_A P2_1 O LPPDM clock output 0 to DMIC (shared by channels 0 and 1)
n DMA requests
n Combined interrupt lines and active high-level interrupts
n Operation modes:
l Serial Master or Slave modes for the high-speed SPI modules
n Programmable data transfer clock bit rate for dynamic control of the serial bit rate
n Programmable data item size (4 to 32 bits) for each data transfer
Table 3-20 presents SPI interface signals and provides descriptions to their functions.
n Descriptor caching and data prefetching used to meet system performance in high-latency systems
n Interrupt moderation
n On-chip PHY via an USB 2.0 Transceiver Macrocell Interface (UTMI+)
Table 3-22 presents USB interface signals and provides descriptions to their functions.
n eXpanded SPI (xSPI) with all the command formats as described in JEDEC xSPI version 1.0
n Two xSPI command modes:
l 1S-1S-1S—one IO signal used during command transfer, command modifier transfer, and data
CAUTION
The following pin multiplexing options are recommended:
- For OSPI0, the OSPI0_D[0-7]_B data bus signals are recommended to be used for 100 MHz
operation. OSPI0_D[0-7]_A and OSPI0_D[0-7]_C data bus signals are recommended to be used for 50
MHz operation.
- For OSPI1, the OSPI1_D[0-7]_C data bus signals are recommended to be used for 100 MHz
operation. OSPI1_D[0-7]_A and OSPI1_D[0-7]_B data bus signals are recommended to be used for 50
MHz operation.
l UHS-I mode
l Speed modes:
o Default-Speed (DS)
o High-Speed (HS)
o SDR12
o SDR25
o SDR50
n SDIO interface:
l 4-bit data bus
n eMMC interface:
l 4-bit/8-bit data bus
l SDMA
l ADMA2
l ADMA3
n Clocking:
l Supports independent clocks for the Host controller, slave interface, and master interface
n Interrupt outputs:
l Combined and separate interrupt outputs
n Data buffering:
l Automatic packing/unpacking of data to fit buffer width
Table 3-24 presents SDMMC interface signals and provides descriptions to their functions.
CAUTION
The following pin multiplexing options are recommended:
For SDMMC, the SD_*_C signals are recommended to be used for 50 MHz operation. SD_*_A, SD_*_
B, and SD_*_D signals are recommended to be used for 25 MHz operation.
n One Low-Power CPI (LPCPI) controller in the RTSS-HE. The LPCPI receives parallel data from an external
camera sensor (up to 8-bit data bus).
Each CPI controller supports the following main features:
n Up to 55 MHz pixel clock
n Programmable polarity for the pixel clock, horizontal and vertical synchronization signals
n Single frame capture (snapshot) mode
n Pixel clock output to external camera sensor
Each CPI controller supports the following specific features depending on the pixel data source and bus
width:
Table 3-25 presents CPI interface signals and provides descriptions to their functions.
CAUTION
- For CAM_PCLK and CAM_XVCLK signals, recommended to be used are CAM_PCLK_B and CAM_
XVCLK_B pin multiplexing options.
Table 3-26 presents LPCPI interface signals and provides descriptions to their functions.
CAUTION
- For LPCAM_PCLK and LPCAM_XVCLK signals, recommended to be used are LPCAM_PCLK_A and
LPCAM_XVCLK_A pin multiplexing options.
n PHY Protocol Interface (PPI) between the CSI-2 host controller and the D-PHY receiver
n Up to two D-PHY RX data lanes
n Up to 2.5 Gbps throughput per lane
n Dynamically configurable multi-lane merging
n Long and short packet decoding
n Virtual channel extension—up to 16 interleaved virtual channels
n Timing accurate signaling of frame and line synchronization packets
n Several frame formats:
l General frame or digital interlaced video with or without accurate sync timing
l YUV422: 8-bit/10-bit
l RGB: RGB888/RGB666/RGB565/RGB555/RGB444
l RAW: RAW6/RAW7/RAW8/RAW10/RAW12/RAW14/RAW16
l 16- or 48-bit output parallel data bus, operating at pixel clock rate and delivering either one color
component at a time or one pixel (or pair of pixels) per pixel clock cycle, respectively
l Vertical and horizontal timing accurate video synchronization signals
NOTE
The CSI D-PHY Rx module shares the MIPI_REXT signal connection to a reference resistor (200 Ω, ±1%)
with DSI D-PHY Tx module. For more details, see Table 3-29 MIPI DSI Signal Descriptions.
n Windowing: blending a programmable rectangular area of one layer into the other
n Gamma correction
n Dithering (2 bits per color component): providing softer color transitions for displays with less color
depth
n Multiple input pixel formats selectable per layer:
l ARGB8888, RGBA8888, RGB888, RGB565, ARGB1555, ARGB4444
l MIPI Alliance Specification for Stereoscopic Display Formats (SDF) v1.0—22 November 2011
n PPI between the DSI host controller and the D-PHY transmitter
n Up to two D-PHY TX data lanes
n Up to 2.5 Gbps throughput per lane
n Bidirectional communication and escape mode support through data lane 0
n End of Transmission Packet (EoTp)
n ECC and checksum capabilities
n Fault recovery schemes
o 16-bit RGB
o 18-bit RGB
o 24-bit RGB
l The maximum resolution and frame rate are limited by the pixel clock and the available DSI physical
link bandwidth (defined by the number of lanes and the maximum speed per lane)
n Slave interface used for the transmission of generic commands
n Independently programmable virtual channel ID for the DPI and slave interfaces
n DPI payload FIFO with 1024 × 32-bit slots depth
n Generic command FIFO with 16 × 32-bit slots depth
n Generic payload FIFO with 128 × 32-bit slots depth
n Generic read FIFO with 32 × 32-bit slots depth
n Video mode pattern generator with the following capabilities:
l Vertical and horizontal color bar generation without DPI stimuli
l Conversion results can be stored into sample registers and to SRAM via DMA
l Threshold and window detection options. A comparator logic can generate interrupts when an input
n The ADC12, ADC24, as well as other analog peripherals, are powered from a dedicated internal 1.8-V
LDO
For information on ADC interface signals and their descriptions, see Section 3.21.6 Analog Signals.
For information on DAC interface signals and their descriptions, see Section 3.21.6 Analog Signals.
CMP[0-3]_IN3 3
CMP[0-3]_OUT
VREF_IN0 0
VREF_IN1 1
Internal AMUX
2
Vref
MUX
DAC6 3 3 2 1 0
QEC0_X
QECx
UT0_T0
UTx
CMP-004
For information on CMP interface signals and their descriptions, see Section 3.21.6 Analog Signals.
Table 3-30 presents the CMP digital outputs.
Table 3-30 CMP Signal Descriptions
Signal Name Pin Name Type Description
CMP Outputs A/B
CMP0_OUT_A P7_3
O CMP0 comparison result output
CMP0_OUT_B P14_7
n Programmable hysteresis
n Power supply from VDD_IO_1V8 pin
n Response time: < 10 µs
For information on LPCMP interface signals and their descriptions, see Section 3.21.6 Analog Signals.
Function by Module
Signal Name
ADC12 ADC24 DAC CMP LPCMP
ANA_S9 ADC121_IN3 CMP3_IN1
ANA_S10 ADC121_IN4 CMP2_IN3
ANA_S11 ADC121_IN5 CMP3_IN3
ANA_S12 ADC122_IN0 CMP0_IN2
ANA_S13 ADC122_IN1 CMP1_IN2
ANA_S14 ADC122_IN2 CMP2_IN2
ANA_S15 ADC122_IN3 CMP3_IN2
ANA_S16 ADC122_IN4 VREF_IN0
ANA_S17 ADC122_IN5 VREF_IN1
ANA_S18 DAC12_0_OUT VREF_IN2
ANA_S19 DAC12_1_OUT
ANA_S20 LPCMP_IN0
ANA_S21 LPCMP_IN1
ANA_S22 LPCMP_IN2
ANA_S23 LPCMP_IN3
Table 3-32 presents the analog signals with the respective mapping to the analog modules and provides
descriptions to their functions.
Table 3-32 Analog Signal Descriptions
Signal Name Pin Name Type Description
ADC120_IN0 (ADC120 input 0)
ANA_S0 P0_0 A ADC24_IN0_P (ADC24 differential input 0 positive)
CMP0_IN0 (CMP0 input 0)
ADC120_IN1 (ADC120 input 1)
ANA_S1 P0_1 A ADC24_IN1_P (ADC24 differential input 1 positive)
CMP1_IN0 (CMP1 input 0)
ADC120_IN2 (ADC120 input 2)
ANA_S2 P0_2 A ADC24_IN2_P (ADC24 differential input 2 positive)
CMP2_IN0 (CMP2 input 0)
ADC120_IN3 (ADC120 input 3)
ANA_S3 P0_3 A ADC24_IN3_P (ADC24 differential input 3 positive)
CMP3_IN0 (CMP3 input 0)
ADC120_IN4 (ADC120 input 4)
ANA_S4 P0_4 A ADC24_IN0_N (ADC24 differential input 0 negative)
CMP0_IN3 (CMP0 input 3)
ADC120_IN5 (ADC120 input 5)
ANA_S5 P0_5 A ADC24_IN1_N (ADC24 differential input 1 negative)
CMP1_IN3 (CMP1 input 3)
ADC121_IN0 (ADC121 input 0)
ANA_S6 P0_6 A ADC24_IN2_N (ADC24 differential input 2 negative)
CMP0_IN1 (CMP0 input 1)
ADC121_IN1 (ADC121 input 1)
ANA_S7 P0_7 A ADC24_IN3_N (ADC24 differential input 3 negative)
CMP1_IN1 (CMP1 input 1)
ANA_S8 P1_0 A ADC121_IN2 (ADC121 input 2)
4 Pin Assignments
SEUART_
B RX
JTAG_TCK GPIO5_0 GPIO5_2 GPIO5_6 VSS GPIO6_4 GPIO12_5 GPIO7_0 GPIO8_2 VSS VSS N.C. N.C.
D GPIO12_0 GPIO12_1 NSRST GPIO4_3 GPIO13_6 GPIO5_4 GPIO6_2 GPIO6_6 GPIO7_1 GPIO8_4 VSS N/A N.C. N.C.
E GPIO13_3 GPIO13_4 GPIO4_0 GPIO12_3 GPIO4_2 JTAG_TDO GPIO5_1 GPIO6_1 GPIO12_7 GPIO8_1 N.C. N.C. VSS VSS
VDD_IO_
F GPIO13_0
1V8
GPIO13_1 GPIO13_2 GPIO2_7 GPIO2_5 GPIO6_0 GPIO12_6 GPIO7_2 GPIO3_3 GPIO3_2 N.C. VSS N.C.
VDD_ VREG_
G VSS
CORE_0V8
GPIO2_4 GPIO2_0 GPIO1_6 N.C.
MIPI_1V8
GPIO6_5 GPIO3_0 GPIO3_1 GPIO3_4 GPIO3_5 GPIO14_2 GPIO14_1
VDD_
H GPIO2_6 GPIO2_3 GPIO1_7 GPIO1_2 GPIO0_6 GPIO0_1 USB_VBUS GPIO9_1 GPIO9_0 GPIO8_7 GPIO8_6
CORE_0V8
VSS GPIO8_5
VREG_
J GPIO2_2 GPIO2_1 GPIO1_4 GPIO0_7 GPIO0_2
DIG_1V8
MIPI_REXT GPIOV_5 GPIO11_1 GPIO9_7 GPIO9_5 GPIO9_4 GPIO9_3 GPIO9_2
K GPIO1_5 GPIO1_3 GPIO0_5 GPIO0_4 POR_N VDD_BATT USB_REXT GPIO11_6 GPIOV_0 GPIO10_3 GPIO10_2 GPIO10_1 GPIO10_0 GPIO9_6
VDD_ VREG_
L GPIO1_0 GPIO1_1
MAIN
GPIO0_0 VSS VREG_AON
MIPI_0V8
GPIO14_6 GPIOV_6 GPIO7_5 GPIO10_7 GPIO10_6 GPIO10_5 GPIO10_4
MIPICSI_ MIPIDSI_
R VSW VSS_BUCK LFXO_P VSS VSS USB_DP GPIO14_7 GPIO14_4 GPIO11_7 GPIO3_7 VSS GPIOV_4
0_N C_P
For detailed information about package outlines, thermal characteristics, and markings, see Section 6.2.1
WLCSP208 Package Information.
VDD_
GPIO14_ GPIO13_
B N.C. VSS GPIO7_1 GPIO8_4 CORE_ GPIO3_0 GPIO8_0 GPIO7_0 GPIO6_3 GPIO5_7 GPIO5_6 GPIO5_3 GPIO5_1 GPIO4_7 GPIO4_4 GPIO4_3 GPIO4_1
0 6
0V8
VDD_ VDD_
GPIO12_ GPIO13_ GPIO13_ GPIO12_ GPIO12_
E CORE_ GPIO3_2 GPIO6_6 GPIO6_5 GPIO6_4 GPIO6_1 GPIO5_5 GPIO5_4 GPIO5_2 CORE_
6 3 4 2 1
0V8 0V8
GPIO14_
H GPIO8_5 GPIO9_3 GPIO2_3 GPIO2_6 GPIO2_5
1
GPIO11_
J GPIO8_7 GPIO8_6 GPIO9_4 N.C. VSS N.C. NSRST GPIO2_2 GPIO1_7 GPIO2_7
5
GPIO11_ GPIO14_
K GPIO9_1 GPIO9_0 GPIO9_6 VSS VSS VSS GPIO1_3 GPIO2_1 GPIO2_0
4 6
VREG_
GPIO10_ GPIO10_ GPIO10_
N GPIO0_5 VREF_P MIPI_
2 3 5
1V8
VDD_
T GPIO7_4 GPIO7_5 VSW
BATT
VREG_ VREG_
U GPIO7_7 GPIOV_2 GPIO7_6 POR_N
AON DIG_1V8
VDD_ VREG_
USB_ MIPIDSI_ MIPIDSI_ MIPIDSI_ MIPI_ MIPICSI_ MIPICSI_ MIPICSI_ VSS_
V GPIOV_3 GPIOV_0 GPIOV_4 GPIOV_6 GPIO3_6 CORE_ USB_DM VSS LFXO_P AUX_
REXT 1_N C_P 0_N REXT 0_N 1_P C_N BUCK
0V8 1V8
VREG_
VDD_IO_ VDD_IO_ USB_ VDD_ MIPIDSI_ MIPIDSI_ MIPIDSI_ VDD_ VREG_ MIPICSI_ MIPICSI_ MIPICSI_ VREG_
W GPIOV_1 GPIOV_5 GPIOV_7 USB_DP LFXO_N CORE_
FLEX 1V8 VBUS USB_3V3 1_P C_N 0_P MIPI_1V8 MIPI_0V8 0_P 1_N C_P LP_1V8
0V8
For detailed information about package outlines, thermal characteristics, and markings, see Section 6.2.2
FBGA194 Package Information.
CAUTION
The following pin multiplexing options are recommended:
- For OSPI0, the OSPI0_D[0-7]_B data bus signals are recommended to be used for 100 MHz operation. OSPI0_D[0-7]_A and OSPI0_D[0-7]_C
data bus signals are recommended to be used for 50 MHz operation.
- For OSPI1, the OSPI1_D[0-7]_C data bus signals are recommended to be used for 100 MHz operation. OSPI1_D[0-7]_A and OSPI1_D[0-7]_B
data bus signals are recommended to be used for 50 MHz operation.
- For SDMMC, the SD_*_C signals are recommended to be used for 50 MHz operation. SD_*_A, SD_*_B, and SD_*_D signals are
recommended to be used for 25 MHz operation.
- For CAM_PCLK and CAM_XVCLK signals, recommended to be used are CAM_PCLK_B and CAM_XVCLK_B pin multiplexing options.
- For LPCAM_PCLK and LPCAM_XVCLK signals, recommended to be used are LPCAM_PCLK_A and LPCAM_XVCLK_A pin multiplexing options.
l I—Digital Input
O—Digital Output
l
l R—Radio frequency
l P—Passive
l PWR—Power
l GND—Ground
l N.C.—No Connect
6. Configuration Register—Associated pin control register. For more information on registers, refer to the corresponding series-specific Hardware Reference
Manual, Section Signal Multiplexing and I/O Buffer Configuration.
7. Buffer Type—Associated I/O buffer type, if applicable:
l LVCMOS—1.8-V Low-Voltage CMOS digital I/O buffer
Pin Name 0 1 2 3 4 5 6 7
P3_4 GPIO3_4 OSPI0_RXDS_A UART5_RX_A LPPDM_C0_B I2S1_SCLK_A I2C0_SCL_B QEC1_Y_A CAM_D8_A
P3_5 GPIO3_5 OSPI0_SCLKN_A UART5_TX_A LPPDM_D0_B SPI0_SS1_B I2C0_SDA_B QEC1_Z_A CAM_D9_A
P3_6 GPIO3_6 HFXO_OUT_A LPUART_CTS_B LPPDM_C1_B SPI0_SS2_B I2C1_SDA_B QEC2_X_A CAM_D10_A
P3_7 GPIO3_7 JTAG_TRACECLK LPUART_RTS_B LPPDM_D1_B SPI1_SS1_A I2C1_SCL_B QEC2_Y_A CAM_D11_A
P4_0 GPIO4_0 JTAG_TDATA0 I2S1_WS_A SPI1_SS2_A QEC2_Z_A CDC_VSYNC_B CAM_D12_A
P4_1 GPIO4_1 JTAG_TDATA1 I2S0_SDI_B SPI1_SS3_A QEC3_X_A SD_CLK_D CDC_HSYNC_B CAM_D13_A
P4_2 GPIO4_2 JTAG_TDATA2 I2S0_SDO_B SPI2_MISO_A QEC3_Y_A SD_CMD_D CAM_D14_A
P4_3 GPIO4_3 JTAG_TDATA3 I2S0_SCLK_B SPI2_MOSI_A QEC3_Z_A SD_RST_D CAM_D15_A
P4_4 GPIO4_4 JTAG_TCK I2S0_WS_B SPI2_SCLK_A FAULT0_A
P4_5 GPIO4_5 JTAG_TMS SPI2_SS0_A FAULT1_A
P4_6 GPIO4_6 JTAG_TDI SPI2_SS1_A FAULT2_A
P4_7 GPIO4_7 JTAG_TDO SPI2_SS2_A FAULT3_A
P5_0 GPIO5_0 OSPI1_RXDS_A UART4_RX_C PDM_D2_A SPI0_MISO_B I2C2_SDA_B UT0_T0_B SD_D0_A
P5_1 GPIO5_1 OSPI1_SS0_A UART4_TX_C PDM_D3_A SPI0_MOSI_B I2C2_SCL_B UT0_T1_B SD_D1_A
P5_2 GPIO5_2 OSPI1_SCLKN_A UART5_RX_C PDM_C3_A SPI0_SS0_B LPI2C_SCL_B UT1_T0_B SD_D2_A
P5_3 GPIO5_3 OSPI1_SCLK_A UART5_TX_C SPI0_SCLK_B LPI2C_SDA_B UT1_T1_B SD_D3_A CDC_PCLK_A
P5_4 GPIO5_4 OSPI1_SS1_A UART3_CTS_A PDM_D2_B SPI0_SS3_A UT2_T0_B SD_D4_A CDC_DE_A
P5_5 GPIO5_5 OSPI1_SCLK_C UART3_RTS_A PDM_D3_B UT2_T1_B SD_D5_A ETH_RXD0_A CDC_HSYNC_A
P5_6 GPIO5_6 RESERVED UART1_CTS_B I2C2_SCL_C UT3_T0_B SD_D6_A ETH_RXD1_A CDC_VSYNC_A
P5_7 GPIO5_7 OSPI1_SS0_C UART1_RTS_B I2C2_SDA_C UT3_T1_B SD_D7_A ETH_RST_A
P6_0 GPIO6_0 OSPI0_D0_C UART4_DE_A PDM_D0_C UT4_T0_B SD_D0_D ETH_TXD0_A
P6_1 GPIO6_1 OSPI0_D1_C UART5_DE_A PDM_C0_C UT4_T1_B SD_D1_D ETH_TXD1_A
P6_2 GPIO6_2 OSPI0_D2_C UART2_CTS_A PDM_D1_C UT5_T0_B SD_D2_D ETH_TXEN_A
P6_3 GPIO6_3 OSPI0_D3_C UART2_RTS_A PDM_C1_C UT5_T1_B SD_D3_D ETH_IRQ_A
P6_4 GPIO6_4 OSPI0_D4_C UART2_CTS_B SPI1_SS0_B UT6_T0_B SD_D4_D ETH_REFCLK_A
P6_5 GPIO6_5 OSPI0_D5_C UART2_RTS_B SPI1_SS1_B UT6_T1_B SD_D5_D ETH_MDIO_A
P6_6 GPIO6_6 OSPI0_D6_C UART0_CTS_B SPI1_SS2_B UT7_T0_B SD_D6_D ETH_MDC_A
P6_7 GPIO6_7 OSPI0_D7_C UART0_RTS_B PDM_C2_A SPI1_SS3_B UT7_T1_B SD_D7_D ETH_CRS_DV_A
P7_0 GPIO7_0 CMP3_OUT_A SPI0_MISO_C I2C0_SDA_C UT8_T0_B SD_CMD_A CAN_RXD_A
P7_1 GPIO7_1 CMP2_OUT_A SPI0_MOSI_C I2C0_SCL_C UT8_T1_B SD_CLK_A CAN_TXD_A
P7_2 GPIO7_2 UART3_CTS_B CMP1_OUT_A SPI0_SCLK_C I2C1_SDA_C UT9_T0_B SD_RST_A
P7_3 GPIO7_3 UART3_RTS_B CMP0_OUT_A SPI0_SS0_C I2C1_SCL_C UT9_T1_B CAN_STBY_A
P7_4 GPIO7_4 LPUART_CTS_A LPPDM_C2_A LPSPI_MISO_A LPI2C_SCL_A UT10_T0_B
Pin Name 0 1 2 3 4 5 6 7
P7_5 GPIO7_5 LPUART_RTS_A LPPDM_D2_A LPSPI_MOSI_A LPI2C_SDA_A UT10_T1_B
P7_6 GPIO7_6 LPUART_RX_A LPPDM_C3_A LPSPI_SCLK_A I3C_SDA_D UT11_T0_B
P7_7 GPIO7_7 LPUART_TX_A LPPDM_D3_A LPSPI_SS_A I3C_SCL_D UT11_T1_B
P8_0 GPIO8_0 OSPI1_SCLKN_C AUDIO_CLK_A FAULT0_B LPCAM_D0_A SD_D0_C CDC_D0_A CAM_D0_B
P8_1 GPIO8_1 I2S2_SDI_A FAULT1_B LPCAM_D1_A SD_D1_C CDC_D1_A CAM_D1_B
P8_2 GPIO8_2 I2S2_SDO_A SPI0_SS3_B FAULT2_B LPCAM_D2_A SD_D2_C CDC_D2_A CAM_D2_B
P8_3 GPIO8_3 I2S2_SCLK_A SPI1_MISO_B FAULT3_B LPCAM_D3_A SD_D3_C CDC_D3_A CAM_D3_B
P8_4 GPIO8_4 I2S2_WS_A SPI1_MOSI_B QEC0_X_B LPCAM_D4_A SD_D4_C CDC_D4_A CAM_D4_B
P8_5 GPIO8_5 RESERVED SPI1_SCLK_B QEC0_Y_B LPCAM_D5_A SD_D5_C CDC_D5_A CAM_D5_B
P8_6 GPIO8_6 RESERVED I2S3_SCLK_B QEC0_Z_B LPCAM_D6_A SD_D6_C CDC_D6_A CAM_D6_B
P8_7 GPIO8_7 RESERVED I2S3_WS_B QEC1_X_B LPCAM_D7_A SD_D7_C CDC_D7_A CAM_D7_B
P9_0 GPIO9_0 RESERVED I2S3_SDI_B QEC1_Y_B SD_CMD_C CDC_D8_A CAM_D8_B
P9_1 GPIO9_1 LPUART_RX_B I2S3_SDO_B QEC1_Z_B SD_CLK_C CDC_D9_A CAM_D9_B
P9_2 GPIO9_2 LPUART_TX_B I2S3_SDI_A SPI2_MISO_B QEC2_X_B SD_RST_C CDC_D10_A CAM_D10_B
P9_3 GPIO9_3 HFXO_OUT_B UART7_RX_B I2S3_SDO_A SPI2_MOSI_B QEC2_Y_B CDC_D11_A CAM_D11_B
P9_4 GPIO9_4 UART7_TX_B I2S3_SCLK_A SPI2_SCLK_B I2C3_SDA_C QEC2_Z_B CDC_D12_A CAM_D12_B
P9_5 GPIO9_5 OSPI1_D0_C I2S3_WS_A SPI2_SS0_B I2C3_SCL_C QEC3_X_B CDC_D13_A CAM_D13_B
P9_6 GPIO9_6 OSPI1_D1_C AUDIO_CLK_B SPI2_SS1_B I2C3_SDA_B QEC3_Y_B CDC_D14_A CAM_D14_B
P9_7 GPIO9_7 OSPI1_D2_C UART7_DE_B SPI2_SS2_B I2C3_SCL_B QEC3_Z_B CDC_D15_A CAM_D15_B
P10_0 GPIO10_0 OSPI1_D3_C UART6_DE_B SPI2_SS3_B UT0_T0_C LPCAM_HSYNC_A CDC_D16_A CAM_HSYNC_B
P10_1 GPIO10_1 OSPI1_D4_C LPI2S_SDI_B UT0_T1_C LPCAM_VSYNC_A CDC_D17_A CAM_VSYNC_B
P10_2 GPIO10_2 OSPI1_D5_C LPI2S_SDO_B UT1_T0_C LPCAM_PCLK_A CDC_D18_A CAM_PCLK_B
P10_3 GPIO10_3 OSPI1_D6_C LPI2S_SCLK_B UT1_T1_C LPCAM_XVCLK_A CDC_D19_A CAM_XVCLK_B
P10_4 GPIO10_4 OSPI1_D7_C LPI2S_WS_B I2C0_SDA_D UT2_T0_C ETH_TXD0_B CDC_D20_A
P10_5 GPIO10_5 UART6_RX_A I2S2_SDI_B SPI3_MISO_B I2C0_SCL_D UT2_T1_C ETH_TXD1_B CDC_D21_A
P10_6 GPIO10_6 UART6_TX_A I2S2_SDO_B SPI3_MOSI_B I2C1_SDA_D UT3_T0_C ETH_TXEN_B CDC_D22_A
P10_7 GPIO10_7 UART7_RX_A I2S2_SCLK_B SPI3_SCLK_B I2C1_SCL_D UT3_T1_C CDC_D23_A OSPI1_RXDS_C
P11_0 GPIO11_0 OSPI1_D0_A UART7_TX_A I2S2_WS_B SPI3_SS0_B UT4_T0_C ETH_REFCLK_B CDC_D0_B
P11_1 GPIO11_1 OSPI1_D1_A UART7_DE_A SPI3_SS1_B UT4_T1_C ETH_MDIO_B CDC_D1_B
P11_2 GPIO11_2 OSPI1_D2_A UART6_DE_A LPPDM_C2_B SPI3_SS2_B UT5_T0_C ETH_MDC_B CDC_D2_B
P11_3 GPIO11_3 OSPI1_D3_A UART5_RX_B LPPDM_C3_B SPI3_SS3_B UT5_T1_C ETH_RXD0_B CDC_D3_B
P11_4 GPIO11_4 OSPI1_D4_A UART5_TX_B PDM_C2_B LPSPI_MISO_B UT6_T0_C ETH_RXD1_B CDC_D4_B
P11_5 GPIO11_5 OSPI1_D5_A UART6_RX_B PDM_C3_B LPSPI_MOSI_B UT6_T1_C ETH_CRS_DV_B CDC_D5_B
Pin Name 0 1 2 3 4 5 6 7
P11_6 GPIO11_6 OSPI1_D6_A UART6_TX_B LPPDM_D2_B LPSPI_SCLK_B UT7_T0_C ETH_RST_B CDC_D6_B
P11_7 GPIO11_7 OSPI1_D7_A UART5_DE_B LPPDM_D3_B LPSPI_SS_B UT7_T1_C ETH_IRQ_B CDC_D7_B
P12_0 GPIO12_0 OSPI0_SCLK_C AUDIO_CLK_C I2S1_SDI_B UT8_T0_C CDC_D8_B
P12_1 GPIO12_1 OSPI0_SCLKN_C UART4_RX_B I2S1_SDO_B UT8_T1_C CDC_D9_B
P12_2 GPIO12_2 OSPI0_RXDS_C UART4_TX_B I2S1_SCLK_B UT9_T0_C CDC_D10_B
P12_3 GPIO12_3 OSPI0_SS0_C UART4_DE_B I2S1_WS_B UT9_T1_C CDC_D11_B
P12_4 GPIO12_4 OSPI0_SS1_C SPI3_MISO_A UT10_T0_C CAN_RXD_C CDC_D12_B
P12_5 GPIO12_5 SPI3_MOSI_A UT10_T1_C CAN_TXD_C CDC_D13_B
P12_6 GPIO12_6 SPI3_SCLK_A UT11_T0_C CAN_STBY_C CDC_D14_B
P12_7 GPIO12_7 OSPI1_RXDS_B SPI3_SS0_A UT11_T1_C CDC_D15_B
P13_0 GPIO13_0 OSPI1_D0_B SPI3_SS1_A QEC0_X_C SD_D0_B CDC_D16_B
P13_1 GPIO13_1 OSPI1_D1_B SPI3_SS2_A QEC0_Y_C SD_D1_B CDC_D17_B
P13_2 GPIO13_2 OSPI1_D2_B SPI3_SS3_A QEC0_Z_C SD_D2_B CDC_D18_B
P13_3 GPIO13_3 OSPI1_D3_B SPI2_SS3_A QEC1_X_C SD_D3_B CDC_D19_B
P13_4 GPIO13_4 OSPI1_D4_B LPI2S_SDI_C QEC1_Y_C SD_D4_B CDC_D20_B
P13_5 GPIO13_5 OSPI1_D5_B LPI2S_SDO_C QEC1_Z_C SD_D5_B CDC_D21_B
P13_6 GPIO13_6 OSPI1_D6_B LPI2S_SCLK_C QEC2_X_C SD_D6_B CDC_D22_B
P13_7 GPIO13_7 OSPI1_D7_B LPI2S_WS_C QEC2_Y_C SD_D7_B CDC_D23_B
P14_0 GPIO14_0 OSPI1_SCLK_B UART6_RX_C QEC2_Z_C SD_CMD_B
P14_1 GPIO14_1 OSPI1_SCLKN_B UART6_TX_C QEC3_X_C SD_CLK_B
P14_2 GPIO14_2 OSPI1_SS0_B UART7_RX_C QEC3_Y_C SD_RST_B
P14_3 GPIO14_3 OSPI1_SS1_B UART7_TX_C QEC3_Z_C
P14_4 GPIO14_4 CMP3_OUT_B SPI1_MISO_C FAULT0_C
P14_5 GPIO14_5 CMP2_OUT_B SPI1_MOSI_C FAULT1_C
P14_6 GPIO14_6 CMP1_OUT_B SPI1_SCLK_C FAULT2_C
P14_7 GPIO14_7 CMP0_OUT_B SPI1_SS0_C FAULT3_C
5 Electrical Characteristics
NOTE
Specifications shown in Table 5-5 Power Modes Case Definition are subject to change.
Table 5-5 provides status of each module during different power modes of the device.
Table 5-5 Power Modes Case Definition
Current
SRAM
Main LP Consumption
Voltage Clock Wake-Up
Power Mode MRAM M55- Peripherals Peripherals
Regulation Bulk M55-HE 4KB Source Sources
HP Power Power Typ Units Typ Units
SRAM TCM Backup
TCM
GO Modes IVDD_MAIN when VDD_MAIN = 3.3 V
All CPU cores
running CoreMark
at max frequency.
GO_1 94(3) mA
Both NPU cores
running convolution
MAC workload.
All CPU cores
ON ON ON
running CoreMark Any
GO_2 64 mA
at max frequency. ON with interrupt
ON PLL
No NPU enabled. DC-DC ON clocks gated All ON from a N/A
A32-0 and A32-1 powered
running CoreMark peripheral 58 mA
GO_3
at 800 MHz.
No NPU is enabled. 72 μA/MHz
Only M55-HP
running CoreMark 25(3) mA
GO_4 OFF
at 400 MHz. OFF OFF
No NPU is enabled. 62 μA/MHz
GO_5 Only M55-HE OFF ON HFRC All OFF 2.1 mA
Current
SRAM
Main LP Consumption
Voltage Clock Wake-Up
Power Mode MRAM M55- Peripherals Peripherals
Regulation Bulk M55-HE 4KB Source Sources
HP Power Power Typ Units Typ Units
SRAM TCM Backup
TCM
running
WHILE(1) at
76.8 MHz.
No NPU is enabled. 27 μA/MHz
Only M55-HE
running
725 μA
GO_6 WHILE(1) at
19.2 MHz.
No NPU is enabled. 38 μA/MHz
READY Modes IVDD_MAIN when VDD_MAIN = 3.3 V
M55-HP WFI(2) at
400 MHz from PLL. ON with
RDY_1 ON ON OFF PLL Any 13.5(4) mA < 40 ns
M55-HE powered clocks gated
interrupt
off.
DC-DC OFF ON All ON from a
M55-HE WFI at
powered
78.6 MHz from
RDY_2 OFF OFF ON HFRC All OFF peripheral 1.4 mA < 200 ns
HFRC. M55-HP
powered off.
IDLE Modes IVDD_MAIN when VDD_MAIN = 3.3 V
All CPU cores
powered off. Any
IDLE_1 HFXO 2.5 mA 2-4 μs
38.4 MHz clock interrupt
from HFXO. OFF but OFF but ON with from a
DC-DC OFF OFF OFF All ON
All CPU cores retained retained clocks gated powered
powered off. peripheral
IDLE_2 HFRC (1) 900 μA 2-4 μs
600 kHz clock from
HFRC.
STANDBY Modes IVDD_MAIN when VDD_MAIN = 3.3 V
Any
LPUART,
All CPU cores interrupt
OFF but OFF but LPI2C ON +
STBY_1 powered off. HFRC DC-DC OFF OFF OFF HFRC All OFF from a 65 μA 2-4 μs
retained retained STOP Mode
ready. powered
peripherals
peripheral
STOP Modes IVDD_BATT when VDD_BATT = 3.0 V
STOP_1 STOP_2 plus 512KB LDO OFF OFF OFF OFF but OFF but LFXO All OFF LPRTC, Any 6150 nA 1.1 ms
Current
SRAM
Main LP Consumption
Voltage Clock Wake-Up
Power Mode MRAM M55- Peripherals Peripherals
Regulation Bulk M55-HE 4KB Source Sources
HP Power Power Typ Units Typ Units
SRAM TCM Backup
TCM
of M55-HE TCM
retained
SRAM retained.
STOP_3 plus 4KB retained
STOP_2 Backup SRAM LPTIMER, 1450 nA
retained. CMP, BOD,
STOP_4 plus LPGPIO ON
interrupt
LPTIMER, BOD,
STOP_3 from a 1400 nA
CMP, and LPGPIO
powered
active. OFF
peripheral
STOP_5 plus LPRTC
OFF LPRTC +
STOP_4 running from 1350 nA
LPGPIO ON
32.768 kHz LFXO.
32.7 kHz LFRC
STOP_5 running, all other LFRC LPGPIO ON 1250 nA
functions off.
STOP Mode current
N/A
adder IVDD_IO_1V8
I/O Domain Adder for STOP
when VDD_IO_1V8
in all cases
= 1.8 V
200 nA
1. If RTSS-HE is powered down then the LPCPI, LPI2S, LPPDM, and LPSPI in the same subsystem are powered down too.
2. WFI: Wait for Interrupt.
3. At ACLK = 400 MHz, HCLK = 200 MHz.
4. At ACLK = 100 MHz, HCLK = 50 MHz, PCLK = 25 MHz.
VDD_BATT
VDD_MAIN
VDD_USB_3V3
VDD_IO_1V8
VDD_IO_FLEX
S32K_CLK
HFOSC_CLK
The following restrictions and considerations apply to Figure 5-1 Power-Up/Power-Down Sequencing:
n The power supply ramp-up time (10% to 90%) must be between 1 μs and 5 ms.
n During power-up phase, VDD_BATT power supply must come up at the same time or before the other
supplies. All other power supplies can come up in any order.
n During power-down phase, VDD_BATT power supply must come down at the same time or after the
other supplies. All other power supplies can come down in any order.
n The low-frequency S32K_CLK comes up after VDD_BATT.
n The high-frequency HFOSC_CLK comes up after DC-DC converter is stable.
NOTE
User SRAM size and availability is device part number dependent. For more information on SRAM
block enabled for each part number and their size, see Section 7 Ordering Information.
LPTM2
LPTM1 Time
LPTM3
UTM2
UTM1 Time
UTM3
QEC1
QEC_A/B
QEC2 QEC3
QEC_IL/QEC_IH
QEC4 QEC5
QEC_SL/QEC_SH
qec_01
CLK
ETH4
ETH5 ETH6
CLK
DATA
ETH7
CLK
DATA
eth_01
SDA
I2C11
I2C4 I2C5
I2C2
SCL
I2C9 I2C6 I2C7 I2C4 I2C5 I2C8 I2C10
I2C3
Stop Start Repeated Stop
i2c_01
Start
i2s_01
SDIN
SDA
I3C5 I3C6
I3C1
SCL
I3C2
i3c_02
Figure 5-9 I3C Push-Pull Timing Diagram
SDA
I3C11 I3C10 I3C5
I3C1 I3C5 I3C9
I3C2 I3C8 I3C9
SCL
I3C4 I3C7 I3C6
Stop Start Repeated Stop
Start
i3c_01
5.7.3.6 PDM Timing Characteristics
Table 5-33 and Figure 5-10 present the PDM timing characteristics.
Table 5-33 PDM Timing Characteristics
No Parameter Min Typ Max Unit
fOP Operating frequency, PDM_CLK 1.032 1.032 1.032 MHz
PDM2 tW_CLK_H Pulse duration, CLK high 484 1 / fOP
PDM3 tW_CLK_L Pulse duration, CLK low 484 1 / fOP
PDM4 tSU_DAT Setup time, DAT 65 ns
PDM5 tH_DAT Hold time, DAT 0 ns
CLK
PDM2 PDM3
PDM4 PDM5
DAT
SCLK CPOL=0
SP5
SP4
SCLK CPOL=1
SP8 SP8
SP9 SP9
CPHA=0
MISO bit n-1 bit n-2 bit n-3 bit n-4 bit 0
SP8
SP8
SP9 SP9
CPHA=1
MISO bit n-1 bit n-2 bit n-3 bit 1 bit 0
spi_01
Figure 5-12 SPI Transmit Timing Diagram
SP6 SP7
SS
SP1
SP4
SP5
SCLK CPOL=0
SP5
SP4
SCLK CPOL=1
SP10
SP11 SP11
CPHA=0
MOSI bit n-1 bit n-2 bit n-3 bit n-4 bit 0
SP11
SP11 SP11
CPHA=1
MOSI bit n-1 bit n-2 bit n-3 bit 1 bit 0
spi_02
CTS
UT3 UT4
TXD
UT5 UT6
RXD
uart_01
Start Bit Data Bits
CLK
O9 O10
DATA_OUT D0 D1 D2
O8
O7
DATA_IN D0 D1 D2
ospi_02
5.7.4.2 SDMMC Timing Characteristics
Table 5-37 and Figure 5-15 present the SDMMC timing characteristics in DS mode.
Table 5-37 SDMMC Timing Characteristics (DS mode)
No Parameter Min Max Unit
DS1 tc_CLK Cycle time, CLK 40(1) ns
DS2 tR_CLK Rise time, CLK 10 ns
DS3 tF_CLK Fall time, CLK 10 ns
DC_CLK Duty cycle 45 55 %
DS5 ts_CMD_CLK Setup time, CMD valid before CLK rising edge 11.7 ns
DS6 th_CMD_CLK Hold time, CMD valid after CLK rising edge 8.3 ns
DS7 ts_DATA_CLK Setup time, DATA valid before CLK rising edge 11.7 ns
DS8 th_DATA_CLK Hold time, DATA valid after CLK rising edge 8.3 ns
1. Some pin multiplex options will reduce the operating frequency. Please see Cautionary information at the start of Section 4.2 Pin
Function Options by Location.
CLK
DS5 DS6 DS2
CMD
DS7 DS8
DATA
mmc_01
Table 5-38 and Figure 5-16 present the SDMMC timing characteristics in HS mode.
Table 5-38 SDMMC Timing Characteristics (HS mode)
No Parameter Min Max Unit
HS1 tc_CLK Cycle time, CLK 20 ns
HS2 tR_CLK Rise time, CLK 3 ns
CLK
HS5 HS6 HS2
CMD
HS7 HS8
DATA
mmc_01
Table 5-39 and Figure 5-17 present the SDMMC timing characteristics in SDR12/SDR25/SDR50 modes.
Table 5-39 SDMMC Timing Characteristics (SDR12/SDR25/SDR50)
No Parameter Mode Min Max Unit
SDR12 40 ns
MC1 tc_CLK Cycle time, CLK SDR25 20 ns
SDR50 10 ns
MC2 tR_CLK Rise time, CLK 3 ns
MC3 tF_CLK Fall time, CLK 3 ns
DC_CLK Duty cycle 45 55 %
SDR12 3 ns
MC5 ts_CMD_CLK Setup time, CMD valid before CLK rising edge SDR25 3 ns
SDR50 3 ns
SDR12 0.8 ns
MC6 th_CMD_CLK Hold time, CMD valid after CLK rising edge SDR25 0.8 ns
SDR50 0.8 ns
SDR12 3 ns
MC7 ts_DATA_CLK Setup time, DATA valid before CLK rising edge SDR25 3 ns
SDR50 3 ns
SDR12 0.8 ns
MC8 th_DATA_CLK Hold time, DATA valid after CLK rising edge SDR25 0.8 ns
SDR50 0.8 ns
CLK
MC5 MC6 MC2
CMD
MC7 MC8
DATA
mmc_01
5.7.5 Camera Interfaces
HSYNC
CPI7
CPI8
DATA D0 Dn-1
DP5
DE
DP5
VSYNC
DP5
HSYNC
DP5
DATA D1 D1 ... Dn
dpi_01
TCK
JT6
TDO
JT5
JT4
TDI
TMS
jtag_01
6 Package Information
Pin 1 Indicator
AXXXXXXX
Product Part Number
XXXXXXX
Suffix - ABCDEF YYWW
Lot Number XXXXXXXXX.XXX.XX
Wafer Reference XX - XXX - XXX
Pin 1 Indicator
AXXXXXXX
Product Part Number
XXXXXXXX
Suffix - ABCDEF YYWW
Lot Number XXXXXXXXX.XXX.XX
Device Manufacturer
A - Alif Semiconductor
Device Family
B - BLE-connected embedded microcontrollers
E - Ensemble, embedded processors
Device Series
0 - Service MCU
1 - Efficiency MCU
3 - Performance MCU
5 - Fusion processor MCU/MPU
7 - Extreme fusion processor MCU/MPU
Number of Application Processing Cores
0 - Zero cores
1 - One cores
2 - Two cores
Number of Real Time Processing Cores
0 - Zero cores
1 - One cores
2 - Two cores
Security Attribute
B - Basic security
F - Full security, complete life cycle management
Machine Learning and AI Capability
1 - MCU Vector Extension (Helium)
4 - Single Neural Processing Unit (Ethos) + MCU Vector Extension (Helium)
8 - Dual Neural Processing Units (Ethos) + MCU Vector Extension (Helium)
Wireless Capability
0 - No wireless
M - BLE + IEEE 802.15.4
Peripheral Set
0 through 9, A through Z = Level of peripheral selection mix, higher is typically more peripherals
On-Chip Application MRAM Size
MRAM memory size in MB
1st digit - N = None, 1 through 9 = 1MB through 9MB, A through F = 10MB through 15MB, 0 = 16MB
2nd digit - 0 = 0KB, 1 = 128KB, 2 = 256KB, 3 = 384KB, 5 = 512KB, 7 = 768KB
On-Chip Application SRAM Size
SRAM memory size in MB
1st digit - N = None, 1 through 9 = 1MB through 9MB, A through F = 10MB through 15MB, 0 = 16MB
2nd digit - 0 = 0KB, 1 = 128KB, 2 = 256KB, 3 = 384KB, 5 = 512KB, 7 = 768KB
Package Type and Pin Count
A - WLCSP208, 0.5 mm pitch
H - WLCSP90, 0.4 mm pitch
Table 6-2 presents the Suffix (characters after main part number) decoding.
Table 6-2 Suffix Definition
Position Description
A ID
B ID revision
C Firmware version
D Fab site. D = Dresden
E Final assembly site. M = Malaysia, K = South Korea
F Final test site. S = Singapore, E = USA
Space
Y
Calendar year of device production
Y
W
Work week of device production
W
G G
E
H H
E1
J J
K K
L L
M M
N N
P P
R R
1 3 5 7 9 11 13 15 17 19 21 23 25 27
2 4 6 8 10 12 14 16 18 20 22 24 26 28
eD
A
D1
aaa (4X) C
D
ddd C
PACKAGE OUTLINE
WLCSP 208 7.574 X 6.850 X 0.500
COMMON DIMENSIONS
A2
7 Ordering Information
Table 7-1 presents the optional features for each orderable part number.
Table 7-1 Orderable Part Numbers
Operating
Part Number MRAM SRAM GPIO (1.8 V) Package
Temperature
AE722F80F55D5AS 5.5MB 13.5MB 120 WLCSP208 Standard
AE722F80F55D5LS 5.5MB 13.5MB 120 FBGA194 Standard
Table 7-2 shows the user SRAM banks with their corresponding sizes (in KB) available for each part number.
Table 7-2 Part Numbers SRAM Breakdown
SRAM2 SRAM3 SRAM4 SRAM5
Total (M55- (M55- (M55- (M55-
SRAM0 SRAM1 SRAM6 SRAM7 SRAM8 SRAM9
Part Number SRAM HP HP HE HE
(KB) (KB) (KB) (KB) (KB) (KB)
(KB) ITCM) DTCM) ITCM) DTCM)
(KB) (KB) (KB) (KB)
AE722F80F55D5AS 13824 4096 2560 256 1024 256 256 2048 512 2048 768
AE722F80F55D5LS 13824 4096 2560 256 1024 256 256 2048 512 2048 768
It is possible to configure address ranges within SRAM0 through SRAM9 to appear as contiguous address
space to a given M55 core through configuration of the firewall controllers. For more information on the
firewalls, refer to the corresponding device series-specific Hardware Reference Manual, Section Interconnect
Firewall Functional Description.
For complete part number decoding, refer to Section 6.1 Device Marking Definition.
8.1 Disclaimers
Portions Copyright © 2021 Synopsys, Inc. Used with permission. All rights reserved. Synopsys & DesignWare
are registered trademarks of Synopsys, Inc.
Legal Notice – Please Read
Alif Semiconductor™ reserves the right, without notice, to alter, edit, update, make corrections, and
improvements to Alif documentation and products at any time. It is the responsibility of customers to
maintain the most current versions of documentation before making any purchases from Alif. The
information found in this documentation is provided to purchasers solely for the purpose of enabling
hardware and software implementation of Alif products.
Alif neither takes any responsibility for, nor guarantees the appropriateness of, its products for a specific
purpose. Customers accept the responsibility for the selection and incorporation of Alif products into their
systems and Alif has no liability with respect thereto. ALIF ALSO DISCLAIMS ANY AND ALL LIABILITY WITH
RESPECT THERETO, INCLUDING WITHOUT LIMITATION, DIRECT, CONSEQUENTIAL, INDIRECT, SPECIAL AND
INCIDENTAL DAMAGES. ADDITIONALLY, ALIF DISCLAIMS AND EXCLUDES ALL WARRANTIES, WHETHER
STATUTORY, EXPRESS OR IMPLIED, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR
A PARTICULAR PURPOSE AND NON-INFRINGEMENT AND THOSE ARISING FROM COURSE OF DEALING AND
USAGE OF TRADE.
Alif Semiconductor and the Alif logo are trademarks of Alif. For more information about our trademarks,
please visit our website at https://alifsemi.com/legal/. The omission of any Alif trademark, product name or
any other name from this list does not constitute a waiver of Alif's intellectual property rights.
The recipient of this document does not have permission to copy, reprint, reproduce, duplicate, share, in any
form, in whole or in part, unless prior written consent from Alif is obtained.
Please contact an Alif representative at contact@alifsemi.com if you have any questions regarding the
information in this document.
Alif sells products according to standards terms and conditions of sales, which can be found at:
https://alifsemi.com/legal/
8.4 Trademarks
The Alif logo, Ensemble, and aiPM are trademarks of Alif Semiconductor. For additional information about
Alif Semiconductor trademarks, refer to https://alifsemi.com/legal/.
Arm, Cortex, CoreSight, TrustZone, AMBA, Thumb, and Ethos are registered trademarks or trademarks of
Arm Limited (or its subsidiaries) in the US and/or elsewhere.
Neon, and Helium are trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
Secure Digital and SD is a registered trademark of SD Card Association.
Synopsys & DesignWare are registered trademarks of Synopsys, Inc.
eMMC is trademarks of MultiMediaCard Association.
All other product or service names are the property of their respective owners.
8.5 Abbreviations
3GPP
3rd Generation Partnership Project
ACP
Accelerator Coherency Port
ADC
Analog to Digital Converter
AES
Advanced Encryption Standard
AHI
Application Host Interface
AI
Artificial Intelligence
aiPM
autonomous intelligent Power Management
AON
Always On
API
Application Programming Interface
APSS
Application Processor Subsystem
ATOC
Application Table of Content
BER
Bit-Error Ratio
BLE
Bluetooth Low Energy
BLIT
Block Image Transfers
BOD
Brown-Out Detect
BOR
Brown-Out Reset
BPU
Breakpoint Unit
CAN
Controller Area Network
CANFD
Controller Area Network with Flexible Data rate
CCC
Common Command Code
CDC
Configurable DPI Controller
CDM
Charged Device Model
CLUT
Color Look-Up Table
CMP
Comparator
CMSIS
Common Microcontroller Software Interface Standard
CNN
Convolutional Neural Network
CPI
Camera Parallel Interface
CPU
Central Processing Unit
CRC
Cyclic Redundancy Check
CSI
Camera Serial Interface
DAC
Digital to Analog Converter
DAP
Debug Access Port
DDR
Double Data Rate
DL
Display List / Download
DLR
Display List Reader
DM
Device Manufacturer
DMA
Direct Memory Access
DMAC
Direct Memory Access Controller
DMIC
Digital Microphone
DPA
Differential Power Analysis
DPI
Display Parallel Interface / Display Pixel Interface
DPU
Data Processing Unit
DRD
Dual-Role Device
DSC
Display Stream Compression
DSI
Display Serial Interface
DTCM
Data Tightly-Coupled Memory
DWT
Data Watchpoint and Trace
ECB
Electronic Codebook
ECC
Error-Correcting Code / Elliptic-Curve Cryptography
eDRX
Extended Discontinuous Reception
EMC
Electromagnetic Compatibility
EMFI
Electromagnetic Fault Injection
EMI
Electromagnetic Interference
EMS
Electromagnetic Susceptibility
EOL
End of Life
EoTp
End of Transmission Packet
EPU
Extension Processing Unit
ESD
Electrostatic Discharge
eSIM
Embedded Subscriber Identity Module
ETH
Ethernet
EVTRTR
Event Router
EWIC
External Wakeup Interrupt Controller
FC
Firewall Component
FIR
Finite Impulse Response
FSR
Full-Scale Range
GIC
Generic Interrupt Controller
GNSS
Global Navigation Satellite Subsystem
GOPS
Giga Operations Per Second
GPIO
General-Purpose Input/Output
GPS
Global Positioning System
GPU
Graphics Processing Unit
HBM
Human Body Model
HCI
Host Communication Interface
HDR
High Data Rate
HE
High Efficiency
HFRC
High-Frequency Resistor-Capacitor
HFXO
High-Frequency Crystal Oscillator
HMI
Human Machine Interface
HP
High Performance
HPP
High Performance Point
HUK
Hardware Unique Key
HWRM
Hardware Reference Manual
HWSEM
Hardware Semaphore
I2C
Inter-Integrated Circuit
I2S
Inter-IC Sound
I3C
Improved Inter-Integrated Circuit
IBI
In-Band Interrupt
ICMP
Internet Control Message Protocol
ICV
Integration Circuit Vendor
IDE
Integrated Design Environment
IFG
Interframe Gap
IFU
Instruction Fetch Unit
IIR
Infinite Impulse Response
IoT
Internet of Things
IPC
Inter-Process Communication
IPI
Image Pixel Interface
IRQRTR
Interrupt Router
iSIM
Integrated Subscriber Identity Module
ISP
In-System Programming
ITCM
Instruction Tightly-Coupled Memory
iUICC
integrated Universal Integrated Circuit Card
IWIC
Internal Wakeup Interrupt Controller
LCD
Liquid Crystal Display
LCS
Life Cycle State
LDE
Lockdown Extension
LDO
Low Drop-Out
LE
Low Energy
LFRC
Low-Frequency Resistor-Capacitor
LFXO
Low-Frequency Crystal Oscillator
LOM
Listen Only Mode
LP
Low-Power
LPCMP
Low-Power Comparator
LPGPIO
Low-Power General-Purpose Input/Output
LPI2C
Low-Power Inter-Integrated Circuit
LPI2S
Low-Power Inter-IC Sound
LPM
Link Power Management
LPP
Low Performance Point
LPPDM
Low-Power Pulse Density Modulation
LPRTC
Low-Power Real-Time Counter
LPSPI
Low-Power Serial Peripheral Interface
LPTIMER
Low-Power Timer
LSB
Least Significant Bit
LTE
Long-Term Evolution
LUT
Look-Up Table
MAC
Media Access Controller
MAU
Memory Authentication Unit
MBI
Master Bus Interface
MCU
Microcontroller Unit
ME
Monitor Extension
MHU
Message Handling Unit
ML
Machine Learning
MMU
Memory Management Unit
MPE
Master Permission Entry
MPU
Memory Protection Unit
MRAM
Magnetoresistive Random-Access Memory
MSL
Moisture Sensitivity Level
MTL
MAC Transaction Layer
MVE
M-profile Vector Extension
MWS
Mobile Wireless Standard
NMI
Non-Maskable Interrupt
NPP
Nominal Performance Point
NPU
Neural Processing Unit
NPU-HE
Neural Processing Unit-High Efficiency
NPU-HP
Neural Processing Unit-High Performance
NRZ
Non-Return-to-Zero
NS
Non-Secure
NVIC
Nested Vectored Interrupt Controller
NVM
Non-Volatile Memory
OCS
OEM-signed Configuration Settings
OEM
Original Equipment Manufacturer
OPP
Operating Performance Point
OSPI
Octal Serial Peripheral Interface
OToC
OEM-signed Table of Contents
OTP
One Time Programmable
PCM
Pulse Code Modulation
PD
Power Domain
PDM
Pulse Density Modulation
PE
Protection Extension
PLL
Phase-Locked Loop
PMU
Performance Monitoring Unit
POR
Power-On-Reset
PPI
PHY Protocol Interface / Private Peripheral Interrupt
PPS
Precise Positioning Service
PPU
Power Policy Unit
PSC
Power Sequence Controller
PSM
Power Saving Mode
PSRAM
Pseudo-Static Random-Access Memory
PSRR
Power Supply Rejection Ratio
PWM
Pulse Width Modulation
QEC
Quadrature Encoder Counter
RAI
Release Assistance Indication
RDC
Receiver Delay Compensation
RF
Radio Frequency
RFI
Radio Frequency Interference
RLE
Run-Length Encoding
RMA
Return Merchandise Authorization
RNN
Recurrent Neural Network
RO
Read Only
ROM
Read Only Memory
RoT
Root-of-Trust
RSA
Rivest–Shamir–Adleman
RSE
Region Size Extension
RSTC
Reset Controller
RTC
Real-Time Counter
RTOS
Real-Time Operating System
RTSS
Real-Time Subsystem
RW
Read/Write
SAR
Successive Approximation Register
SAU
Security Attribution Unit
SBI
Slave Bus Interface
SCU
Snoop Control Unit
SDA
Serial Data
SDIO
Secure Digital Input/Output
SDMMC
Secure Digital / Embedded Multimedia Card
SDR
Single Data Rate
SE
Secure Enclave / Secure Enable
SESS
Secure Enclave Subsystem
SFD
Start of Frame Data / Start Frame Delimiter
SGI
Software Generated Interrupt
SHA
Secure Hash Algorithm
SIM
Subscriber Identity Module
SIMD
Single Instruction Multiple Data
SJW
Synchronization Jump Width
SMP
Symmetric Multi-Processing
SNR
Signal-to-Noise Ratio
SPA
Simple Power Analysis
SPI
Serial Peripheral Interface / Shared Peripheral Interrupt
SRAM
Static Random-Access Memory
SSP
Synchronous Serial Protocol
SST
Single Shot Transmission
STB
Store Buffer
STOC
System Table of Content
SWD
Serial Wire Debug
SWRM
Software Reference Manual
TCM
Tightly-Coupled Memory
TCP
Transmission Control Protocol
TDC
Transmitter Delay Compensation
TE
Translation Extension
TEE
Trusted Execution Environment
TFT
Thin-Film-Translator
TGU
TCM Gate Unit
TOC
Table of Content
TRNG
True Random Number Generator
TSENS
Temperature Sensor
UART
Universal Asynchronous Receiver/Transmitter
UDE
Unprivileged Debug Extension
UDP
User Datagram Protocol
UI
Unit Interval / User Interface
UL
Upload
UPP
Ultra-Low Performance Point
USB
Universal Serial Bus
UTIMER
Universal Timer
VTOR
Vector Table Offset Register
WDT
Watchdog Timer
WFE
Wait For Event
WFI
Wait For Interrupt
XIP
eXecute-in-Place
XO
Execute Only
ZI
Zero Initialized
9 Revision History
Table 9-1 provides the history of changes to this document.
Table 9-1 Revision History
Date Revision Changes
Changes from previous revision include:
n Updated Section Features: On-Chip Application Memory, External Memory
Interfaces, Secure Enclave, Extreme-Low Power Technology, Serial Communication
Interfaces, Analog Interface Capabilities, Audio Interfaces, Clock Generation, and
Operating Parameters
n Updated Figure 2-1 Device Block Diagram
n Updated CPU revision in Section 3.2.1 M55-HP Overview
n Updated CPU revision in Section 3.2.2 M55-HE Overview
n Updated Section 3.7.4 Power Supply Supervisors
n Updated Section 3.8 Reset Management Overview
n Updated Section 3.9 Clock Generation and Control
n Updated MRAM read cache size in Section 3.12.1 MRAM Overview
n Updated Section 3.12.2 SRAM Overview
n Updated Section 3.12.4 External Memory Expansion Options
n Updated Section 3.15.1 LPTIMER Overview
n Updated Section 3.17.4 I2C Overview
n Updated Section 3.18.1 Cryptographic OSPI Overview
n Updated Section 3.19.1 CPI Overview
n Updated Section 3.21.1 ADC Overview
n Updated Section 3.21.2 DAC12 Overview
n Updated Section 3.21.3 CMP Overview
October 2023 2.5 n Updated Section 3.21.4 LPCMP Overview
n Added VDD_PLL_0V8 power supply on ball C25 on WLCSP208 package and ball A1
on FBGA194 package
n Removed SoC POR reset (VDD_POR)
n Updated power supplies naming - VDD_MIPI_0V8 to VREG_MIPI_0V8, VDD_3V3 to
VDD_MAIN, and VDD_BUCK_3V3 to VDD_BUCK accordingly
n Updated 4.1.1 WLCSP208 Package Pin Location Assignment
n Updated 4.1.2 FBGA194 Package Pin Location Assignment
n Updated CAUTION note in Section 4.2 Pin Function Options by Location
n Updated Table 4-1 Pin Function Options by Location
n Updated and moved Section 6.3 Storage Conditions under Section 6 Package
Information
n Updated Table 5-7 ESD Characteristics
n Updated OSPI, CPI, and LPCPI maximum supported frequencies in 5.1.2 Maximum
Performance Ratings
n Updated Table 5-4 General Operating Conditions
n Updated Table 5-5 Power Modes Case Definition
n Removed Section Supply Current Characteristics. Information is moved in Table 5-5
Power Modes Case Definition
n Removed Section Wake Up Times. Information is moved in Table 5-5 Power Modes
Case Definition
n Added values to Table 5-6 Reference Voltage Characteristics