Fully On Chip Areea Efficient LDO Voltaage Regulator

Suresh A 1, Sreehari Rao Patri 1, Debbasish Dwibedy 1, Sunilkumar Bhat 1, Gaurav K 1and
a Krishnaprasad KSR 1
1
Departmennt of Electronics and Communication Engineeringg,
National Institutee of Technology Warangal, Telangana - 506004, India.
I
E-mail: suresh_nitw@nnitw.ac.in, patri@nitw.ac.in, debasishdwibedy7@
@gmail.com,
sunilk.tsa@gmaill.com, gskabra1991@gmail.com and krish@nitw.ac.in.

Abstract— A novel full on-chip, area efficient low dropout linear Compensation circuitry in Secction V, Simulation Results and
O is designed with a
regulator is presented in this paper. This LDO conclusions are given in Sectionn VI and VII respectively.
recycling folded cascode error amplifier thaat offers very good
stability and a load regulation of 6.760μ μV/mA. A refined II. PROPOSED LDO DESCRIPTION
frequency compensation scheme is used whicch maintains LDO The conventional external capacitorless LDO structure is
stability over entire load current range i.e. 0-100mA and fast DO uses a large on chip capacitor
given in Fig.1. This type of LD
transient response without any necessity of outtput capacitor. The which consumes a large portionn of chip area.
overshoot/undershoot in the output voltage under
u the extreme
load transients are 195.3mV /71.7mV. The areea of the presented
LDO is greatly reduced due to removal of on-chip high output
capacitance. The area of presented LDO is only
o 0.05 mm2. The
LDO presented requires a bias current of 70μA and 200mV
dropout voltage and is designed in 180nm technnology.

Keywords—High slew rate, low-dropout regulator,

r recycling
folded cascode error amplifier, low-quiescent current.

I. INTRODUCTION
The rapid evolution of battery operated mobile
m devices has
driven the requirement for developmentt of low-voltage
integrated systems .Although supply voltagees are lowered, the Fig. 1. Conventional Low drop out Regulator
power consumption of modern systems arre not necessarily
low[1]. These systems consistently drive dynnamic loads which The purposed LDO regulattor constitutes error amplifier, a
are usually idle for most amount of timee but occasionally pass transistor, and feedback resistors, associated with the
require fast current pulses. These requiremennts are met with an compensation circuit is shownn in Fig. 2. The purposed LDO
efficient power management system utilizingg efficient and high does not have a on chip output capacitor.
c
performance voltage regulators consumingg little power to
conserve battery life.
The recent trend towards capacitor less LD DOs for system on
chip (SoC) leads to sufficient design challenges in terms of
stability and transient response. Since the on chip capacitor has
to be small, the regulator has to be compenssated internally. In
addition, since low on chip capacitance has limited
l capacity in
supplying and storing charge, the regulator facesf challenges in
responding quickly to fast transients. Goood load transient
response with small overshoots and underrshoots define the
overall accuracy of the regulator. In past, varrious strategies are
attempted for improving the power efficieency and transient
response of capacitor less LDO regulatoors. They include
procedures for modifying error amplifier to improve slew rate
[2], [3], [4], [5], [6], [7]or use suitable voltaage spike detection
circuits connected at the load for taking necessary action
against transient response improvement [11],[6],[7].However, Fig. 2. Proposed Loow drop out Regulator
they fall short of meeting the requiired performance
improvement(power efficiency)due to additiional circuitry and The error amplifier generaates error signal that drives the
current. Also the large onchip capacitor conssumes more silicon pass transistor to regulate the output.
o Pass transistor exhibits a
area which increases the cost. large parasitic capacitance at its
i input due to its large aspect
ratio for it drives large load current.
c The leading factors for
To attain efficient performance with loww area requirement, amplitude of the output voltagee spikes are: speed of the load
this paper presents a LDO with zero onchipp output capacitor, variations, load capacitance present
p at the output of LDO,
low quiescent current, high-gain and slew raate enhanced error loop bandwidth and loop phase margin. But the dominating
amplifier while meeting the required transiient response. The factor among them is the slew w rate at the gate of the pass
proposed LDO description is discussed in section
s II, transfer transistor [3], [5], [6], [7].
function is derived in Section III, error ampliifier in Section IV.

978-1-4799-4075-2/14/$31.00 ©2014 IEEE

 The novel approach in this design is that the external current conditions, distance between them is ensured.
capacitor which is usually considered in conventional capacitor
§ SC gd ·
less LDO is entirely removed and only the parasitic capacitor is − g mp R2 ¨1 − ¸
present at the output. Due to the absence of on chip capacitor, a ¨ g mp ¸
fast reacting path (differentiator) is utilized as compensation. A2 (S ) = © ¹ ……………….. (5)
§ ·
III. TRANSFER FUNCTION ¨1 + S ¸
¨ ω ¸
The open-loop transfer function of the proposed amplifier can © p2 ¹
be represented in block diagram as follows:
Where gmp is the pass transistor transconductance and R2 is
the output equivalent resistance.

g mf R1sRZ C f
A3 (S ) = ……..…………. ……….(6)
1+ sR1C g
Where RZ and Cf represents the differentiator as
compensation elements. The voltage drop derived from
capacitor current equation is given as,
I max Δt
ΔVout = …………………………… (7)
Fig. 3. Transfer function block diagram
Cout
Where Cout which represents parasitic capacitance at the
Here A1(s) constitute the error amplifier block; A2(s)
output node being less, contributes to the overshoot/undershoot
constitutes the pass transistor and feedback resistors while
at the output and needs to be reduced as it is detrimental to the
A3(s) constitutes the compensation circuitry.
performance of LDO.
(K + 1)g m1a R1
A1 (S ) = ……………………….…… (1) ΔI load = ΔVg g mp , Cg ΔVg = Cf eff ΔVout and
§ ·
¨1 + S ¸ Cf eff ΔVout
¨ ω ¸ ΔI load = g mp . For small ΔVout large Cfeff is
© p1 ¹ Cg
Where gm1a is the transconductance of input transistor, R1 is necessary.
the error amplifier output resistance,ɘp1 is the dominant pole
contribution.ɘp1 is given by Cf eff = C f g mf 1 g mf 2 RZ R1 ……………… (8)
1 Where Cf along with gmf1, gmf2 boost the feedback gain
ωp = resulting in higher equivalent capacitance thus compensating
1
R1 C1total
the loop (Large Cfeff ). The other factor responsible for ΔVout
C1total = C1 + C gspass + A pass C GD ……………….... (2)
to decrease is achieved by reducing the Δt factor in eq. 7. Δt
߱z due to Cgd of pass transistor is given by is the time taken by the loop to respond and is a function of
g mp loop bandwidth of error amplifier and t SR is the additional loop
ωZ = ………………………………………….. (3) delay caused due to slew rate at the gate of the pass transistor.
C gd
and as gmp is varied with load, the zero location in the 1
frequency response varies. Δt = + t SR ………………………… (9)
BW
߱p2 at the output is given by So thus the loop bandwidth of error amplifier has to be
1 large and large slew rate current for faster response, but the
ω p2 = tradeoff between slew rate and high power consumption has to
R2total C 2
be considered.
C 2 = C db + C gd
IV. ERROR AMPLIFIER
1 ……….(4)
R 2total = The error amplifier presented modifies the conventional
§ C gd § 1 ·· folded cascade (FC) error amplifier to achieve the better
R ds (R f 1 + R f 2 ) ¨ ¨ ¸¸
performance while consuming less power. The modification
¨ C1 + C gs + C gd ¨g ¸¸
© © mp ¹¹ recycles the bias current of idle transistors of conventional
folded cascode amplifier but still maintaining the performance.
ω p 2 varies with load transients, but due to the C2 being The conventional folded cascode error amplifier is shown in
much less will lie at higher frequency as compared to that of Fig. 2.The conventional folded cascode amplifier transistors
M3 and M4 have the largest transconductance for conducting
ω p1 . So, even if ω p 2 moves towards ω p1 during low load large current but their role for small signal current generated by
input transistors M1 and M2 is just as folding node.
 improvement in PSRR and load regulation. The slew rate factor
is also enhanced by k times and thus improves the charging and
discharging of pass transistor capacitor which reduces the
overshoot and undershoot at the output of regulator drastically.
The slew rate of proposed error amplifier is expressed as
2 KI B
SRRFC = …………..……………………… (11)
CL
The conventional error amplifier slew rate is denoted by
2I B
Fig. 4. Conventional Error Amplier (Folded Cascode) SRFC = ……………………. (12)
CL
Modified version of conventional (FC) amplifier is
Where IB represents the bias current that flows into the load
presented in Fig. 4.The input transistors M1 and M2 are split to
capacitor, which is equivalent capacitance at the gate of pass
carry equal currents although their internal capacitance remains
the same, the M3 and M4 maintain a current mirror ratio of k: transistor and is C1total = C1 + C gspass + Apass CGD .
1.The cross over connections is used so that the small signal
currents get added at the source of M5 and M6 are in phase. The choice of k plays a significant role in determining the
Transistors M11, M12 along with M5 and M6 is maintained the phase margin, which is a good indicator of transient response.
same aspect ratio to ensure the drain potentials of current To keep non dominant poles of transistor at least 3 times that of
mirrors are same for proper matching [9]. unity gain frequency k is usually selected to be lying between 2
and 4.
The small signal transconductance for the modified
topology is V. COMPENSATION CIRCUITRY
Fig. 5 shows the schematic of the proposed LDO regulator
GM = g m1a (1 + k ) ………………………… (10)
constituting pseudo differentiator as compensation circuit,
Thus gain bandwidth (GBW) is improved by a factor of 4 pMOS pass transistor (Mpass), the proposed recycling folded
for the value of k=3 used, for the same power, and thus speed cascode error amplifier.
is consequently increased. The basic idea of frequency compensation is to modify the
transfer function of the LDO in a way that stability and good
settling characteristics are achieved regardless of operating
conditions. The load environment of the LDO to be
designed is diverse, ranging roughly from 0mA to
maximum of 100mA of DC current. Such a wide range of
possible load currents causes the location of the output pole
to move extensively, which complicates the compensation.
A compensation circuit was needed for capacitor less-LDO
along with good transient response and stability for varied load
currents. A Fast transient path from the LDO output to the gate
of pass transistor is required for enhancing the transient
response of the LDO. The output voltage sampled by the Rz
and Cf acting as differentiator produce a voltage at the input of
Fig. 5. Proposed error amplifier (Recycling folded cascode) transistor M21.As input to M21 increases, so does the current
of M20 to increase, which further leads to discharge of parasitic
The increased rds2 and rds4 (M2 and M4 resistances) as a capacitance of pass transistor. This effect on the gate of pass
result of split operation performed on the input transistors transistor increases the load current through pass transistor to
conducts less current thus enhancing the gain. This gain increase, thus regulating the output. This push-pull activity is
enhancement further increases the loop gain which leads to the not only efficient for bias current but also for slew rate [8].

Fig. 6. Schematic of Low drop out Regulator

 VI. SIMULATION RESULTS
The proposed LDO regulator is simulated in the UMC
180nm CMOS process using cadence tool.
A. Transient Response
Fig 6.demonstrates the circuit transient response under load
current changes from 0mA to 100mA. The undershoot is
71.7mV and overshoot is 195.3mV. The load transient
response confirms that the proposed regulator is stable for
whole range of load currents.

Fig. 9. Simulated line regulation

D. PSSR (Power supply rejection ratio)

The PSRR is -29.65dB for frequencies up to 1 kHz and -
25.74dB at 100 kHz and is shown in Fig. 9.

Fig. 7. Simulated Transient response

B. Load Regulation
The load regulation is described by the following equation

ο௏೚ ோ೚ುಲೄೄ Fig. 10. Simulated PSRR Response
ൌ ଵା஺ ……………………………...(13)
οூ೚ ುಲೄೄ ఉ
E. Loop gain and phase response
Simulated value of the load regulation is: 6.79μV/mA at The overall stability of the system is defined by the loop
load current of 100mA as shown in Fig. 7. gain and its phase response and is as shown in Fig. 10.The
results shows that the system is stable for varied load current
changes.

Fig. 11. Simulated loop gain and phase response

F. Layout
Fig. 8. Simulated load regulation
The layout of the realized circuit is shown in figure 11.The
total area of the chip is about 140X370(μm) 2, where the 75%
C. Line Regulation of it is taken by the power MOS. From layout it can verified
The line regulation is the measure of the capability of the that no on chip output capacitor is used, only a feedback
LDO to maintain constant output voltage for the input voltage capacitor of 400fF is used.
change and is described by
Line regulation = ¨Vo/¨Vi
Simulated value of line regulation is represented in Fig. 8.
From the figure it can be verified the LDO has drop out range
of 200mV. The LDO switches from off state to on state in this
range.

Fig. 12. Layout of LDO

 In order to provide a clear picture of the performance value of on-chip capacitor, chip-area efficiency is thus greatly
improvement in the proposed LDO resulting from the proposed improved and multiple proposed LDO regulators can be
error amplifier, a comparison of some reported LDOs is given applied in chip-level power management. Moreover, the chip
in Table I. area of this design occupies 140X370(μm)2 of silicon area,
fully integrated and is much smaller than the published
VII. CONCLUSIONS designs of the state of art. Therefore, the proposed LDO is a
This paper presented a stable LDO voltage regulator suitable choice for SoC power management applications.
with a novel recycling folded cascode error amplifier structure This scheme addresses the problems of limited bandwidth
that enhances the gain, bandwidth and slew rate without and slew rate in the conventional LDO by applying a simple
increasing power or area consumption. The overshoot of the and effective modification to the conventional LDO circuit
LDO with the proposed circuit is 195.3mV for the current using recycling folded cascode amplifier.
change from 100 to 0mA and undershoot of 71.7mV, when the
output current changes from 0 to 100mA. The load regulation
is 6.79mV/A at 100mA. As regulator does not use any large
TABLE I. COMPARISON OF THE PROPOSED CAPACITOR-LESS LDO TOPOLOGY AGAINST THE STATE OF THE ART

[11] [8] [12] [1] [6] [13] This work

Year 2005 2007 2008 2010 2010 2011 2014
Tech.[μm] 0.09 0.35 0.35 0.35 0.35 0.35 0.18
VDrop[mV] 300 200 400 200 200 142 200
Conchip(pF) N/A 21 N/A 7 6 8 0.38
Cout(PF) 600 0-100 0 0-100 0-1000 0-100 0
IMax[mA] 100 50 50 100 100 100 0-100
IQ[μA] 6000 65 0.103 20 43 27 70
¨VOUT[mV] 90 90 320 97 70 25 71.7
Settling Time N.A 15 400 <9 3 N/A 1.9
Ts[μs]
Current 94 99.87 99.99 99.98 99.957 99.973 99.98
efficiency[%]
Area(࢓࢓૛ ሻ 0.098 0.120 0.096 0.145 0.155 0.2 0.05

SoC,”IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 5, pp. 1119–
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