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    Emmanuel Oppong Afriyie
    This document provides an overview of a computer organization and design course focusing on RISC-V. The course covers topics such as computer components, processor design, memory hierarchies, and performance improvement techniques through parallelism and pipelining. Students will learn about the hardware/software interface and how programs are executed from high-level code down to machine instructions. The course uses a RISC-V simulator for hands-on labs. It is taught using lectures and a textbook on computer organization and design based on the RISC-V architecture.

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    Chapter 0

    Uploaded by

    Emmanuel Oppong Afriyie
    21 views26 pages
    This document provides an overview of a computer organization and design course focusing on RISC-V. The course covers topics such as computer components, processor design, memory hierarchies, and performance improvement techniques through parallelism and pipelining. Students will learn about the hardware/software interface and how programs are executed from high-level code down to machine instructions. The course uses a RISC-V simulator for hands-on labs. It is taught using lectures and a textbook on computer organization and design based on the RISC-V architecture.

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    Computer Organization and Design RISC-V Edition: The Hardware Software Interface”

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    This document provides an overview of a computer organization and design course focusing on RISC-V. The course covers topics such as computer components, processor design, memory hierarchies, and performance improvement techniques through parallelism and pipelining. Students will learn about the hardware/software interface and how programs are executed from high-level code down to machine instructions. The course uses a RISC-V simulator for hands-on labs. It is taught using lectures and a textbook on computer organization and design based on the RISC-V architecture.

    Copyright:

    © All Rights Reserved
    21 views26 pages

    Chapter 0

    Uploaded by

    Emmanuel Oppong Afriyie
    This document provides an overview of a computer organization and design course focusing on RISC-V. The course covers topics such as computer components, processor design, memory hierarchies, and performance improvement techniques through parallelism and pipelining. Students will learn about the hardware/software interface and how programs are executed from high-level code down to machine instructions. The course uses a RISC-V simulator for hands-on labs. It is taught using lectures and a textbook on computer organization and design based on the RISC-V architecture.

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    of 26

    COMPUTER ORGANIZATION AND DESIGN RISC-V

    Edition
    The Hardware/Software Interface

    EECS2021E
    Computer Organization
    Amir Ashouri
    York University
    Fall 2019
    These slides are based on the slides by the authors.
    The slides doesn’t include all the material covered in the lecture.
    The slides will be explained, modified, and sometime corrected in
    the lecture.
    Course Staff
    Instructor:
    n Amir Ashouri (aashouri@eecs.yorku.ca)

    n Office Hours: Wednesdays (will be announced)


    n https://wiki.eecs.yorku.ca/course_archive/2019-20/F/2021E

    n TAs: (will be announced)


    n Main point of contact for your course labs
    n Lab Hours:
    LAB 01 (Mondays) 19:00-22:00 (YK LAS 1006)
    LAB 02 (Tuesdays) 19:00-22:00 (YK LAS 1006)
    Course Textbook

    n Required Textbook:

    n “Computer Organization and Design


    RISC-V Edition: The Hardware
    Software Interface”

    n (The Morgan Kaufmann Series in


    Computer Architecture and Design)
    n David A. Patterson & John L. Hennessy
    1st edition.
    Tentative Schedule
    Date Lecture Content Labs
    Sep 9 to 11 Chapter 1, Chapter 2 (2.1 - 2.4)
    1

    Sep 9 to 11 Chapter 2 (2.5 - 2.7)


    2

    Sep 16 to 20 Chapter 2 (2.8)


    Lab 1
    Sep 23 to 27 Chapter 2 (2.9 - 2.11)
    3 Lab 2
    Sep 30 to Oct 4 Chapter 2
    4 Lab 3

    Oct 7 to Oct 11 Chapter 3


    5 Lab 4

    6
    Oct 14 to Oct 18 Fall Reading Week - NO CLASSES
    Oct 21 to Oct 25 Chapter 3
    7 MidTerm
    Oct 28 to Nov 1 Chapter 3
    8 Lab 5

    Nov 4 to Nov 1 Chapter 3


    9 Lab 6
    10 Oct 28 to Nov 1 Chapter 3 Lab 7

    Oct 28 to Nov 1 Chapter 4


    11 Lab 8
    Apr 1 to Apr 5 Chapter 4
    12

    13 Apr 8 to Apr 12 Chapter 4


    Prerequisites
    n General Prerequisite

    n Basic Understanding of Programing

    n Labs (@ LAS 1006)


    n We will use York’s inhouse RISK-V simulator
    for our lab assignments
    RISK-V Simulator (1/2)
    RISK-V Simulator (2/2)
    Grade Composition

    n Lab 30%
    n Midterm 30%
    n Final 40%
    EECS2021E Course Description
    n Features RISC-V, the first such
    architecture designed to be used in
    modern computing environments, such as
    cloud computing, mobile devices, and
    other embedded systems
    n Includes relevant examples, exercises,
    and material highlighting the emergence of
    mobile computing and the cloud
    What You Will Learn
    n How programs are translated into the
    machine language
    n And how the hardware executes them
    n The hardware/software interface
    n What determines program performance
    n And how it can be improved
    n How hardware designers improve
    performance

    Chapter 1 — Computer Abstractions and Technology — 10


    §1.1 Introduction
    The Computer Revolution
    n Progress in computer technology
    n Underpinned by Moore’s Law
    n Makes novel applications feasible
    n Computers in automobiles
    n Cell phones
    n Human genome project
    n World Wide Web
    n Search Engines
    n Computers are pervasive

    Chapter 1 — Computer Abstractions and Technology — 11


    Classes of Computers
    n Supercomputers
    n High-end scientific and engineering
    calculations
    n Highest capability but represent a small
    fraction of the overall computer market

    n Embedded computers
    n Hidden as components of systems
    n Stringent power/performance/cost constraints

    Chapter 1 — Computer Abstractions and Technology — 12


    The PostPC Era

    Chapter 1 — Computer Abstractions and Technology — 13


    The PostPC Era
    n Personal Mobile Device (PMD)
    n Battery operated
    n Connects to the Internet
    n Hundreds of dollars
    n Smart phones, tablets, electronic glasses
    n Cloud computing
    n Warehouse Scale Computers (WSC)
    n Software as a Service (SaaS)
    n Portion of software run on a PMD and a
    portion run in the Cloud
    n Amazon and Google
    Chapter 1 — Computer Abstractions and Technology — 14
    Understanding Performance
    n Algorithm
    n Determines number of operations executed
    n Programming language, compiler, architecture
    n Determine number of machine instructions executed
    per operation
    n Processor and memory system
    n Determine how fast instructions are executed
    n I/O system (including OS)
    n Determines how fast I/O operations are executed

    Chapter 1 — Computer Abstractions and Technology — 15


    §1.2 Eight Great Ideas in Computer Architecture
    Eight Great Ideas
    n Design for Moore’s Law

    n Use abstraction to simplify design

    n Make the common case fast

    n Performance via parallelism

    n Performance via pipelining

    n Performance via prediction

    n Hierarchy of memories

    n Dependability via redundancy

    Chapter 1 — Computer Abstractions and Technology — 16


    §1.3 Below Your Program
    Below Your Program
    n Application software
    n Written in high-level language
    n System software
    n Compiler: translates HLL code to
    machine code
    n Operating System: service code
    n Handling input/output
    n Managing memory and storage
    n Scheduling tasks & sharing resources
    n Hardware
    n Processor, memory, I/O controllers

    Chapter 1 — Computer Abstractions and Technology — 17


    Levels of Program Code
    n High-level language
    n Level of abstraction closer
    to problem domain
    n Provides for productivity
    and portability
    n Assembly language
    n Textual representation of
    instructions
    n Hardware representation
    n Binary digits (bits)
    n Encoded instructions and
    data

    Chapter 1 — Computer Abstractions and Technology — 18


    §1.4 Under the Covers
    Components of a Computer
    The BIG Picture n Same components for
    all kinds of computer
    n Desktop, server,
    embedded
    n Input/output includes
    n User-interface devices
    n Display, keyboard, mouse
    n Storage devices
    n Hard disk, CD/DVD, flash
    n Network adapters
    n For communicating with
    other computers

    Chapter 1 — Computer Abstractions and Technology — 19


    Inside the Processor (CPU)
    n Datapath: performs operations on data
    n Control: sequences datapath, memory, ...
    n Cache memory
    n Small fast SRAM memory for immediate
    access to data

    Chapter 1 — Computer Abstractions and Technology — 20


    Abstractions
    The BIG Picture

    n Abstraction helps us deal with complexity


    n Hide lower-level detail
    n Instruction set architecture (ISA)
    n The hardware/software interface
    n Application binary interface
    n The ISA plus system software interface
    n Implementation
    n The details underlying and interface
    Chapter 1 — Computer Abstractions and Technology — 21
    §1.5 Technologies for Building Processors and Memory
    Technology Trends
    n Electronics
    technology
    continues to evolve
    n Increased capacity
    and performance
    n Reduced cost
    DRAM capacity

    Year Technology Relative performance/cost


    1951 Vacuum tube 1
    1965 Transistor 35
    1975 Integrated circuit (IC) 900
    1995 Very large scale IC (VLSI) 2,400,000
    2013 Ultra large scale IC 250,000,000,000

    Chapter 1 — Computer Abstractions and Technology — 22


    Semiconductor Technology
    n Silicon atoms: semiconductor
    n Add materials to transform properties:
    n Conductors N or P.
    n Switch Combine them to make switches.

    Chapter 1 — Computer Abstractions and Technology — 23


    Manufacturing ICs

    n Yield: proportion of working dies per wafer

    Chapter 1 — Computer Abstractions and Technology — 24


    Intel Core i7 Wafer

    n 300mm wafer, 280 chips, 32nm technology


    n Each chip is 20.7 x 10.5 mm
    Chapter 1 — Computer Abstractions and Technology — 25
    From Sand To Silicon
    https://www.youtube.com/watch?v=Q5paWn7bFg4

    Chapter 1 — Computer Abstractions and Technology — 26

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