Lab 3

Digital IC Synthesis (Manual) Fall 2021
LAB-3 (Tutorial)
LOGIC SYNTHESIS
Engineer. Ali Sabir
Engineer. Hamza Attique
Prof. Rashad M. Ramzan
Dr. Hassan Saif
Electrical Engineering Department

National University of Computer &
Emerging Sciences (FAST-NU)
Islamabad-44000, Pakistan
RFCS2, FAST-NU, ISB (http://isb.nu.edu.pk/rfcs2/index.htm) 1(10)

3.1 AIM
The aim of this lab is to synthesize your verilog HDL code by using cadence tool in order to generate netlist,
timing report and output report.
3.2 OBJECTIVE
After completing this lab, you will be able to:

• Understand the verilog code.
• Generet the script file.
• Learn the complete procedure to synthesize your verilog code and to generate their netlist.
• Understand the basic command that will be used for opening cadence and Genus.
3.3 Theory
3.3.1 Introduction
Synthesis will convert the HDL code into netlist code or circuit diagram. It conatin the complete details.
• How the design are interconnected ?
• How the input and output are interconnected ?
• How the low-level module are interconnected with respect to the technology?
Right there we are using the 65nm technology with repect to that the cells are mapped and how they are
interconnected at every nodes if your circuit is complex all these thing will be given with respect to the
technology in the technology file. You will always have the information about physical layout how the
circuit will be on the board. So all these things will be there that will be mapped, basically synthesize is that
so representing your code into hardware will having all these interconnection right.
3.4 SOFTWARE tools Requirement
Equipment:
Computer with Cadence tool having Genus.
3.5 Procedure:
Step: 1 Make folder by name of Digital Synthesis.
• Create the folder in home by name of digital synthesis.

• Write the Verilog code (e.g. ISE, Vivado, Cadence) check for syntax.
• Save the Verilog code by .v extension in digital synthesis folder.
I am writing my Verilog code by using cadence because I know my code is error free, you can use any
Verilog app(e.g. ISE, Vivado) where you can verify their functionality. For writing the Verilog code in
cadence you may follow the steps that is given below.
• First open the digital synthesis folder.
• Right click by your cursor new window will be open move your courser down and click on open
terminal another new window will be open and then write gedit a new blank window will be open

• Write your Verilog code there.
Here is the complete Verilog code for 32-bit 4 input MUX, Now save your code by .v extension (e.g.
MUX_32_bit.v). After saving the code, your code would be look like as shown in the given below window.

Step 2:
Before synthesis by using cadence -> genus you msut have three file in digital synthesis folder.
a) Library
b) Constraint
c) Script
Every technology have their own library, you must know on which technology you are working.
Generate the Script_novel.tcl file and save in the digital synthesis folder.
Follow the steps in order to generate the script file.
• Open the digital synthesis folder.
• Right click by your cursor new window will be open, move your courser down and click on open
terminal another new window will be open and then type gedit a new blank window will be open
include load_etc.tcl
#Utility scripts
set DESIGN MUX_32
set top_module MUX_32
set SYN_EFF medium
# effort of tool

set MAP_EFF medium

# effort for mapping
set_attribute lib_search_path /home/admin/Documents/Libraries_LIB
set_attribute library {/home/admin/Documents/NLDM/tcbn65gplus_200a/tcbn65gplustc.lib }
##Verilog##
read_hdl -v2001 {
MUX_32.v
}
elaborate $DESIGN # RTL TO BOOLEAN OPTIMIZATION
check_design $DESIGN -unresolved #Display unresolved issue

read_sdc constraint.sdc
# read the constraint file
set_attribute syn_generic_effort medium
# effort for synthesis
set_attribute syn_map_effort medium
# effort for mapping
set_attribute syn_opt_effort medium
# effort optimization
syn_generic $DESIGN
# generic mapping, syntehsis, standard cell optimization,
syn_map $DESIGN
syn_opt $DESIGN
write_sdc $DESIGN >> ./Outputs/${DESIGN}_map.sdc
report_timing -summary >> ./reports/${DESIGN}_timing.rpt
# Timing report folder
report qor -levels_of_logic >> ./reports/${DESIGN}_qor.rpt
# qor report
report area >> ./reports/${DESIGN}_area.rpt
# Area report
report gates >> ./reports/${DESIGN}_gates.rpt
# Gate Report
report power >> ./reports/${DESIGN}_power.rpt
# Power Report
report utilization > ./reports/${DESIGN}_utilization.rpt
write_hdl $DESIGN -mapped >> ./Netlist/${DESIGN}_map.v
# Netlist folder
This is your script file. At this stage you don’t need to make your own script file you just need to
understand the basic commands. In the post lab you can use the same script file by just changing the
from MUX_32_bit to XYZ. The given below window show the script file, now save the script file.

Step 3
Generate the constraint file.
• Generate constraint file allow us to constraint the tool as per the user requirement (e.g. If a user
wants to complete the design in designated area and power budget than constraint file will be used
to give the input to the tool so that it may constrain the as per user requirement)
• At this stage no need to make constrain file. We will do in the next lab.
Step 4
Open the cadence tool
• Right click by your cursor new window will be open, move your courser down and click on open
terminal another new window will be open and then type gedit a new blank window will be open
• Type: su => password: aqifhamza

• Eneter the given commands

➢ mount –a
➢ csh
➢ source /home/admin/Cadence_Works/cshrc # depend upon where your library is
placed
Step 4
Open the Genus by entering the given command.
➢ genus -legacy_ui

• Genus tool is be ready for the script file.\

• Before entering the command for script, check your script file is ready.
NETLIST
module Mux_32_bit(mux_out, data_3, data_2, data_1, data_0, enable,
select);
input [31:0] data_3, data_2, data_1, data_0;
input enable, select;
output [31:0] mux_out;
wire [31:0] data_3, data_2, data_1, data_0;
wire enable, select;
wire [31:0] mux_out;
wire n_0, n_1, n_2, n_3, n_4, n_5, n_6, n_7;
wire n_8, n_9, n_10, n_11, n_12, n_13, n_14, n_15;
wire n_16, n_17, n_18, n_19, n_20, n_21, n_22, n_23;
wire n_24, n_25, n_26, n_27, n_28, n_29, n_30, n_31;
wire n_32;
BUFTD0 g22__2398(.I (n_28), .OE (enable), .Z (mux_out[19]));
AO22D0 g858__8428(.A1 (n_30), .A2 (data_0[5]), .B1 (select), .B2
(data_1[5]), .Z (n_32));
(data_1[10]), .Z (n_31));
(data_1[11]), .Z (n_29));


(data_1[19]), .Z (n_28));
(data_1[29]), .Z (n_27));
(data_1[26]), .Z (n_26));
(data_1[17]), .Z (n_25));
(data_1[6]), .Z (n_24));
(data_1[2]), .Z (n_23));
(data_1[24]), .Z (n_22));
(data_1[20]), .Z (n_21));
(data_1[25]), .Z (n_20));
(data_1[1]), .Z (n_19));
(data_1[16]), .Z (n_18));
(data_1[0]), .Z (n_17));
(data_1[3]), .Z (n_16));
(data_1[28]), .Z (n_15));
(data_1[8]), .Z (n_14));
(data_1[15]), .Z (n_13));
(data_1[9]), .Z (n_12));
(data_1[30]), .Z (n_11));
(data_1[14]), .Z (n_10));
(data_1[18]), .Z (n_9));
(data_1[27]), .Z (n_8));
(data_1[13]), .Z (n_7));
(data_1[7]), .Z (n_6));
(data_1[4]), .Z (n_5));
(data_1[31]), .Z (n_4));
(data_1[22]), .Z (n_3));
(data_1[21]), .Z (n_2));

(data_1[12]), .Z (n_1));
(data_1[23]), .Z (n_0));
CKND0 g879(.I (select), .ZN (n_30));
Endmodule
ASSIGNMENT
Task 1: Write the Verilog code for given figure by using xillinx ISE show their waveform, Generate
their netlist, outputs and reports by using Genus tool.
Task 2: Write one detail paragraph on each report file that is shown in the given figure represented
by circle.
Task 3: Write the conclusion in your own word ?
RFCS2, FAST-NU, ISB (http://isb.nu.edu.pk/rfcs2/index.htm) 10(10

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Digital IC Synthesis (Manual) Fall 2021

Electrical Engineering Department

RFCS2, FAST-NU, ISB (http://isb.nu.edu.pk/rfcs2/index.htm) 1(10)

After completing this lab, you will be able to:

3.4 SOFTWARE tools Requirement

Step: 1 Make folder by name of Digital Synthesis.

• Create the folder in home by name of digital synthesis.

RFCS2, FAST-NU, ISB (http://isb.nu.edu.pk/rfcs2/index.htm) 2(10)

• Write your Verilog code there.

RFCS2, FAST-NU, ISB (http://isb.nu.edu.pk/rfcs2/index.htm) 3(10)

RFCS2, FAST-NU, ISB (http://isb.nu.edu.pk/rfcs2/index.htm) 4(10)

set MAP_EFF medium

check_design $DESIGN -unresolved #Display unresolved issue

RFCS2, FAST-NU, ISB (http://isb.nu.edu.pk/rfcs2/index.htm) 5(10)

RFCS2, FAST-NU, ISB (http://isb.nu.edu.pk/rfcs2/index.htm) 6(10)

• Eneter the given commands

RFCS2, FAST-NU, ISB (http://isb.nu.edu.pk/rfcs2/index.htm) 7(10)

• Genus tool is be ready for the script file.\

RFCS2, FAST-NU, ISB (http://isb.nu.edu.pk/rfcs2/index.htm) 8(10)

AO22D0 g855__3680(.A1 (n_30), .A2 (data_0[19]), .B1 (select), .B2

RFCS2, FAST-NU, ISB (http://isb.nu.edu.pk/rfcs2/index.htm) 9(10)

Task 3: Write the conclusion in your own word ?

RFCS2, FAST-NU, ISB (http://isb.nu.edu.pk/rfcs2/index.htm) 10(10

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