Tutorial 03 Latch FF State Machines 1
Tutorial 03 Latch FF State Machines 1
Tutorial 03 Latch FF State Machines 1
Tutorial 3
Michal Kubíček
Department of Radio Electronics, FEEC BUT Brno
Vytvořeno za podpory projektu OP VVV Moderní a otevřené studium techniky CZ.02.2.69/0.0/0.0/16_015/0002430.
Tutorial 3
page 2 kubicek@vutbr.cz
Latch and Flip-Flop in VHDL
page 3 kubicek@vutbr.cz
Digital system - sequential
pres_state
next_state outputs
inputs
next
out
state REG logic
logic clk
page 4 kubicek@vutbr.cz
Registers
pres_state
next_state outputs
inputs
next
out
state REG logic
logic clk
page 5 kubicek@vutbr.cz
Registers
LATCH
❑ LATCH = level sensitive D-type register
❑ Whenever the CLK input is in active state, signal from the D input is
forwarded to the Q output (including any glitches)
❑ The data on the D input must be stable around falling edge of the CLK
signal so that there is no metastable state.
CLK D Q
D CLK
page 6 kubicek@vutbr.cz
Registers
LATCH
❑ The main problem: formation of combinatorial loop
The D input is connected to the Q output whenever the clock signal (CLK) is in active state. In the
example below this results in connection a combinatorial loopback. If the duration of active level of CLK
signal is longer, than delay of the loopback, oscillations can be observed (the system effectively forms a
ring oscillator).
A=Q A Y
D Q
B B
CLK
CLK
Y=D Y=!(A∙B)
page 7 kubicek@vutbr.cz
Registers
LATCH counter
❑ VHDL inference
PROCESS (clk) BEGIN
counter + 1
IF clk = '1' THEN
counter <= counter + 1;
END IF; +1 Latch
END PROCESS; clk
page 8 kubicek@vutbr.cz
Registers
LATCH counter
❑ VHDL inference
PROCESS (clk) BEGIN
counter + 1
IF clk = '1' THEN
counter <= counter + 1;
END IF; +1 Latch
END PROCESS; clk
clk
counter+1 2 3 4 5 6
❑ VHDL inference
PROCESS (counter) BEGIN
counter + 1
counter <= counter + 1;
END PROCESS;
+1
! WARNING:Xst:2170 - Unit Top : the following signal(s) form a combinatorial loop: Madd_counter_cy<0>.
! WARNING:Xst:2170 - Unit Top : the following signal(s) form a combinatorial loop: Madd_counter_lut<5>.
! WARNING:Xst:2170 - Unit Top : the following signal(s) form a combinatorial loop: Madd_counter_lut<3>.
! WARNING:Xst:2170 - Unit Top : the following signal(s) form a combinatorial loop: Madd_counter_lut<1>.
! WARNING:Xst:2170 - Unit Top : the following signal(s) form a combinatorial loop: Madd_counter_lut<6>.
! WARNING:Xst:2170 - Unit Top : the following signal(s) form a combinatorial loop: Madd_counter_lut<7>.
! WARNING:Xst:2170 - Unit Top : the following signal(s) form a combinatorial loop: Madd_counter_lut<2>.
! WARNING:Xst:2170 - Unit Top : the following signal(s) form a combinatorial loop: Madd_counter_lut<4>.
page 10 kubicek@vutbr.cz
Registers
Combinatorial loop
page 11 kubicek@vutbr.cz
Registers
Combinatorial loop
1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis
may not be accurate. The preferred resolution is to modify the design to remove
combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed
by acknowledging the condition and setting the following XDC constraint on any one of
the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets ]'.
One net in the loop is data_out_OBUF[0]. Please evaluate your design. The cells in the
loop are: data_out_OBUF[0]_inst_i_1.
page 12 kubicek@vutbr.cz
Registers
Combinatorial loop counter
ERROR: at 100 ns(10000): Iteration limit 10000 is reached. Possible zero delay
oscillation detected where simulation can not advance in time because signals
can not resolve to a stable value in File
"D:/Project/ISE/MPLD/2016/CV_02/S3E_ALU/SOURCES/comb_loop_test.vhd" Line 19.
Please correct this code in order to advance past the current simulation time.
page 13 kubicek@vutbr.cz
...and if all latches and combinatorial loops have not been removed,
your faith is worthless; you are still in your sins.
Registers
Flip-Flop
❑ D-type edge sensitive register = D-type Flip-Flop
❑ The signal from D input is transferred to the Q output at every active
clock edge (usually rising edge is considered), no glitches can propagate
through Flip-Flop
❑ The input signal (D) must be stable shortly before and shortly after the
active clock edge (setup/hold time requirement)
CLK D Q
D CLK
page 15 kubicek@vutbr.cz
Registers
Flip-Flop
❑ Effectively eliminates problem of a combinatorial loopback
The D input is "connected" to the Q output only for a very short time. This time is negligible compared to
a typical delay of any loopback path.
A=Q
B A Y
D Q
B
CLK CLK
Y=D
page 16 kubicek@vutbr.cz
Registers
Flip-Flop counter
❑ VHDL inference
PROCESS (clk) BEGIN
counter + 1
IF rising_edge(clk) THEN
counter <= counter + 1; D Q
END IF; +1
END PROCESS; clk CLK
counter 1 2
clk
counter+1 2 3
page 17 kubicek@vutbr.cz
Registers
page 18 kubicek@vutbr.cz
Registers
❑ In FPGAs there are registers that can be either set to Flip-Flop or LATCH
function. But using this register as a LATCH saves no resources ➔ no
benefit. Many modern FPGAs feature registers with Flip-Flop function only.
page 19 kubicek@vutbr.cz
Registers
page 20 kubicek@vutbr.cz
Registers
page 21 kubicek@vutbr.cz
Registers
page 22 kubicek@vutbr.cz
Registers
page 23 kubicek@vutbr.cz
Registers
page 24 kubicek@vutbr.cz
Registers
page 25 kubicek@vutbr.cz
Registers
page 26 kubicek@vutbr.cz
Registers
page 29 kubicek@vutbr.cz
Finite State Machines (FSM)
page 30 kubicek@vutbr.cz
Finite State Machines
S0
S1
S2
page 31 kubicek@vutbr.cz
Finite State Machines
page 32 kubicek@vutbr.cz
Finite State Machines
page 33 kubicek@vutbr.cz
Finite State Machines
9:00 Outputs
controlling
home systems
9:01
next
out
state REG logic
logic clk
rst
Time
adjustment 5:30-7:30 22°C windows obscured
7:30-15:00 18°C
17:00-19:00 23°C
19:00-22:00 23°C windows obscured
22:00-5:30 17°C windows obscured
This FSM is perfectly suitable for software
realization as the reaction time is not critical.
page 34 kubicek@vutbr.cz
State machines in FPGAs: examples
page 35 kubicek@vutbr.cz
FPGA-based FSM: real use
Video controller
Resolution 1920 x 1050, 60Hz:
page 36 kubicek@vutbr.cz
FPGA-based FSM: real use
page 37 kubicek@vutbr.cz
FPGA-based FSM: real use
page 38 kubicek@vutbr.cz
FPGA-based FSM: real use
page 39 kubicek@vutbr.cz
FPGA-based FSM: real use
10011100101111100011100101100101010111
0101111100 ≠ K28.5
10011100101111100011100101100101010111
0101111100 ≠ K28.5
10011100101111100011100101100101010111
0101111100 = K28.5
10011100101111100011100101100101010111
11110000 10010110
page 40 kubicek@vutbr.cz
FPGA-based FSM: real use
Another applications
❑ DMA controller
❑ Bus arbiters
❑ Encoders and decoders (RS, LDPC, H.264...)
❑ Different levels of standard protocols (Ethernet MAC...)
page 41 kubicek@vutbr.cz
Description of FSM functionality
page 42 kubicek@vutbr.cz
FSM description
page 43 kubicek@vutbr.cz
FSM description
Sate diagrams
page 44 kubicek@vutbr.cz
FSM description
page 45 kubicek@vutbr.cz
FSM description
page 47 kubicek@vutbr.cz
Finite State Machines
pres_state
inputs
next
out
state REG REG
logic clk logic clk
page 48 kubicek@vutbr.cz
Finite State Machines
State register
The state register stores information about current FSM state. Its minimum
required size (number of bits) is given N = log2(M), where M is number of
working (valid, intended) states of the FSM.
N = ceil(log2(M))
0 1 2 ... 14 15
pres_state
4b binary counter:
16 states ➔ minimum size of
next_state outputs
the state register is
N = ceil(log2(16)) = 4
+1 REG
clk
page 49 kubicek@vutbr.cz
Finite State Machines
State register
The state register stores information about current FSM state. Its minimum
required size (number of bits) is given N = log2(M), where M is number of
working (valid, intended) states of the FSM.
N = ceil(log2(M))
0 1 2 ... 8 9
pres_state
page 50 kubicek@vutbr.cz
Finite State Machines
State register
In FPGA use always edge triggered D-type register = Flip-Flop
Other technologies:
soucasny_stav
❑ D, DE registers
❑ T, TE registers pristi_stav vystup
❑ J-K...
+1 REG
clk
Without tight timing control it is not possible to use LATCH (combinatorial loopback
may infer).
page 51 kubicek@vutbr.cz
Finite State Machines
counter 1 2 3 4 5
+1 Latch
clk
clk
counter+1 2 3 4 5 6
page 52 kubicek@vutbr.cz
Finite State Machines
D Q
counter 1 2
+1
clk CLK
clk
counter+1 2 3
page 53 kubicek@vutbr.cz
Finite State Machines
STD_LOGIC_VECTOR(n-1 DOWNTO 0)
Minimum number of bits N required for the state signal for M-state FSM is
N = ceil(log2(M))
FSM with 10 states (M=10) requires at least N=4 bit register (vector) for state register.
page 54 kubicek@vutbr.cz
Finite State Machines
page 55 kubicek@vutbr.cz
Finite State Machines
page 56 kubicek@vutbr.cz
Finite State Machines
page 57 kubicek@vutbr.cz
Finite State Machines
page 58 kubicek@vutbr.cz
Finite State Machines
page 59 kubicek@vutbr.cz
Finite State Machines
page 60 kubicek@vutbr.cz
Finite State Machines
...
page 61 kubicek@vutbr.cz
Finite State Machines
...
page 62 kubicek@vutbr.cz
Finite State Machines
page 63 kubicek@vutbr.cz
Finite State Machines
------------------------------------------------------------------
ARCHITECTURE Behavioral OF UART_FSM IS
------------------------------------------------------------------
BEGIN
...
page 64 kubicek@vutbr.cz
Binary counter:
FMS-style description
page 65 kubicek@vutbr.cz
Finite State Machines
Binary counter
4-bit counter: 2N = 16 states (0 to (2N – 1) = 15)
State diagram (free-running counter)
0 1 2 ... 14 15
BIN
clk
page 66 kubicek@vutbr.cz
Finite State Machines
For state description a custom data type t_state is used. This data type
will be converted to a STD_LOGIC_VECTOR during the synthesis. Number of
bits (length of the vector) will be set according to the selected sate encoding.
page 67 kubicek@vutbr.cz
Finite State Machines
pres_state
next_state outputs
inputs
next
out
state REG
page 69 kubicek@vutbr.cz logic clk
logic
Finite State Machines
BEGIN
pres_state
next_state outputs
inputs
next
out
state REG
page 70 kubicek@vutbr.cz logic clk
logic
Finite State Machines
Note the same results for FSM with Sequential encoding and the counter style description.
The encoding can be selected directly in the VHDL code (for each state machine independently):
page 71 kubicek@vutbr.cz
Finite State Machines
In most cases the implemented system (state machine) required a more or less complex output
logic stage which translates current state to the corresponding output number. Only for sequential
encoded FSM and for Counter style this output logic decode was effectively only an interconnection
(no actual logic gates).
pres_state
next_state outputs
inputs
next
out
state REG
page 72 kubicek@vutbr.cz logic clk
logic
Moore and Mealy FSM
page 73 kubicek@vutbr.cz
Finite State Machines
Moore Mealy
page 74 kubicek@vutbr.cz
Finite State Machines
Moore FSM
pres_state
next_state outputs
inputs
next
out
state REG logic
logic clk
page 75 kubicek@vutbr.cz
Finite State Machines
pres_state
inputs
next
out
state REG logic
REG
logic clk clk
page 76 kubicek@vutbr.cz
Finite State Machines
Mealy FSM
pres_state
next_state outputs
inputs
next
out
state REG logic
logic clk
page 77 kubicek@vutbr.cz
Finite State Machines
pres_state
inputs
next
out
state REG logic
REG
logic clk clk
page 78 kubicek@vutbr.cz
Finite State Machines
pres_state
next_state outputs
inputs
next
state REG
logic clk
page 79 kubicek@vutbr.cz
Finite State Machines
page 80 kubicek@vutbr.cz
Than you for your attention !
page 81 kubicek@vutbr.cz