Counter

Nama : Filosofi Dwibakti

Kelas : 1 D4 Teknik Komputer A
NRP : 2210191006
Dosen : Reni Soelistijorini
Matkul : Rangkaian Logika
Tgl Praktikum : 11 Mei 2020
ClockDevider
a. Program VHDL
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Clockdiv is
port (Clk25Mhz: in STD_LOGIC;
Clk: out STD_LOGIC
);
end Clockdiv;

architecture Behavioral of Clockdiv is

constant max: integer := 25000000;
constant half : integer := max/2;
signal count : integer range 0 to max;

begin
process
begin
wait until Clk25Mhz' EVENT and Clk25Mhz = '1' ;
if count < max then count <= count + 1;
else count <= 0;
end if;
if count < half then Clk <= '0' ;
else Clk <= '1' ;
end if;
end process;
end Behavioral;
b. RTL Schematics

c. Technology Schematics
Counter
a. Program VHDL
- Clkdiv
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity clkdiv is
Port (mclk : in STD_LOGIC;
clr : in STD_LOGIC;
clk190 : out STD_LOGIC;
clk48 : out STD_LOGIC
);
end clkdiv;

architecture Behavioral of clkdiv is

signal q : std_logic_vector(23 downto 0);
begin
process (mclk,clr)
begin
if clr = '1' then q <= x"000000";
elsif mclk' event and mclk = '1' then
q <= q + 1;
end if;
clk48 <= q(19);
clk190 <= q(17);
end process;
end Behavioral;

- Mod10kcnt
Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity mod10kcnt is
Port (clr: in STD_LOGIC;
clk: in STD_LOGIC;
q : out STD_LOGIC_VECTOR(13 downto 0)
 );
end mod10kcnt;

architecture Behavioral of mod10kcnt is

signal count :STD_LOGIC_VECTOR(13 downto 0);
begin
process(clk,clr)
begin
if clr = '1' then
count <= (others => '0');
elsif clk' event and clk = '1' then
if conv_integer(count) = 9999 then
count <= (others => '0' );
else count <= count + 1;
end if; end if;
end process;
q <= count;
end Behavioral;

- binBCD14
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity binBCD14 is
Port (b : in STD_LOGIC_VECTOR(13 downto 0);
p : out STD_LOGIC_VECTOR (16 downto 0)
);
end binBCD14;

architecture Behavioral of binBCD14 is

begin
process(b)
variable z : STD_LOGIC_VECTOR (32 downto 0);
begin
for i in 0 to 32 loop z(i) := '0';
end loop;
z(16 downto 3) := b;
 for i in 0 to 10 loop
if z(17 downto 14) > 4 then
z(17 downto 14) := z(17 downto 14) + 3;
end if;
if z(21 downto 18) > 4 then
z(21 downto 18) := z(21 downto 18) + 3;
end if;
if z(25 downto 22) > 4 then
z(25 downto 22) := z(25 downto 22) + 3;
end if;
if z(29 downto 26) > 4 then
z(29 downto 26) := z(29 downto 26) + 3;
end if;
z(32 downto 1) := z(31 downto 0);
end loop;
p <= z(30 downto 14);
end process;
end Behavioral;

- x7segbc
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;

entity x7segbc is
port (x : in std_logic_vector(15 downto 0);
cclk : in std_logic;
clr : in std_logic;
a_to_g : out std_logic_vector(6 downto 0);
an : out std_logic_vector(3 downto 0);
dp : out std_logic );
end x7segbc;

architecture Behavioral of x7segbc is

signal s : std_logic_vector(1 downto 0);
signal digit : std_logic_vector(3 downto 0);
signal aen : std_logic_vector(3 downto 0);
begin
 dp <= '1' ;
aen(3) <= x(15) or x(14) or x(13) or x(12);
aen(2) <= x(15) or x(14) or x(13) or x(12) or x(11) or
x(10) or x(9) or x(8);
aen(1) <= x(15) or x(14) or x(13) or x(12) or x(11) or
x(10) or x(9) or x(8) or x(7) or x(6) or x(5) or x(4);
aen(0) <= '1' ;

process(s,x)
begin
case s is
when "00" => digit <= x(3 downto 0);
when "01" => digit <= x(7 downto 4);
when "10" => digit <= x(11 downto 8);
when others => digit <= x(15 downto 12);
end case;
end process;

process(digit)
begin
case digit is
when x"0" => a_to_g <= "0000001";
when x"1" => a_to_g <= "1001111";
when x"2" => a_to_g <= "0010010";
when x"3" => a_to_g <= "0000110";
when x"4" => a_to_g <= "1001100";
when x"5" => a_to_g <= "0100100";
when x"6" => a_to_g <= "0100000";
when x"7" => a_to_g <= "0001111";
when x"8" => a_to_g <= "0000000";
when x"9" => a_to_g <= "0000100";
when x"A" => a_to_g <= "0001000";
when x"B" => a_to_g <= "1100000";
when x"C" => a_to_g <= "0110001";
when x"D" => a_to_g <= "1000010";
when x"E" => a_to_g <= "0110000";
when others => a_to_g <= "0111000";
end case;
 end process;

process(s,aen)
begin
an <= "1111";
if aen(conv_integer(s))= '1' then
an(conv_integer(s))<= '0' ;
end if;
end process;

process(cclk,clr)
begin
if clr= '1' then s <= "00";
elsif cclk' event and cclk= '1' then
s <= s + 1;
end if;
end process;
end Behavioral ;

- mod10kcnt_top
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mod10kcnt_top is
port( mclk : in std_logic;
btn : in std_logic;
a_to_g : out std_logic_vector(6 downto 0);
an : out std_logic_vector(3 downto 0);
dp : out std_logic
);
end mod10kcnt_top;

architecture Behavioral of mod10kcnt_top is

component clkdiv is
port (mclk : in std_logic;
clr : in std_logic;
clk190: out std_logic;
clk48: out std_logic
 );
end component;

component mod10kcnt is
port (clr : in STD_LOGIC;
clk : in STD_LOGIC;
q : out STD_LOGIC_VECTOR(13 downto 0)
);
end component;

component binBCD14 is
port (b : in STD_LOGIC_VECTOR(13 downto 0);
p : out STD_LOGIC_VECTOR(16 downto 0)
);
end component;

component x7segbc is
port (x : in std_logic_vector(15 downto 0);
cclk : in std_logic;
clr : in std_logic;
a_to_g : out std_logic_vector(6 downto 0);
an : out std_logic_vector(3 downto 0);
dp : out std_logic
);
end component;

signal b : std_logic_vector(13 downto 0);

signal p : std_logic_vector(16 downto 0);
signal clr, clk48, clk190 : std_logic;

begin
clr <= btn;
u1: clkdiv port map(
mclk => mclk,
clr => clr,
clk190 => clk190,
clk48 => clk48
);
 u2: mod10kcnt port map(
clr => clr,
clk => clk48,
q => b
);

u3: binbcd14 port map(

b => b,
p => p
);

u4: x7segbc port map(

x => p(15 downto 0),
cclk => clk190,
clr => clr,
a_to_g => a_to_g,
an => an,
dp => dp
);

end Behavioral;
b. RTL Schematics
- Clkdiv

- Mod10kcnt
- BinBCD14
- X7segbc
- Mod10kcnt_top
Tugas Stopwatch
a. Program VHDL
- 2bit Counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity twobitcounter is
Port (clk : in STD_LOGIC;
count_out : out STD_LOGIC_vector(1 downto 0));
end twobitcounter;
architecture Behavioral of twobitcounter is
signal sig1,sig2 : std_logic;
signal count_out_sig : std_logic_vector (1 downto 0);
begin
process (clk)
begin
if clk'event and clk = '1' then
count_out_sig(0) <= sig1;
count_out_sig(1) <= sig2;
end if;
end process;
sig1 <= not count_out_sig(0);
sig2 <= count_out_sig(1) xor count_out_sig(0);
count_out <= count_out_sig;
end Behavioral;

- 16bit Counter
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;

entity sixteen_bit_countr is
Port (CEn, CLK : in STD_LOGIC;
RST : in STD_LOGIC;
OUTPUT0 : out STD_LOGIC_VECTOR (3 downto
0);
 OUTPUT1 : out STD_LOGIC_VECTOR (3 downto
0);
OUTPUT2 : out STD_LOGIC_VECTOR (3 downto
0);
OUTPUT3 : out STD_LOGIC_VECTOR (3 downto
0));
end sixteen_bit_countr;

architecture Behavioral of sixteen_bit_countr is

signal s_cnt_tenths,s_cnt_ones,s_cnt_tens,s_cnt_hundos :
std_logic_vector(3 downto 0):="0000";
begin
process(Cen, RSt,CLK)
begin
if (RST = '1' and (CEn='1' or CEn='0')) then
s_cnt_tenths <= (others=> '0');
s_cnt_ones <= (others=> '0');
s_cnt_tens <= (others=> '0');
s_cnt_hundos <= (others=> '0');
ELSif (CEn = '1' and rising_edge(CLK)) then
if s_cnt_tenths="1001" then
s_cnt_tenths<="0000";
if s_cnt_ones="1001" then
s_cnt_ones <="0000";
if s_cnt_tens = "1001" then
s_cnt_tens <="0000";
if s_cnt_hundos ="1001" then
s_cnt_hundos<="0000";
else s_cnt_hundos <= s_cnt_hundos+1;end if;
else s_cnt_tens <= s_cnt_tens +1; end if;
else s_cnt_ones <= s_cnt_ones +1; end if;
else s_cnt_tenths <= s_cnt_tenths+1; end if;
end if;
end process;

output0<=s_cnt_tenths;
output1<=s_cnt_ones;
output2<=s_cnt_tens;
 output3<=s_cnt_hundos;

end Behavioral;

- 7-Segment Decoder
Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sev_seg_decoder is
Port (binary_num : in STD_LOGIC_VECTOR (3 downto 0);
ABCDEFG : out STD_LOGIC_VECTOR (6 downto
0));
end sev_seg_decoder;

architecture Behavioral of sev_seg_decoder is

begin
process(binary_num)
begin
case binary_num is
when "0000" => ABCDEFG <="0000001";
when "0001" => ABCDEFG <="1001111";
when "0010" => ABCDEFG <="0010010";
when "0011" => ABCDEFG <="0000110";
when "0100" => ABCDEFG <="1001100";
when "0101" => ABCDEFG <="0100100";
when "0110" => ABCDEFG <="1100000";
when "0111" => ABCDEFG <="0001111";
when "1000" => ABCDEFG <="0000000";
when "1001" => ABCDEFG <="0001100";
when others => ABCDEFG <="0111000";
END CASE;
END PROCESS;
end Behavioral;

- Multiplexer 4 to 1
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity four_to_one_mux is
Port (x0,x1,x2,x3 : in STD_LOGIC_VECTOR (6 downto 0);
 sr : in STD_LOGIC_VECTOR (1 downto 0);
f : out STD_LOGIC_vector(6 downto 0));
end four_to_one_mux;

architecture Behavioral of four_to_one_mux is

begin
f<= x3 when (sr="11") else
x2 when (sr="10") else
x1 when (sr="01") else
x0 when (sr="00") else
"0000000";
end Behavioral;

- Stopwatch
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Stopwatch is
Port ( start_stop : in STD_LOGIC;
reset : in STD_LOGIC;
clk_in : in STD_LOGIC;
DISP0 : out STD_LOGIC_VECTOR (6 downto 0);
AN : out STD_LOGIC_VECTOR (3 downto 0);
dp : out std_logic ); end Stopwatch;

architecture Behavioral of Stopwatch is

component four_bit_countr
port (CEn, CLK : in STD_LOGIC;
RST : in STD_LOGIC;
OUTPUT0,OUTPUT1,OUTPUT2,OUTPUT3 : out
STD_LOGIC_VECTOR (3 downto 0)
);
end component;

component sev_seg_decoder
port (binary_num : in std_logic_vector(3 downto 0);
ABCDEFG :out std_logic_vector(6 downto 0));
end component;
component twobitcounter
port (clk : in STD_LOGIC;
count_out : out STD_LOGIC_vector(1 downto 0));
end component;

component four_to_one_mux
port (x0,x1,x2,x3 : in std_logic_vector(6 downto 0);
sr : in STD_LOGIC_VECTOR (1 downto 0);
f : out STD_LOGIC_vector(6 downto 0));
end component;

SIGNAL TEMP,TEMP2 : STD_LOGIC;

signal counter,counter2 : integer range 0 to 11000000 := 0;
signal s_0, s_1, s_2,s_3: std_logic_vector(6 downto 0) :="0000000";
signal SR : STD_LOGIC_VECTOR(1 DOWNTO 0);
signal bin0,bin1,bin2,bin3 : std_logic_vector(3 downto 0);
begin
frequency_divider: process (clk_in) begin--250 Hz clock divider
if rising_edge(clk_in) then
if (counter = 200000) then
temp <= NOT(temp);
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;

frequency_divider2: process (clk_in) begin--clock divider for

cycling through digits
if rising_edge(clk_in) then
if (counter2 = 5000000) then
temp2 <= NOT(temp2);
counter2 <= 0;
else
counter2 <= counter2 + 1;
end if;
 end if;
end process;

COMB: PROCESS(SR)--process to cycle through anodes

BEGIN
CASE SR IS
WHEN "00" =>
AN<="1110";dp<='1';
WHEN "01" =>
AN<="1101";dp<='0';--engage decimal point
WHEN "10" =>
AN<="1011";dp<='1';
WHEN "11" =>
AN<="0111";dp<='1';
when others =>
AN<="1111";
END CASE;
END PROCESS COMB;

COUNTER2BIT : twobitcounter
port map (clk => temp,
count_out=>SR);

COUNTER4BIT0 : four_bit_countr
port map (clk => temp2,
OUTPUT0=>bin0,
OUTPUT1=>bin1,
OUTPUT2=>bin2,
OUTPUT3=>bin3,
CEn => start_stop,
RST => RESET
);

decode0 : sev_seg_decoder
port map (binary_num => bin0,
ABCDEFG => S_0
);
decode1 : sev_seg_decoder
port map (binary_num => bin1,
ABCDEFG => S_1
);

decode2 : sev_seg_decoder
port map (binary_num => bin2,
ABCDEFG => S_2
);

decode3 : sev_seg_decoder
port map (binary_num => bin3,
ABCDEFG => S_3
);

mux : four_to_one_mux
port map (x0 => S_0,
x1 => S_1,
x2 => s_2,
x3 => s_3,
f => DISP0,
sr =>SR
);
end Behavioral;
b. RTL Schematics
c. Technology Schematics