t Qvestions IQ.

IMPORTANT QUESTIONNS

UNIT-I
T QUESTIONS

(Refer Unit-, 02)

+AB'C'+AB'C'= C"
Prove that ABC'* ABC'
function into other canonical form.
Convert the given (Refer Unit-1, 04)
+ b'c + ac
Fa, b. c)= a'b
(Refer Unit-1, Q8)
postulates.
List the Huntington (Refer Unit-I, Q13)
mintems and maxterms.
Define (Refer Unit-I, Q17)
implicant and essential prime implicants. Give an example.
Define prime (Refer Unit-4. Q18)
the tabulation method is reduction prime implicants chart.
Explain
BAY QUESTIONS (Refer Unit-. 021)
about digital hardware.
Briefly explain (Refer UnitL Q24)
variables and functions in logic circuits.
Explain briefly about the (Refer Uni-I. Q28)
and theorems of Boolean algebra.
State and explain the postulates (Refer Unit-1. Q31)
circuits.
control with help of logic
C0. Design a three-way light difference
of k-map method and give the (Refer Unit-1. Q32)
is the basic principle
1 What method.
representations of variables in k-map
function using
to minimal POS ReferUnit- Q35)
2
Discuss the step by step process
k-map with an example.
McClusky
the following Boolean
function by using Quine (Refer Unit-l. Q39)
Simplify
10, 12, 13)
method. f(A, B, C, D) =
Xm(0, 2, 3, 6, 7, 8,

UNIT-II

(Refer U'nit-Il. Q)
HORT QUESTIONS
subtraction.
Write the general rules in borrowing in (Refer&'nir-I.Q4)
Realize 4x1 MUX using 2x1 MUXes. (Refer init-lU. Q)

03. Draw the nctional logic diagram of 3 to 8 decoder. (Refer Unir-l. Q12)

94, What is code converter? (ReferUnir.

QI)

5. (Refer'nir-11,.Q1)
Design half adder with NAND gates only
6
D
esIgn to 4 decoder
a 3 to 8 decoder using 2
(Refer U'nit-l1. Q19)
SSAY QUESTIONS
numbers with example.
of signed and
unsigned (Refer Unit-ll. Q22)
the addition and subtraction

Q8 neat sketches.
Descr the design process of Full adder with
 DIGITAL ELECTRON
1Q.2 (Refer Uni-II, 0
Q9 What is multiplexer? Realize 2 to 1 and 4 to 1 multiplexers.
(Refer Unit-I1, 02
decoder.
Q10. Write short notes on decoders and implement 2 to 4
(Refer Unit-I, Q7
with 8 to 3 encoder realization.
Q11. Explain encoder along
Refer Unit-I, 03
encoders.
Q12 Write short notes on priority
(Refer Unit-I, 033
versa.
Excess-3 and vice
Q13. Explain the conversion of BCD to
diagram.
(Refer Unit-I, Q38
with circuit logic
Q14. Explain about the 4-bit comparator along

= UNIT-Ill

SHORT QUESTIONS (Refer Unia-11,L0

of programmable logic devices.
Q1 List the different types Refer Uni-u, 23
Q2 Why was PAL developed? (Refer Unit-1T5
of PLA?
Q3 What are the applications (ReferUni-I, 06
between PLA and PAL?
Q4 What are the difference (Refer Uni-1, Q
FPGAs.
Q5. Write the applications of

ESSAY QUESTIONS

logics in detail.
(Refer Unt-1noi
With neat sketch explain about programmable array
Q6
the PLA with neat sketch in
detail along with its
Discuss about
Q7 (Refer Uni-1, Q19
program table.
using CPLDs.
(Refer Unit-IILQI)
and basic construction
Q8 Explain the general structure
of FPGAs along
What is FPGAs? Explain the general structure
(Refer Vnit-DL, QI9)
with its placement and routing problems.
neat sketch. (Refer Uni-IL, Q20)
010. Explain about2-input and 3-input lookup tables with
(Refer Uni-llL, Q2)
011 Write verilog code foe basic logic gates.
UNIT-IV
SHORT QUESTIONS

Draw the characteristics table and excitation table of JK flip-flop (Refer Uni-IVQ)
01

02 Distinguish between synchronous and asynchronous sequential circuits. (Refer Unit-IK 03)

Q3 Write the characteristics table and excitation table of SRflip-flop (ReferU'nir-lK 2

04 What is a flip-flop and how many types of flip-flops? (Refer Uni-IK 0)
What is the difference between synchronous and asynchronous
Q5
counters? (Refer Unit-IVQ1)
ESSAY QUESTIONS

Explain the operalion of gated SR latch along with its truth table
Q6
and timing diagram.
(Refer Unin1ve
Dram the logic diagram of JK flip-flop and using excitation table
Q7
explain its operation.
(Refer Uni-IVQ19
Q8.
Explain the operation of master-slave and edge triggered of

SR Flip-flop.
(Refer Unit-IK Q199
 o r t o n t Qvestions
.3
With neat sketch explainof master-slave edge triggered T Flip-flop
in detail
(Refer Unit-JV, 022)
o10 Explain the operation of serial in- serial out and serial in-parallel
out shift register with neat sketches.
(Refer Unit-JV, 024)
Ott. Describe the operation of universal shift register with neat sketch.
(Refer Unit-1V, Q.26)
012 Design of a 4 bit binary nipple (asynchronous) counter in detail
Refer Unit-1V 229)
Design a MOD-12 synchronous counter using JK flip-flop. Refer Unit-1V Q31)
UNIT-V=
sHORT QUESTIONS
Q1 List the comparison between Moore and Mealy model.
(Refer Unit-V, Qi)
o2 What is state assignment?
(Refer Unit- K, Q3)
to 03 Define algorithmic state machine charts.
(Refer Unit-V 25)
ho04 Write the advantages of FSM. (Refer Unit-K, 27)
O5 What are the basic components of ASM?
Refer T'rir 29)
ESSAY OUESTIONS

Expiain the basic design steps for the analysis of synchronous

sequential circuit with an example.
(Refer Unit-K, Q12)
7. With neat sketches explain the representation of FSM using
Moore and Mealy state models.
(Refer Unit-V Q15)
3. Write short notes on the state minimization
along with patitioning
minimization procedure.
(Refer Unit-V, Q16)
With neat sketch explain about sequence generation.
910. Write short notes
(Refer Unit- 08)
on
detector with example.
sequence an
(Refer Unit-V Q20)
911. Describe about the algorithmic state machine charts
(Refer Unit-K. Q22)
12 Draw ASM block diagram of Mealy and Moore circuits.
(Refer Unin-V. Q24)
13 Discuss about Monoshot multivibrator using op-amp along
with ts input and output waveforms.
(Refer Unit-1. Q38)
odel Paper 1

FACULTY OF ENGINEERING
0SMANIA UNIVERSIT
Examination

B.E. II Semester (CSE, IT, ECE)

MODEL PAPER I

DIGITAL ELECTRONICS
Marks: 70

Time 3 Hours

five questions
from Part-B
questions from
Part-A and Any
Note: Answer all

PART A (20 MARKS)

xy'z+x'y'z+xyz.

(1) Given the

Boolean function,
F
IRefer Unit4,
Boolean algebra.
using
Simplify the
algebraic expression [Refer Unit4, 016
implicant.
implicant and prime
Define the terms
(2)
subtraction of two n-digit
in
(3)
Discuss steps
involved
Refer Unit-|1, 03]
unsigned numbers.

1 multiplexer using
Draw the circuit
diagram of 2 to [Refer Unit-41, 051
(4)
transmission gates. [Refer Unit-L, Q41
Write the advantages
of PLA.
(5) [Refer Unit-ll, Q111
of HDLs.
importance
(6) Write the
[Refer Unit-V, 21
between a latch and flip-flop.
Distinguish
(7)
characteristic
characteristic equation,
Define the terms
(8) [Refer Unit-IV, 04
excitation table.
table and
[Refer Unit-V, a3
assignment?
What is state
(9) Refer Unit-V, Q7
of FSM.
Write the advantages
(10)
PART B (50 MARKS)
IRefer Unit-, Q23
of digital hardware with, neat sketches.
(11) (a) Exolain the design
principle of K-map method and give the
(b) What is the basic
Refer Unit-, Q32
of varlables in K-map method.
different representations
(Refer Unit-4, Q24
RealIze 2-to-1 and 4-to-1 Muxes
(121 (a) What is multiplexer
explain about BCD to 7-segment
h With neat figures
[Refer Unit-l, Q33
decoder conversion.
 DIOITAL ILICTRONICSs
)(a) with neat sketch explain about programmable array
logic in detail.
[Refer Unt-1, Q13]
() Explain about the 2-input and 3-input lookup tables
with neat sketch.
[Refer Unit-411, Q22]
(34)(a) Explain the operation of gated SR latch along with its
truth table and timing diagram.
[Refer Unit-/V, Q14]
(b) Design of a 4 bit binary ripple counter in detail.
(Refer Unit-V, Q29]
5) (a) with neat sketch
explain about sequence generation.
[Refer Unit-V, Q18]
(b) Describe about the algorithmic state machine
charts. Refer Unit-V, a22]
(16) (a) Design a three-way light control with the
help of
logic circuits.
[Refer Unit-4, a31]
(b) Discuss about PLA with neat sketch in detail.
[Refer Unit-41, Q15]
(17) (a) Realize 3-to-8 decoder along with its truth
table.
Refer Unit-I, Q27]
(b) Explain the operation of master-slave and
edge
triggered of SR flip-flop.
[Refer Unit-V, a19]
Model Paper II MP3

FACULTY OF ENGINEERING
0SMANIA UNIVERSITY
Examination
B.E. I Semester (CSE, IT, ECE)
MODEL PAPER II

DIGITAL ELECTRONICS
Marks: 70
Time: 3 Hours
from Part-B.
Note: Answer all questions from
Part-A and Any five questions

PART A(20 MARKS)

List the Huntington postulates.

[Refer Unit-, Q8
(1)
Explain the tabulation method is reduction prime
(2)
implicant chart.
[Refer Unit-, Q18

Realize 4 x 1 MUX using 2 x 1 MUXes.

[Refer Unit-|l, Q4
(3)
What is code converter?
[Refer Unit|l, 212
(4)

What are the differences between PLA and

PAL? [Refer Unit-ll, Q7
(5)
Write the applications of FPGAs. [Refer Unit-, 29
(6)
(7) Draw the characteristic table and excitation table of

JK flip-flop.
Refer Unit-V, Q1
What are the differences between combinational and
(8)
sequential circuits?
[Refer Unit-/V, Q7

Compare ASM charts and state diagrams. [Refer Unit-V, Qó]

(9)
(10) What are the basic components of ASM? [Refer Unit-V, Q9

PART B (50 MARKS)

(11) (a) State and explain the postulates and theorems of Boolean algebra.
[Refer Unit-1, Q28]

(b) Describe steps to minimal SOP function using K-map with

[Refer Unit4, Q34]
an example.

(12) (a) Describe the design process of full adder with neat
[Refer Unit-4l, Q22}
sketches.

IRefer Unit-4l, Q29)

(b) Explain Encoder along with 8-to-3 encoder realization.
 DIGITAL ELECTRONICs
MPA
structure and basic construction
al (a) Explain the general
(13)
using CPLDs. [Refer Unit-l1, Q18]
and write verilog code for 1-bit full adder. Refer Unit-4, a26]
(b) Design
T flip-flóp along with its working operation
14) (a) Implement
and excitation table. IRefer Unit-V, Q17

(b) Describe the operation of universal shift register with

neat sketch. [Refer Unit-V, Q26]

(15) (a) With neat sketches explain the representation of FSM

using Moore and Mealy state models. [Refer Unit-V, Q15]

(b) Implement ASM block along with its equivalent state

diagram. Refer Unit-V, Q23]

Write the general rules for simplifying logic function
(16) (a)

using K-map. [Refer Unit-, Q36]

about the state minimization along' with
(b) Explain
partitioning minimization procedure. [Refer Unit-V, Q16]

(17) Write short notes on the following,

(a) Priority encoders. [Refer Unit-41, Q30]

(b) Triggering of flip-flops. [Refer Unit-iv, Q18]