INTEGRATED CIRCUITS

DATA SHEET

TDA8703
8-bit high-speed analog-to-digital
converter
Product specification 1996 Aug 26
Supersedes data of April 1993
File under Integrated Circuits, IC02
Philips Semiconductors Product specification

8-bit high-speed analog-to-digital

TDA8703
converter

FEATURES APPLICATIONS
• 8-bit resolution • General purpose high-speed analog-to-digital
• Sampling rate up to 40 MHz conversion
• High signal-to-noise ratio over a large analog input • Digital TV, IDTV
frequency range (7.1 effective bits at 4.43 MHz • Subscriber TV decoder
full-scale input) • Satellite TV decoders
• Binary or two's complement 3-state TTL outputs • Digital VCR.
• Overflow/underflow 3-state TTL output
• TTL compatible digital inputs GENERAL DESCRIPTION
• Low-level AC clock input signal allowed
The TDA8703 is an 8-bit high-speed Analog-to-Digital
• Internal reference voltage generator Converter (ADC) for video and other applications.
• Power dissipation only 290 mW (typical) It converts the analog input signal into 8-bit binary-coded
digital words at a maximum sampling rate of 40 MHz.
• Low analog input capacitance, no buffer amplifier
All digital inputs and outputs are TTL compatible, although
required
a low-level AC clock input signal is allowed.
• No sample-and-hold circuit required.

ORDERING INFORMATION

TYPE PACKAGE
NUMBER NAME DESCRIPTION VERSION
TDA8703 DIP24 plastic dual in-line package; 24 leads (600 mil) SOT101-1
TDA8703T SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

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8-bit high-speed analog-to-digital converter TDA8703

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VCCA analog supply voltage 4.5 5.0 5.5 V
VCCD digital supply voltage 4.5 5.0 5.5 V
VCCO output stages supply voltage 4.2 5.0 5.5 V
ICCA analog supply current − 28 36 mA
ICCD digital supply current − 19 25 mA
ICCO output stages supply current − 11 14 mA
ILE DC integral linearity error − − ±1 LSB
DLE DC differential linearity error − − ±1/2 LSB
AILE AC integral linearity error note 1 − − ±2 LSB
B −3 dB bandwidth note 2; fCLK = 40 MHz − 19.5 − MHz
fCLK/fCLK maximum conversion rate note 3 40 − − MHz
Ptot total power dissipation − 290 415 mW

Notes
1. Full-scale sinewave (fi = 4.4 MHz; fCLK; fCLK = 27 MHz).
2. The −3 dB bandwidth is determined by the 3 dB reduction in the reconstructed output (full-scale signal at input).
3. The circuit has two clock inputs CLK and CLK. There are four modes of operation:
a) TTL (mode 1); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling
on the LOW-to-HIGH transition of the input clock signal.
b) TTL (mode 2); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling
on the HIGH-to-LOW transition of the input clock signal.
c) AC drive modes (modes 3 and 4); When driving the CLK input directly and with any AC signal of 0.5 V
(peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the
clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-to-LOW transition.
d) If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF
capacitor.

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8-bit high-speed analog-to-digital converter TDA8703

BLOCK DIAGRAM

clock inputs

handbook, full pagewidth

V CCA CLK CLK VCCD TC CE
7 16 17 18 21 22

STABILIZER CLOCK DRIVER

DEC 5
TDA8703
TDA8703T
VRT 9

12 D7
MSB
13 D6
14 D5
15 D4
analog VI 8 ANALOG - TO - DIGITAL
LATCHES TTL OUTPUTS 23 D3 data outputs
voltage input CONVERTER
24 D2
1 D1
2 D0 LSB

VRB 4
19
VCCO

OVERFLOW / UNDERFLOW overflow /

TTL OUTPUT 11
LATCH underflow
output
3 20
AGND DGND MGA015

analog ground digital ground

Fig.1 Block diagram.

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8-bit high-speed analog-to-digital converter TDA8703

PINNING

SYMBOL PIN DESCRIPTION

D1 1 data output; bit 1
D0 2 data output; bit 0 (LSB)
AGND 3 analog ground
VRB 4 reference voltage bottom (decoupling)
DEC 5 decoupling input (internal stabilization
loop decoupling)
n.c. 6 not connected handbook, halfpage
D1 1 24 D2
VCCA 7 positive supply voltage for analog
circuits (+5 V) D0 2 23 D3

VI 8 analog voltage input AGND 3 22 CE

VRT 9 reference voltage top (decoupling) V RB 4 21 TC
n.c. 10 not connected
DEC 5 20 DGND
O/UF 11 overflow/underflow data output
n.c. 6 19 V CCO
D7 12 data output; bit 7 (MSB) TDA8703/
V CCA 7
TDA8703T 18 V CCD
D6 13 data output; bit 6
D5 14 data output; bit 5 VI 8 17 CLK

D4 15 data output; bit 4 V RT 9 16 CLK

CLK 16 clock input n.c. 10 15 D4

CLK 17 complementary clock input O/UF 11 14 D5
VCCD 18 positive supply voltage for digital
D7 12 13 D6
circuits (+5 V)
MLB034
VCCO 19 positive supply voltage for output
stages (+5 V)
DGND 20 digital ground
TC 21 input for two's complement output (TTL
level input, active LOW)
CE 22 chip enable input (TTL level input,
active LOW)
D3 23 data output; bit 3 Fig.2 Pin configuration.
D2 24 data output; bit 2

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8-bit high-speed analog-to-digital converter TDA8703

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCCA analog supply voltage −0.3 +7.0 V
VCCD digital supply voltage −0.3 +7.0 V
VCCO output stages supply voltage −0.3 +7.0 V
VCCA − VCCD supply voltage differences −1.0 +1.0 V
VCCO − VCCD supply voltage differences −1.0 +1.0 V
VCCA − VCCO supply voltage differences −1.0 +1.0 V
VVI input voltage range referenced to AGND −0.3 +7.0 V
VCLK/VCLK AC input voltage for switching note 1; referenced to DGND − 2.0 V
(peak-to-peak value)
IO output current − +10 mA
Tstg storage temperature −55 +150 °C
Tamb operating ambient temperature 0 +70 °C
Tj junction temperature − +125 °C

Notes
1. The circuit has two clock inputs CLK and CLK. There are four modes of operation:
a) TTL (mode 1); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling
on the LOW-to-HIGH transition of the input clock signal.
b) TTL (mode 2); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling
on the HIGH-to-LOW transition of the input clock signal.
c) AC drive modes (modes 3 and 4); When driving the CLK input directly and with any AC signal of 0.5 V
(peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the
clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-to-LOW transition.
d) If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF
capacitor.

HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL RESISTANCE

SYMBOL PARAMETER VALUE UNIT

Rth j-a from junction to ambient in free air
SOT101-1 55 K/W
SOT137-1 75 K/W

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8-bit high-speed analog-to-digital converter TDA8703

CHARACTERISTICS
VCCA = V7 − V3 = 4.5 V to 5.5 V; VCCD = V18 − V20 = 4.5 V to 5.5 V; VCCO = V19 − V20 = 4.5 V to 5.5 V; AGND and
DGND shorted together; VCCA − VCCD = −0.5 V to +0.5 V; VCCO − VCCD = −0.5 V to +0.5 V;
VCCA − VCCD = −0.5 V to +0.5 V; Tamb = 0 °C to +70 °C; unless otherwise specified (typical values measured at
VCCA = VCCD = VCCO = 5 V and Tamb = 25 °C).

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply
VCCA analog supply voltage 4.5 5.0 5.5 V
VCCD digital supply voltage 4.5 5.0 5.5 V
VCCO output stages supply voltage 4.2 5.0 5.5 V
ICCA analog supply current − 28 36 mA
ICCD digital supply current − 19 25 mA
ICCO output stage supply current all outputs LOW − 11 14 mA
Inputs
CLOCK INPUT CLK AND CLK (note 1; REFERENCED TO DGND)
VIL LOW level input voltage 0 − 0.8 V
VIH HIGH level input voltage 2.0 − VCCD V
IIL LOW level input current VCLK/VCLK = 0.4 V −400 − − µA
IIH HIGH level input current VCLK/VCLK = 0.4 V − − 100 µA
VCLK/VCLK = VCCD − − 300 µA
Zi input impedance fCLK/fCLK = 10 MHz − 4 − kΩ
Ci input capacitance fCLK/fCLK = 10 MHz − 4.5 − pF
VCLK − VCLK AC input voltage for switching note 1; DC level = 1.5 V 0.5 − 2.0 V
(peak-to-peak value)
TC AND CE (REFERENCED TO DGND)
VIL LOW level input voltage 0 − 0.8 V
VIH HIGH level input voltage 2.0 − VCCD V
IIL LOW level input current VIL = 0.4 V −400 − − µA
IIH HIGH level input current VIH = 2.7 V − − 20 µA
VI (ANALOG INPUT VOLTAGE REFERENCED TO AGND)
VVI(B) input voltage (bottom) 1.33 1.41 1.48 V
VVI(0) input voltage output code = 0 1.455 1.55 1.635 V
VOS(B) offset voltage (bottom) VVI(0) − VVI(B) 0.125 − 0.155 V
VVI(T) input voltage (top) 3.2 3.36 3.5 V
VVI(255) input voltage output code = 255 3.115 3.26 3.385 V
VOS(T) offset voltage (top) VVI(T) − VVI(255) 0.085 − 0.115 V
VVI(p-p) input voltage amplitude (peak-to-peak value) 1.66 1.71 1.75 V
IIL LOW level input current VVI = 1.4 V − 0 − µA
IIH HIGH level input current VVI = 3.6 V 60 120 180 µA
Zi input impedance fi = 1 MHz − 10 − kΩ
Ci input capacitance fi = 1 MHz − 14 − pF

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8-bit high-speed analog-to-digital converter TDA8703

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Reference resistance
Rref reference resistance VRT to VRB − 220 − Ω
Outputs
DIGITAL OUTPUTS (D7 - D0) (REFERENCED TO DGND)
VOL LOW level output voltage IO = 1 mA 0 − 0.4 V
VOH HIGH level output voltage IO = −0.4 mA 2.7 − VCCD V
IOZ output current in 3-state mode 0.4 V < VO < VCCD −20 − +20 µA
Switching characteristics (note 2; see Fig.3)
fCLK/fCLK maximum clock frequency 40 − − MHz
Analog signal processing (fCLK = 40 MHz)
B −3 dB bandwidth note 3 − 19.5 − MHz
Gd differential gain note 4 − 0.6 − %
φd differential phase note 4 − 0.8 − deg
f1 fundamental harmonics (full-scale) fi = 4.43 MHz − − 0 dB
fall harmonics (full-scale), all components fi = 4.43 MHz − −55 − dB
SVRR1 supply voltage ripple rejection note 5 − −28 −25 dB
SVRR2 supply voltage ripple rejection note 5 − 1 2.5 %/V
Transfer function
ILE DC integral linearity error − − ±1 LSB
DLE DC differential linearity error − − ±1/2 LSB
AILE AC integral linearity error note 6 − − ±2 LSB
EB effective bits fi = 4.43 MHz − 7.1 − bits
Timing (note 7; see Figs 3 to 6; fCLK = 40 MHz)
tdS sampling delay − − 2 ns
tHD output hold time 6 − − ns
tdLH output delay time LOW-to-HIGH transition − 8 10 ns
tdHL output delay time HIGH-to-LOW transition − 16 20 ns
tdZH 3-state output delay times enable-to-HIGH − 19 25 ns
tdZL 3-state output delay times enable-to-LOW − 16 20 ns
tdHZ 3-state output delay times disable-to-HIGH − 14 20 ns
tdLZ 3-state output delay times disable-to-LOW − 9 12 ns

1996 Aug 26 8
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8-bit high-speed analog-to-digital converter TDA8703

Notes
1. The circuit has two clock inputs CLK and CLK. There are four modes of operation:
a) TTL (mode 1); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling
on the LOW-to-HIGH transition of the input clock signal.
b) TTL (mode 2); CLK decoupled to DGND by a capacitor. CLK input is TTL threshold voltage of 1.5 V and sampling
on the HIGH-to-LOW transition of the input clock signal.
c) AC drive modes (modes 3 and 4); When driving the CLK input directly and with any AC signal of 0.5 V
(peak-to-peak value) imposed on a DC level of 1.5 V, sampling takes place on the LOW-to-HIGH transition of the
clock signal. When driving the CLK input with such a signal, sampling takes place on the HIGH-to-LOW transition.
d) If one of the clock inputs is not driven, then it is recommended to decouple this input to DGND with a 100 nF
capacitor.
2. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 2 ns.
3. The −3 dB bandwidth is determined by the 3 dB reduction in the reconstructed output (full-scale signal at the input).
4. Low frequency ramp signal (VVI(p-p) = 1.8 V and fi = 15 kHz) combined with a sinewave input voltage (VVI(p-p) = 0.5 V,
fi = 4.43 MHz) at the input.
5. Supply voltage ripple rejection:
a) SVRR1; variation of the input voltage producing output code 127 for supply voltage variation of 1 V:
SVRR1 = 20 log (∆VVI(127) / ∆VCCA)
b) SVRR2; relative variation of the full-scale range of analog input for a supply voltage variation of 1 V:
SVR2 = {∆(VVI(0) − VVI(255)) / (VVI(0) − VVI(255))} ÷ ∆VCCA.
6. Full-scale sinewave (fi = 4.4 MHz; fCLK; fCLK = 27 MHz).
7. Output data acquisition:
a) Output data is available after the maximum delay of tdHL and tdLH.

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8-bit high-speed analog-to-digital converter TDA8703

Table 1 Output coding and input voltage (referenced to AGND; typical values)

BINARY OUTPUT BITS TWO'S COMPLEMENT OUTPUT BITS

STEP VVI(p-p) O/UF D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Underflow <1.55 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
0 1.55 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
1 − 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1
. . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . .
254 . 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0
255 3.26 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
Overflow >3.26 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1

Table 2 Mode selection

TC CE D7-D0 O/UF
X(1) 1 high impedance high impedance
0 0 active; two’s complement active
1 0 active; binary active

Note
1. X = don’t care.

handbook, full pagewidth

CLK 1.3 V

sample N sample N + 1
sample N + 2

VI

t HD

t dS
2.4 V

D0 - D7 data N – 1 1.3 V data N data N + 1

0.4 V

t dLH
MEA105
t dHL

Fig.3 Timing diagram.

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8-bit high-speed analog-to-digital converter TDA8703

handbook, full pagewidth

reference
CE level
input (1.4 V)

2.4 V
data
outputs
0.4 V
t dHZ t dZH
t dLZ t dZL MLB035 - 1

Fig.4 3-state delay timing diagram.

V CCO
handbook, halfpage

2 kΩ

VCCO
S1
handbook, halfpage

2 kΩ D0 to D7

D0 to D7 C 5
kΩ
15 pF
IN916
IN916 or
or IN3064
IN3064

DGND
MGD691 S2

MBB955
DGND

Fig.6 Load circuit for timing measurement;

Fig.5 Load circuit for timing measurement; data 3-state outputs (CE: fi = 1 MHz; VVI = 3 V);
outputs (CE = LOW). see Table 3.

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8-bit high-speed analog-to-digital converter TDA8703

Table 3 Mode selection

TIMING MEASUREMENT SWITCH S1 SWITCH S2 CAPACITOR
tdZH open closed 15 pF
tdZL closed open 15 pF
tdHZ closed closed 5 pF
tdLZ closed closed 5 pF

INTERNAL PIN CONFIGURATIONS

handbook, halfpage handbook, halfpage

VCCO V CCA

D7 to D0 (x 90)
VI
O/U

DGND AGND
MGD692 MLB037

Fig.7 TTL data and overflow/underflow outputs. Fig.8 Analog inputs.

handbook, halfpage
VCCO

handbook, halfpage
V CCD

CE

TC

DGND
MLB039

DGND

MGD693

Fig.9 CE (3-state) input. Fig.10 TC (two’s complement) input.

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8-bit high-speed analog-to-digital converter TDA8703

handbook, full pagewidth

V CCA

VRT

VRB

DEC

AGND
MCD188

Fig.11 VRB, VRT and DEC.

VCCD
handbook, full pagewidth

CLK V ref

30 kΩ 30 kΩ

DGND
MCD189 - 1

Fig.12 CLK and CLK inputs.

1996 Aug 26 13
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8-bit high-speed analog-to-digital converter TDA8703

APPLICATION INFORMATION
Additional application information will be supplied upon request (please quote number FTV/8901).

handbook, full pagewidth

D1 1 D2
24

D0 2 D3
23

AGND 3 CE
22

V RB 4 TC
21

DEC 5 DGND
20
22 nF
n.c. 6 VCCO
19 5V
47 pF TDA8703 22 Ω (1)
V CCA TDA8703T VCCD
7
18

4.7 µF 22 nF
VI 8 CLK
17

V RT 100 pF
9 CLK
16
4.7 µF 22 nF
n.c. 10 D4 DGND
15

O / UF 11 D5
14
AGND
D7 12 D6
13

MGA014 - 1

CLK should be decoupled to the DGND with a 100 nF capacitor, if a TTL signal is used on CLK (see Chapter “Characteristics”, note 1).
CLK and CLK can be used in a differential mode (see Chapter “Characteristics”, note 1).
VRB and VRT are decoupling pins for the internal reference ladder; do not draw current from these pins in order to achieve good linearity.
If it is required to use the TDA8703 in a parallel system configuration, the references (VRB and VRT) of each TDA8703 can be connected together.
Code 0 will be identical and code 255 will remain in the 1 LSB variation for each TDA8703.
Analog and digital supplies should be separated and decoupled.
Pins 6 and 10 should be connected to AGND in order to prevent noise influence.
(1) It is recommended to decouple VCCO through a 22 Ω resistor especially when the output data of the TDA8703 interfaces with a capacitive CMOS
load device.

Fig.13 Application diagram.

1996 Aug 26 14
Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8703

PACKAGE OUTLINES

DIP24: plastic dual in-line package; 24 leads (600 mil) SOT101-1

seating plane

D ME

A2 A

L A1

c
Z e w M
b1
(e 1)
b
24 13 MH

pin 1 index

1 12

0 5 10 mm
scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

UNIT
A A1 A2
b b1 c D (1) E (1) e e1 L ME MH w Z (1)
max. min. max. max.
1.7 0.53 0.32 32.0 14.1 3.9 15.80 17.15
mm 5.1 0.51 4.0 2.54 15.24 0.25 2.2
1.3 0.38 0.23 31.4 13.7 3.4 15.24 15.90
0.066 0.021 0.013 1.26 0.56 0.15 0.62 0.68
inches 0.20 0.020 0.16 0.10 0.60 0.01 0.087
0.051 0.015 0.009 1.24 0.54 0.13 0.60 0.63

Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION

92-11-17
SOT101-1 051G02 MO-015AD
95-01-23

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Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8703

SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

D E A
X

y HE v M A

24 13

Q
A2 A
A1 (A 3)

pin 1 index
θ
Lp
L

1 12 detail X
e w M
bp

0 5 10 mm
scale

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z
(1)
θ
max.
0.30 2.45 0.49 0.32 15.6 7.6 10.65 1.1 1.1 0.9
mm 2.65 0.25 1.27 1.4 0.25 0.25 0.1 o
0.10 2.25 0.36 0.23 15.2 7.4 10.00 0.4 1.0 0.4 8
0.012 0.096 0.019 0.013 0.61 0.30 0.42 0.043 0.043 0.035 0o
inches 0.10 0.01 0.050 0.055 0.01 0.01 0.004
0.004 0.089 0.014 0.009 0.60 0.29 0.39 0.016 0.039 0.016

Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION

92-11-17
SOT137-1 075E05 MS-013AD
95-01-24

1996 Aug 26 16
Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8703

SOLDERING Several techniques exist for reflowing; for example,

thermal conduction by heated belt. Dwell times vary
Introduction
between 50 and 300 seconds depending on heating
There is no soldering method that is ideal for all IC method. Typical reflow temperatures range from
packages. Wave soldering is often preferred when 215 to 250 °C.
through-hole and surface mounted components are mixed
Preheating is necessary to dry the paste and evaporate
on one printed-circuit board. However, wave soldering is
the binding agent. Preheating duration: 45 minutes at
not always suitable for surface mounted ICs, or for
45 °C.
printed-circuits with high population densities. In these
situations reflow soldering is often used.
WAVE SOLDERING
This text gives a very brief insight to a complex technology.
Wave soldering techniques can be used for all SO
A more in-depth account of soldering ICs can be found in
packages if the following conditions are observed:
our “IC Package Databook” (order code 9398 652 90011).
• A double-wave (a turbulent wave with high upward
DIP pressure followed by a smooth laminar wave) soldering
technique should be used.
SOLDERING BY DIPPING OR BY WAVE
• The longitudinal axis of the package footprint must be
The maximum permissible temperature of the solder is parallel to the solder flow.
260 °C; solder at this temperature must not be in contact • The package footprint must incorporate solder thieves at
with the joint for more than 5 seconds. The total contact the downstream end.
time of successive solder waves must not exceed
5 seconds. During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
The device may be mounted up to the seating plane, but applied by screen printing, pin transfer or syringe
the temperature of the plastic body must not exceed the dispensing. The package can be soldered after the
specified maximum storage temperature (Tstg max). If the adhesive is cured.
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the Maximum permissible solder temperature is 260 °C, and
temperature within the permissible limit. maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
REPAIRING SOLDERED JOINTS 6 seconds. Typical dwell time is 4 seconds at 250 °C.

Apply a low voltage soldering iron (less than 24 V) to the A mildly-activated flux will eliminate the need for removal
lead(s) of the package, below the seating plane or not of corrosive residues in most applications.
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in REPAIRING SOLDERED JOINTS
contact for up to 10 seconds. If the bit temperature is Fix the component by first soldering two diagonally-
between 300 and 400 °C, contact may be up to 5 seconds. opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
SO time must be limited to 10 seconds at up to 300 °C. When
REFLOW SOLDERING using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
Reflow soldering techniques are suitable for all SO 270 and 320 °C.
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

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Philips Semiconductors Product specification

8-bit high-speed analog-to-digital converter TDA8703

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1996 Aug 26 18
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