MCP40D17/18/19: 7-Bit Single I C™ (With Command Code) Digital POT With Volatile Memory in SC70

MCP40D17/18/19
7-Bit Single I2C™ (with Command Code) Digital POT

with Volatile Memory in SC70
Features Package Types

• Potentiometer or Rheostat configuration options Potentiometer Rheostat
• 7-bit: Resistor Network Resolution MCP40D18 MCP40D17
- 127 Resistors (128 Steps) SC70-6 SC70-6
• Zero Scale to Full Scale Wiper operation VDD 1 A 6 A
VDD 1 6 W
W
A
VSS 2 5 B
• RAB Resistances: 5 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ VSS 2 5 W B
B W
• Low Wiper Resistance: 100Ω (typical) SCL 3 4 SDA
SCL 3 4 SDA
• Low Tempco:
MCP40D19
- Absolute (Rheostat): 50 ppm typical SC70-5
(0°C to 70°C)
VDD 1 5 W
- Ratiometric (Potentiometer): 15 ppm typical W
VSS 2
• I2C Protocol B A
SCL 3 4 SDA
- Supports SMBus 2.0 Write Byte/Word
Protocol Formats
- Supports SMBus 2.0 Read Byte/Word
Protocol Formats
Applications
• PC Servers (I2C Protocol with Command Code)
• Standard I2C Device Addresses:
• Amplifier Gain Control and Offset Adjustment
- All devices offered with address “0101110”
- MCP40D18 also offered with address • Sensor Calibration (Pressure, Temperature,
“0111110” Position, Optical and Chemical)
• Brown-out reset protection (1.5V typical) • Set point or offset trimming
• Power-on Default Wiper Setting (Mid-scale) • Cost-sensitive mechanical trim pot replacement
• Low-Power Operation: • RF Amplifier Biasing
- 2.5 µA Static Current (typical) • LCD Brightnes and Contract Adjustment
• Wide Operating Voltage Range:
- 2.7V to 5.5V - Device Characteristics
Specified
- 1.8V to 5.5V - Device Operation
• Wide Bandwidth (-3 dB) Operation:
- 2 MHz (typical) for 5.0 kΩ device
• Extended temperature range (-40°C to +125°C)
• Very small package (SC70)
• Lead free (Pb-free) package
Device Features
# of Steps
Resistance (typical)
Interface
Memory
Control
VDD
Wiper Wiper Operating
Type
Device Configuration Options (kΩ) (Ω) Range ( 1) Package

MCP40D17 I2C 128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 75 1.8V to 5.5V SC70-6
MCP40D18 I2C 128 Potentiometer RAM 5.0, 10.0, 50.0, 100.0 75 1.8V to 5.5V SC70-6
MCP40D19 I2C 128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 75 1.8V to 5.5V SC70-5
Note 1: Analog characteristics only tested from 2.7V to 5.5V
© 2009 Microchip Technology Inc. DS22152B-page 1
Downloaded from Arrow.com.

MCP40D17/18/19
Device Block Diagram
VDD Power-up/ A (2)

Brown-out
VSS
Control
W
I2C Serial
SCL Interface
Module, Resistor
SDA Network 0 B (1, 2)
Control
Logic, & (Pot 0)
Note 1: Some configurations will have this
Memory signal internally connected to
Note 1
ground.
2: In some configurations, this signal
may not be connected externally
(internally floating or grounded).
Comparison of Similar Microchip Devices ( 1)
Technology
Resistance (typical)
WiperLock
# of Steps
Interface
Interface
Memory
Control
VDD
Wiper Operating
Type
HV
Device Configuration Options (kΩ) Range Package
( 2)
MCP40D17 I2C 128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V No No SC70-6
MCP4017 ( 2, 4) I2C 128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V No No SC70-6
( 2)
MCP4012 U/D 64 Rheostat RAM 2.1, 5.0, 10.0, 50.0 1.8V to 5.5V Yes No SOT-23-6
( 2)
MCP4022 U/D 64 Rheostat EE 2.1, 5.0, 10.0, 50.0 2.7V to 5.5V Yes Yes SOT-23-6
MCP4132 ( 3) SPI 129 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V Yes No PDIP-8,
MCP4142 ( 3)
SPI 129 Rheostat EE 5.0, 10.0, 50.0, 100.0 2.7V to 5.5V Yes Yes SOIC-8,
MSOP-8,
MCP4152 ( 3) SPI 257 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V Yes No
DFN-8
MCP4162 ( 3) SPI 257 Rheostat EE 5.0, 10.0, 50.0, 100.0 2.7V to 5.5V Yes Yes
MCP4532 ( 3) I2C 129 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V Yes No MSOP-8,
MCP4542 ( 3) I2C 129 Rheostat EE 5.0, 10.0, 50.0, 100.0 2.7V to 5.5V Yes Yes DFN-8
MCP4552 ( 3) I2C 257 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V Yes No
MCP4562 ( 3) I2C 257 Rheostat EE 5.0, 10.0, 50.0, 100.0 2.7V to 5.5V Yes Yes
MCP40D18 ( 2) I2C 128 Potentiometer RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V No No SC70-6
MCP4018 ( 2, 4) I2C 128 Potentiometer RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V No No SC70-6
MCP4013 ( 2) U/D 64 Potentiometer RAM 2.1, 5.0, 10.0, 50.0 1.8V to 5.5V Yes No SOT-23-6
( 2)
MCP4023 U/D 64 Potentiometer EE 2.1, 5.0, 10.0, 50.0 2.7V to 5.5V Yes Yes SOT-23-6
MCP40D19 ( 2) I2C 128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V No No SC70-5
MCP4019 ( 2, 4) I2C 128 Rheostat RAM 5.0, 10.0, 50.0, 100.0 1.8V to 5.5V No No SC70-5
( 2)
MCP4014 U/D 64 Rheostat RAM 2.1, 5.0, 10.0, 50.0 1.8V to 5.5V Yes No SOT-23-5
MCP4024 ( 2) U/D 64 Rheostat EE 2.1, 5.0, 10.0, 50.0 2.7V to 5.5V Yes Yes SOT-23-5
Note 1: This table is broken into three groups by a thick line (and color coding). The unshaded devices in this table
are the devices described in this data sheet, while the shaded devices offer a comparable resistor network
configuration.
2: Analog characteristics only tested from 2.7V to 5.5V.
3: Analog characteristics only tested from 3.0V to 5.5V.
4: These devices have a simplified I2C command format, which allows higher data throughput.
DS22152B-page 2 © 2009 Microchip Technology Inc.

MCP40D17/18/19
1.0 ELECTRICAL † Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
CHARACTERISTICS This is a stress rating only and functional operation of
the device at those or any other conditions above those
Absolute Maximum Ratings † indicated in the operational listings of this specification
Voltage on VDD with respect to VSS ..... -0.6V to +7.0V is not implied. Exposure to maximum rating conditions
Voltage on SCL, and SDA with respect to VSS for extended periods may affect device reliability.
............................................................................. -0.6V to 12.5V
Voltage on all other pins (A, W, and B)
with respect to VSS ............................ -0.3V to VDD + 0.3V
Input clamp current, IIK
(VI < 0, VI > VDD, VI > VPP ON HV pins) ........... ±20 mA
Output clamp current, IOK
(VO < 0 or VO > VDD) ....................................... ±20 mA
Maximum output current sunk by any Output pin
........................................................................... 25 mA
Maximum output current sourced by any Output pin
........................................................................... 25 mA
Maximum current out of VSS pin ...................... 100 mA
Maximum current into VDD pin ......................... 100 mA
Maximum current into A, W and B pins........... ±2.5 mA
Package power dissipation (TA = +50°C, TJ = +150°C)
SC70-5 ............................................................ 302 mW
SC70-6 ............................................................ 483 mW
Storage temperature .......................... -65°C to +150°C
Ambient temperature with power applied
........................................................... -40°C to +125°C
ESD protection on all pins ........................≥ 4 kV (HBM)
........................................................................≥ 400V (MM)
Maximum Junction Temperature (TJ) .............. +150°C

MCP40D17/18/19
AC/DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C ≤ TA ≤ +125°C (extended)
DC Characteristics All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters Sym Min Typ Max Units Conditions

Supply Voltage VDD 2.7 — 5.5 V Analog Characteristics specified
1.8 — 5.5 V Digital Characteristics specified
VDD Start Voltage VBOR — — 1.65 V RAM retention voltage (VRAM) < VBOR
to ensure Wiper
Reset
VDD Rise Rate to VDDRR (Note 7) V/ms
ensure Power-on
Reset
Delay after device TBORD — 10 20 µS
exits the reset
state
(VDD > VBOR)
Supply Current IDD — 45 80 µA Serial Interface Active,
(Note 8) Write all 0’s to Volatile Wiper
VDD = 5.5V, FSCL = 400 kHz
— 2.5 5 µA Serial Interface Inactive,
(Stop condition, SCL = SDA = VIH),
Wiper = 0, VDD = 5.5V
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS.
3: MCP40D18 device only, includes VWZSE and VWFSE.
4: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.
5: This specification by design.
6: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
7: POR/BOR is not rate dependent.
8: Supply current is independent of current through the resistor network

MCP40D17/18/19
AC/DC CHARACTERISTICS (CONTINUED)

Resistance RAB 4.0 5 6.0 kΩ -502 devices (Note 1)
(± 20%) 8.0 10 12.0 kΩ -103 devices (Note 1)
40.0 50 60.0 kΩ -503 devices (Note 1)
80.0 100 120.0 kΩ -104 devices (Note 1)
Resolution N 128 Taps No Missing Codes
Step Resistance RS — RAB / — Ω Note 5
(127)
Wiper Resistance RW — 100 170 Ω VDD = 5.5 V, IW = 2.0 mA, code = 00h
— 155 325 Ω VDD = 2.7 V, IW = 2.0 mA, code = 00h
Nominal ΔRAB/ΔT — 50 — ppm/°C TA = -20°C to +70°C
Resistance — 100 — ppm/°C TA = -40°C to +85°C
Tempco
— 150 — ppm/°C TA = -40°C to +125°C
Ratiometeric ΔVWB/ΔT — 15 — ppm/°C Code = Midscale (3Fh)
Tempco
Resistor Terminal VA,VW,VB Vss — VDD V Note 4, Note 5
Input Voltage
Range (Terminals
A, B and W)
Maximum current IT — — 2.5 mA Terminal A IAW, W = Full Scale (FS)
through Terminal — — 2.5 mA Terminal B IBW, W = Zero Scale (ZS)
(A, W or B)
— — 2.5 mA Terminal W IAW or IBW, W = FS or ZS
Note 5
— — 1.38 mA IAB, VB = 0V, VA = 5.5V,
RAB(MIN) = 4000
— — 0.688 mA IAB, VB = 0V, VA = 5.5V,
Terminal A RAB(MIN) = 8000
and
— — 0.138 mA Terminal B IAB, VB = 0V, VA = 5.5V,
RAB(MIN) = 40000
— — 0.069 mA IAB, VB = 0V, VA = 5.5V,
RAB(MIN) = 80000
temperature.

MCP40D17/18/19

Full Scale Error VWFSE -3.0 -0.1 — LSb 5 kΩ 2.7V ≤ VDD ≤ 5.5V
(MCP40D18 only) -2.0 -0.1 — LSb 10 kΩ 2.7V ≤ VDD ≤ 5.5V
(code = 7Fh)
-0.5 -0.1 — LSb 50 kΩ 2.7V ≤ VDD ≤ 5.5V
-0.5 -0.1 — LSb 100 kΩ 2.7V ≤ VDD ≤ 5.5V
Zero Scale Error VWZSE — +0.1 +3.0 LSb 5 kΩ 2.7V ≤ VDD ≤ 5.5V
(MCP40D18 only) — +0.1 +2.0 LSb 10 kΩ 2.7V ≤ VDD ≤ 5.5V
(code = 00h)
— +0.1 +0.5 LSb 50 kΩ 2.7V ≤ VDD ≤ 5.5V
— +0.1 +0.5 LSb 100 kΩ 2.7V ≤ VDD ≤ 5.5V
Potentiometer INL -0.5 ±0.25 +0.5 LSb 2.7V ≤ VDD ≤ 5.5V
Integral MCP40D18 device only (Note 2)
Non-linearity
Potentiometer DNL -0.25 ±0.125 +0.25 LSb 2.7V ≤ VDD ≤ 5.5V
Differential Non- MCP40D18 device only (Note 2)
linearity
Bandwidth -3 dB BW — 2 — MHz 5 kΩ Code = 3Fh
(See Figure 2-83, — 1 — MHz 10 kΩ Code = 3Fh
load = 30 pF)
— 260 — kHz 50 kΩ Code = 3Fh
— 100 — kHz 100 kΩ Code = 3Fh
temperature.

MCP40D17/18/19

Rheostat Integral R-INL -2.0 ±0.5 +2.0 LSb 5 kΩ 5.5V, IW = 900 µA
Non-linearity -5.0 +3.5 +5.0 LSb 2.7V, IW = 430 µA (Note 6)
MCP40D18
See Section 2.0 LSb 1.8V (Note 6)
(Note 3)
MCP40D17 and -2.0 ±0.5 +2.0 LSb 10 kΩ 5.5V, IW = 450 µA
MCP40D19 -4.0 +2.5 +4.0 LSb 2.7V, IW = 215 µA (Note 6)
devices only
(Note 3)
-1.125 ±0.5 +1.125 LSb 50 kΩ 5.5V, IW = 90 µA
-1.5 +1 +1.5 LSb 2.7V, IW = 43 µA (Note 6)
-0.8 ±0.5 +0.8 LSb 100 kΩ 5.5V, IW = 45 µA
-1.125 +0.25 +1.125 LSb 2.7V, IW = 21.5 µA (Note 6)
Rheostat R-DNL -0.5 ±0.25 +0.5 LSb 5 kΩ 5.5V, IW = 900 mA
Differential -0.75 +0.5 +0.75 LSb 2.7V, IW = 430 µA (Note 6)
Non-linearity
MCP40D18
(Note 3) -0.5 ±0.25 +0.5 LSb 10 kΩ 5.5V, IW = 450 µA
MCP40D17 and -0.75 +0.5 +0.75 LSb 2.7V, IW = 215 µA (Note 6)
MCP40D19
devices only
(Note 3) -0.375 ±0.25 +0.375 LSb 50 kΩ 5.5V, IW = 90 µA
-0.375 ±0.25 +0.375 LSb 2.7V, IW = 43 µA (Note 6)
-0.375 ±0.25 +0.375 LSb 100 kΩ 5.5V, IW = 45 µA
-0.375 ±0.25 +0.375 LSb 2.7V, IW = 21.5 µA (Note 6)
Capacitance (PA) CAW — 75 — pF f =1 MHz, Code = Full Scale
Capacitance (Pw) CW — 120 — pF f =1 MHz, Code = Full Scale
Capacitance (PB) CBW — 75 — pF f =1 MHz, Code = Full Scale
temperature.

MCP40D17/18/19

Digital Inputs/Outputs (SDA, SCK)
Schmitt Trigger VIH 0.7 VDD — — V 1.8V ≤ VDD ≤ 5.5V
High Input
Threshold
Schmitt Trigger VIL -0.5 — 0.3VDD V
Low Input
Threshold
Hysteresis of VHYS — 0.1VDD — V All inputs except SDA and SCL
Schmitt Trigger N.A. — — V VDD < 2.0V
Inputs (Note 5) SDA 100 kHz
N.A. — — V VDD ≥ 2.0V
and
0.1 VDD — — V SCL VDD < 2.0V
400 kHz
0.05 VDD — — V VDD ≥ 2.0V
Output Low VOL VSS — 0.2VDD V VDD < 2.0V, IOL = 1 mA
Voltage (SDA) VSS — 0.4 V VDD ≥ 2.0V, IOL = 3 mA
Input Leakage IIL -1 — 1 µA VIN = VDD and VIN = VSS
Current
Pin Capacitance CIN, COUT — 10 — pF fC = 400 kHz
RAM (Wiper) Value
Value Range N 0h — 7Fh hex
Wiper POR/BOR NPOR/BOR 3Fh hex
Value
Power Requirements
Power Supply PSS — 0.0005 0.0035 %/% VDD = 2.7V to 5.5V,
Sensitivity VA = 2.7V, Code = 3Fh
(MCP40D18 only)
temperature.

MCP40D17/18/19
1.1 I2C Mode Timing Waveforms and Requirements
SCL
91 93
90 92
SDA
START STOP
Condition Condition
FIGURE 1-1: I2C Bus Start/Stop Bits Timing Waveforms.
TABLE 1-1: I2C BUS START/STOP BITS REQUIREMENTS

I2C AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C ≤ TA ≤ +125°C (Extended)
Operating Voltage VDD range is described in Section 2.0 “Typical
Performance Curves”
Param.
Symbol Characteristic Min Max Units Conditions
No.
FSCL Standard Mode 0 100 kHz Cb = 400 pF, 1.8V - 5.5V
Fast Mode 0 400 kHz Cb = 400 pF, 2.7V - 5.5V
D102 Cb Bus capacitive 100 kHz mode — 400 pF
loading 400 kHz mode — 400 pF
90 TSU:STA START condition 100 kHz mode 4700 — ns Only relevant for repeated
Setup time 400 kHz mode 600 — ns START condition
91 THD:STA START condition 100 kHz mode 4000 — ns After this period the first
Hold time 400 kHz mode 600 — ns clock pulse is generated
92 TSU:STO STOP condition 100 kHz mode 4000 — ns
Setup time 400 kHz mode 600 — ns
93 THD:STO STOP condition 100 kHz mode 4000 — ns
Hold time 400 kHz mode 600 — ns
103 100 102

101
SCL
90 106
91 107 92
SDA
In
109 109 110
SDA
Out
Note 1: Refer to specification D102 (Cb) for load conditions.
FIGURE 1-2: I2C Bus Data Timing.

MCP40D17/18/19
TABLE 1-2: I2C BUS DATA REQUIREMENTS (SLAVE MODE)
I2C AC Characteristics Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C ≤ TA ≤ +125°C (Extended)
Operating Voltage VDD range is described in AC/DC characteristics
Parame- Sym Characteristic Min Max Units Conditions
ter No.
100 THIGH Clock high time 100 kHz mode 4000 — ns 1.8V-5.5V
400 kHz mode 600 — ns 2.7V-5.5V
101 TLOW Clock low time 100 kHz mode 4700 — ns 1.8V-5.5V
400 kHz mode 1300 — ns 2.7V-5.5V
102A ( 5) TRSCL SCL rise time 100 kHz mode — 1000 ns Cb is specified to be from
400 kHz mode 20 + 0.1Cb 300 ns 10 to 400 pF
102B ( 5) TRSDA SDA rise time 100 kHz mode — 1000 ns Cb is specified to be from
103A ( 5) TFSCL SCL fall time 100 kHz mode — 300 ns Cb is specified to be from
103B ( 5) TFSDA SDA fall time 100 kHz mode — 300 ns Cb is specified to be from
( 4)
106 THD:DAT Data input hold 100 kHz mode 0 — ns 1.8V-5.5V, Note 6
time 400 kHz mode 0 — ns 2.7V-5.5V, Note 6
107 TSU:DAT Data input 100 kHz mode 250 — ns ( 2)
setup time 400 kHz mode 100 — ns
109 TAA Output valid 100 kHz mode — 3450 ns ( 1)
from clock 400 kHz mode — 900 ns
110 TBUF Bus free time 100 kHz mode 4700 — ns Time the bus must be free
400 kHz mode 1300 — ns before a new transmission
can start
TSP Input filter spike 100 kHz mode — 50 ns Philips Spec states N.A.
suppression 400 kHz mode — 50 ns
(SDA and SCL)
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the
requirement tsu; DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line
TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before
the SCL line is released.
3: The MCP40D18/MCP40D19 device must provide a data hold time to bridge the undefined part between
VIH and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but
must be tested in order to guarantee that the output data will meet the setup and hold specifications for the
receiving device.
4: Use Cb in pF for the calculations.
5: Not Tested.
6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.

MCP40D17/18/19
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS = GND.
Temperature Ranges
Specified Temperature Range TA -40 — +125 °C
Operating Temperature Range TA -40 — +125 °C
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SC70 θJA — 331 — °C/W Note 1
Thermal Resistance, 6L-SC70 θJA — 207 — °C/W
Note 1: Package Power Dissipation (PDIS) is calculated as follows:
PDIS = (TJ - TA) / θJA,
where: TJ = Junction Temperature, TA = Ambient Temperature.

MCP40D17/18/19
NOTES:

MCP40D17/18/19
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
60 2
IDD Interface Inactive (µA)

1.8
50 1.6 5.5V
1.4
40
1.2
IDD (µA)
400 kHz, 5.5V

30 1
0.8
20 100 kHz, 5.5V 0.6
400 kHz, 2.7V
0.4 2.7V
10 0.2
100 kHz, 2.7V
0
0
-40 0 40 80 120
-40 0 40 80 120
Temperature (°C) Temperature (°C)
FIGURE 2-1: Interface Active Current FIGURE 2-2: Interface Inactive Current
(IDD) vs. SCL Frequency (fSCL) and Temperature (ISHDN) vs. Temperature and VDD.
(VDD = 1.8V, 2.7V and 5.5V). (VDD = 1.8V, 2.7V and 5.5V).

MCP40D17/18/19
120 0.3 120 -40C Rw 25C Rw 85C Rw 125C Rw

0.3
-40C Rw 25C Rw 85C Rw 125C Rw
-40C INL 25C INL 85C INL 125C INL -40C INL 25C INL 85C INL 125C INL
-40C DNL 25C DNL 85C DNL 125C DNL -40C DNL 25C DNL 85C DNL 125C DNL
0.2 0.2
Wiper Resistance (RW)

100 85°C DNL 100
125°C 85°C 125°C
0.1 0.1
Error (LSb)
Error (LSb)
80 INL 80
(ohms)
(ohms)
0 0
60 60
-0.1 25°C -0.1
25°C RW DNL
RW -40°C
-40°C
40 40
-0.2 -0.2
INL
20 -0.3 20 -0.3
0 32 64 96 0 32 64 96
Wiper Setting (decimal) Wiper Setting (decimal)
FIGURE 2-3: 5.0 kΩ : Pot Mode – RW (Ω), FIGURE 2-6: 5.0 kΩ : Rheo Mode – RW
INL (LSb), DNL (LSb) vs. Wiper Setting and (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (VDD = 5.5V). (A = VDD, B = VSS). Temperature (VDD = 5.5V).(IW = 1.4 mA, B = VSS)
300 3
300 0.3 -40C Rw 25C Rw 85C Rw 125C Rw
-40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL
-40C INL 25C INL 85C INL 125C INL -40C DNL 25C DNL 85C DNL 125C DNL
260

260 -40C DNL 25C DNL 85C DNL 125C DNL
0.2 INL
125°C 125°C 2
220 85° INL
220 85°C
Error (LSb)
0.1
Error (LSb)
25°C
(ohms)
(ohms)
180 180
0 1
140 140
-0.1 RW
100 RW 100
0
25°C -0.2
60 -40°C DNL 60 DNL
-40°C
20 -0.3 20 -1
0 32 64 96 0 32 64 96
Temperature (VDD = 2.7V). (A = VDD, B = VSS) Temperature (VDD = 2.7V).(IW = 450 µA, B = VSS)
2500 0.35 2500 -40C Rw 25C Rw 85C Rw 125C Rw 44

-40C INL 25C INL 85C INL 125C INL -40C DNL 25C DNL 85C DNL 125C DNL 39
0.25
-40C DNL 25C DNL 85C DNL 125C DNL 2000

2000 34
RW INL
INL DNL 0.15
29
Error (LSb)
Error (LSb)
1500
(ohms)
1500
(ohms)
0.05 24
-0.05 19
1000 1000
14
-0.15 DNL
RW 9
500 500
-0.25
4
0 -0.35 0 -1
0 32 64 96 0 32 64 96
Note: Refer to AN1080 for additional informa- Note: Refer to AN1080 for additional informa-
tion on the characteristics of the wiper tion on the characteristics of the wiper
resistance (RW) with respect to device resistance (RW) with respect to device
voltage and wiper setting value. voltage and wiper setting value.
Temperature (VDD = 1.8V). (A = VDD, B = VSS) Temperature (VDD = 1.8V). (IW =260 µA, B = VSS)

MCP40D17/18/19
0.0
Full-Scale Error (FSE) (LSb) 200
-0.2 180
-0.4 160
RBW Tempco (PPM)

-0.6 140 2.7V
-0.8 120
-1.0 5.5V 100
80
-1.2
2.7 60
-1.4
40 5.5V
1.8V
-1.6 20
-1.8 0
-40 0 40 80 120 0 32 64 96
Ambient Temperature (°C) Wiper Setting (decimal)
FIGURE 2-9: 5.0 kΩ : Full Scale Error FIGURE 2-12: 5.0 kΩ : RBW Tempco
(FSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V). ΔRWB / ΔT vs. Code.
1.8
Zero-Scale Error (ZSE) (LSb)
1.6
1.4
1.2
1.8V
1.0
0.8 2.7
0.6
0.4 5.5V
0.2
0.0
-40 0 40 80 120
Ambient Temperature (°C)
FIGURE 2-10: 5.0 kΩ : Zero Scale Error FIGURE 2-13: 5.0 kΩ : Power-Up Wiper
(ZSE) vs. Temperature (VDD = 5.5V, 2.7V, 1.8V). Response Time.
5200
5180
Nominal Resistance (RAB)
5160
5140
5120 Wiper
(Ohms)
5100
5080
1.8V VDD
2.7V
5060
5040
5020
5.5V
5000
-40 0 40 80 120
FIGURE 2-11: 5.0 kΩ : Nominal Resistance FIGURE 2-14: 5.0 kΩ : Digital Feedthrough
(Ω) vs. Temperature and VDD. (SCL signal coupling to Wiper pin).

MCP40D17/18/19
FIGURE 2-15: 5.0 kΩ : Write Wiper FIGURE 2-18: 5.0 kΩ : Write Wiper
(40h → 3Fh) Settling Time (VDD=5.5V). (FFh → 00h) Settling Time (VDD=5.5V).

MCP40D17/18/19
120 0.3 120 -40C Rw 25C Rw 85C Rw 125C Rw

0.3
0.2 0.2

100 100
85°C 125°C 85°C 125°C DNL
0.1 0.1
Error (LSb)
Error (LSb)
80 80
(ohms)
(ohms)
0 0
60 60
-0.1 -0.1
-40°C RW
-40°C DNL RW
25°C INL 25°C
40 40
-0.2 INL -0.2
20 -0.3 20 -0.3
0 32 64 96 0 32 64 96
FIGURE 2-21: 10 kΩ Pot Mode : RW (Ω), FIGURE 2-24: 10 kΩ Rheo Mode : RW (Ω),
INL (LSb), DNL (LSb) vs. Wiper Setting and INL (LSb), DNL (LSb) vs. Wiper Setting and
Temperature (VDD = 5.5V). (A = VDD, B = VSS). Temperature (VDD = 5.5V).(IW = 450 µA, B = VSS).
300 3
300 0.3 -40C Rw 25C Rw 85C Rw 125C Rw
260

0.2
INL 125°C 85°C 125°C RW 2
220 85° 220
Error (LSb)
0.1
Error (LSb)
25°C
(ohms)
(ohms)
180 180
0 1
140 140
-0.1
100 DNL 100
RW 0
25°C
60 -0.2 60 INL
-40°C -40°C DNL
20 -0.3 20 -1
0 32 64 96 0 32 64 96
Temperature (VDD = 2.7V). (A = VDD, B = VSS). Temperature (VDD = 2.7V).(IW = 210 µA, B = VSS).
0.35 -40C Rw 25C Rw 85C Rw 125C Rw 39

-40C INL 25C INL 85C INL 125C INL 3000 -40C DNL 25C DNL 85C DNL 125C DNL 34
3000 0.25
-40C DNL 25C DNL 85C DNL 125C DNL

29
DNL 0.15
Error (LSb)
Error (LSb)
24
(ohms)
(ohms)
2000 0.05 2000

19
-0.05
INL 14
1000 INL -0.15 1000
RW 9
RW DNL
-0.25 4
0 -0.35 0 -1
0 32 64 96 0 32 64 96
Temperature (VDD = 1.8V). (A = VDD, B = VSS). Temperature (VDD = 1.8V). (IW =260 µA, B = VSS).

MCP40D17/18/19
0.0 100
Full-Scale Error (FSE) (LSb)
-0.1
-0.2 80 2.7V
RBW Tempco (PPM)

-0.3
-0.4 60
-0.5 5.5V
-0.6 2.7 40
-0.7 5.5V
-0.8 1.8V 20
-0.9
-1.0 0
-40 0 40 80 120 0 32 64 96
FIGURE 2-27: 10 kΩ : Full Scale Error FIGURE 2-30: 10 kΩ : RBW Tempco

0.9
0.8
0.7
0.6 1.8V
0.5
2.7
0.4
0.3
0.2 5.5V
0.1
0.0
-40 0 40 80 120
FIGURE 2-28: 10 kΩ : Zero Scale Error FIGURE 2-31: 10 kΩ : Power-Up Wiper

10200
10150
10100
Wiper
(Ohms)
1.8V
10050
VDD
10000
2.7
9950
5.5V
9900
-40 0 40 80 120
FIGURE 2-29: 10 kΩ : Nominal Resistance FIGURE 2-32: 10 kΩ : Digital Feedthrough


MCP40D17/18/19
FIGURE 2-33: 10 kΩ : Write Wiper FIGURE 2-36: 10 kΩ : Write Wiper




MCP40D17/18/19
120 0.3 120 -40C Rw 25C Rw 85C Rw 125C Rw

0.3
-40C DNL 25C DNL 85C DNL 125C DNL 0.2 0.2

-40C DNL 25C DNL 85C DNL 125C DNL
100 100
85°C 125°C 85°C 125°C
0.1 0.1
Error (LSb)
Error (LSb)
80 80
(ohms)
(ohms)
0 0
60 60 INL
DNL -0.1 DNL -0.1
INL RW -40°C
-40°C RW
40 25°C 40 25°C
-0.2 -0.2
20 -0.3 20 -0.3
0 32 64 96 0 32 64 96
Temperature (VDD = 5.5V). Temperature (VDD = 5.5V).(IW = 90 µA, B = VSS)
300 0.3
300 0.3 -40C Rw 25C Rw 85C Rw 125C Rw
260 0.2

0.2 125°C
85° 125°C 85°C INL
220 220
0.1
Error (LSb)
0.1
Error (LSb)
25°C
(ohms)
(ohms)
180 180
0 0
140 140
INL -0.1 -0.1
100 100 DNL RW
DNL RW
25°C -0.2 -0.2
60 60 -40°C
-40°C
20 -0.3 20 -0.3
0 32 64 96 0 32 64 96
Temperature (VDD = 2.7V). Temperature (VDD = 2.7V).(IW = 45 µA, B = VSS).
10000 0.35 10000 -40C Rw 25C Rw 85C Rw 125C Rw

23
-40C Rw 25C Rw 85C Rw 125C Rw -40C INL 25C INL 85C INL 125C INL 21
19
0.25
-40C DNL 25C DNL 85C DNL 125C DNL 8000

8000 17
0.15 RW
DNL 15
Error (LSb)
Error (LSb)
6000 INL
(ohms)
6000 13
(ohms)
0.05
11
4000 -0.05 4000 9
INL 7
-0.15 DNL 5
2000 2000
RW -0.25 3
1
0 -0.35 0 -1
0 32 64 96 0 32 64 96
Temperature (VDD = 1.8V). Temperature (VDD = 1.8V). (IW =260 µA, B = VSS).

MCP40D17/18/19
0.00
Full-Scale Error (FSE) (LSb) 100
80
RBW Tempco (PPM)

-0.04
60
-0.08 2.7V
2.7 5.5V 40
-0.12 5.5V
20
1.8V
-0.16 0
-40 0 40 80 120 0 32 64 96

0.20
0.16
1.8V
0.12
2.7
0.08
0.04
5.5V
0.00
-40 0 40 80 120

49800
49600
49400 Wiper
(Ohms)
VDD
49200 1.8V
49000 2.7V
5.5V
48800
-40 0 40 80 120
FIGURE 2-47: 50 kΩ : Nominal Resistance FIGURE 2-50: 50 kΩ : Digital Feedthrough


MCP40D17/18/19




MCP40D17/18/19
120 0.3 120 -40C Rw 25C Rw 85C Rw 125C Rw

0.3
0.2 0.2

100 125°C DNL 100 85°C 125°C DNL
85°C
0.1 0.1
Error (LSb)
Error (LSb)
80 80
(ohms)
(ohms)
0 0
60 60
INL -0.1 -0.1
RW -40°C RW
40 -40°C 25°C 40 25°C INL
-0.2 -0.2
20 -0.3 20 -0.3
0 32 64 96 0 32 64 96
FIGURE 2-57: 100 kΩ Pot Mode : RW (Ω), FIGURE 2-60: 100 kΩ Rheo Mode : RW
Temperature (VDD = 5.5V). Temperature (VDD = 5.5V). (IW = 45 µA, B = VSS).
300 0.3
300 0.3 -40C Rw 25C Rw 85C Rw 125C Rw
260 0.2

0.2 125°C
85°C
DNL 85° 125°C 220 INL
220 0.1
Error (LSb)
0.1
Error (LSb)
(ohms)
(ohms)
180 180
0 0
140 140
-0.1 DNL -0.1
100 100 RW
RW
INL
60 25°C -0.2 60 25°C -0.2
-40°C -40°C
20 -0.3 20 -0.3
0 32 64 96 0 32 64 96
FIGURE 2-58: 100 kΩ Pot Mode : RW (Ω), FIGURE 2-61: 100 kΩ Rheo Mode : RW
Temperature (VDD = 2.7V). Temperature (VDD = 2.7V). (IW = 21 µA, B = VSS).
15000 0.35 15000 -40C Rw 25C Rw 85C Rw 125C Rw

19
-40C INL 25C INL 85C INL 125C INL -40C DNL 25C DNL 85C DNL 125C DNL 17
12500
0.25

RW 15
DNL 0.15 10000 13
10000
Error (LSb)
Error (LSb)
INL
(ohms)
(ohms)
0.05 11
7500 7500 9
-0.05
7
5000 5000
-0.15 5
DNL 3
2500 INL -0.25 2500
RW 1
0 -0.35 0 -1
0 32 64 96 0 32 64 96
Temperature (VDD = 1.8V). Temperature (VDD = 1.8V). (IW =260 µA, B = VSS).

MCP40D17/18/19
0.00
100
Full-Scale Error (FSE) (LSb)
80
RBW Tempco (PPM)

-0.02
60
5.5V
-0.04
40 2.7V
2.7
-0.06
20
1.8V 5.5V
-0.08 0
-40 0 40 80 120 0 32 64 96
0.12
0.08
1.8V
2.7
0.04
5.5V
0.00
-40 0 40 80 120
99800
99600
99400
99200
99000 Wiper
(Ohms)
1.8V
98800
VDD
98600 2.7V
98400
98200
98000 5.5V
97800
-40 0 40 80 120
FIGURE 2-65: 100 kΩ : Nominal FIGURE 2-68: 100 kΩ : Digital

Resistance (Ω) vs. Temperature and VDD. Feedthrough (SCL signal coupling to Wiper pin).

MCP40D17/18/19
(40h → 3Fh) Settling Time (VDD = 5.5V). (FFh → 00h) Settling Time (VDD = 5.5V).

MCP40D17/18/19
4 0.3
3.5
5.5V 0.25
3 2.7V (@ 3mA)
0.2
2.5
VOL (mV)
VIH (V)
2.7V
2 0.15
5.5V (@ 3mA)
1.5
0.1
1 1.8V (@ 1mA)
0.05
0.5
1.8V
0 0
-40 0 40 80 120 -40 0 40 80 120
FIGURE 2-75: VIH (SCL, SDA) vs. VDD and FIGURE 2-77: VOL (SDA) vs. VDD and
Temperature. Temperature.
2 1.2
1 5.5
5.5V V
1.5
2.7V 0.8
VDD (V)
VIL (V)
1 0.6 2.7V
0.4
0.5 1.8V
0.2
0 0
-40 0 40 80 120 -40 0 40 80 120
FIGURE 2-76: VIL (SCL, SDA) vs. VDD and FIGURE 2-78: POR/BOR Trip point vs. VDD
Temperature. and Temperature.

MCP40D17/18/19
10 10
Code = 7Fh Code = 7Fh
0 0
Code = 3Fh Code = 3Fh
-10
-10 Code = 1Fh
-20
dB
dB
-20 Code = 0Fh
Code = 0Fh Code = 1Fh -30
-30 Code = 01h
Code = 01h -40
-40 -50
-50 -60
100 1,000 10,000 100 1,000 10,000
Frequency (kHz) Frequency (kHz)
FIGURE 2-79: 5 kΩ – Gain vs. Frequency FIGURE 2-82: 100 kΩ – Gain vs.
(-3 dB). Frequency (-3 dB).
10
2.1 Test Circuits
Code = 7Fh
0
Code = 3Fh
-10 +5V
+5V
-20
dB
Code = 0Fh
-30 Code = 1Fh
VIN A
Code = 01h W + VOUT
-40
-50 B -
-60
100 1,000 10,000
Frequency (kHz)
FIGURE 2-80: 10 kΩ – Gain vs. Frequency

(-3 dB). FIGURE 2-83: Gain vs. Frequency Test
(-3 dB).
10
Code = 7Fh
0
-10 Code = 3Fh
-20 Code = 1Fh

dB
Code = 0Fh
-30
Code = 01h
-40
-50
-60
100 1,000 10,000
Frequency (kHz)
FIGURE 2-81: 50 kΩ – Gain vs. Frequency

(-3 dB).

MCP40D17/18/19
NOTES:

MCP40D17/18/19
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
Additional descriptions of the device pins follow.
TABLE 3-1: PINOUT DESCRIPTION FOR THE MCP40D17/18/19

Pin Number
Pin Pin Buffer
MCP40D17 MCP40D18 MCP40D19 Function
Name Type Type
(SC70-6) (SC70-6) (SC70-5)
VDD 1 1 1 P — Positive Power Supply Input
VSS 2 2 2 P — Ground
SCL 3 3 3 I/O ST (OD) I2C Serial Clock pin
SDA 4 4 4 I/O ST (OD) I2C Serial Data pin
B 5 — — I/O A Potentiometer Terminal B
W 6 5 5 I/O A Potentiometer Wiper Terminal
A — 6 — I/O A Potentiometer Terminal A
Legend: A = Analog input ST (OD) = Schmitt Trigger with Open Drain
I = Input O = Output I/O = Input/Output P = Power

MCP40D17/18/19
3.1 Positive Power Supply Input (VDD) 3.6 Potentiometer Wiper (W) Terminal
The VDD pin is the device’s positive power supply input. The terminal W pin is connected to the internal
The input power supply is relative to VSS and can range potentiometer’s terminal W (the wiper). The wiper
from 1.8V to 5.5V. A de-coupling capacitor on VDD terminal is the adjustable terminal of the digital
(to VSS) is recommended to achieve maximum potentiometer. The terminal W pin does not have a
performance. polarity relative to terminals A or B pins. The terminal
While the device’s voltage is in the range of W pin can support both positive and negative current.
1.8V ≤ VDD < 2.7V, the Resistor Network’s electrical The voltage on terminal W must be between VSS and
performance of the device may not meet the data sheet VDD.
specifications.
3.7 Potentiometer Terminal A
3.2 Ground (VSS) The terminal A pin (available on some devices) is
The VSS pin is the device ground reference. connected to the internal potentiometer’s terminal A.
The potentiometer’s terminal A is the fixed connection
3.3 I2C Serial Clock (SCL) to the Full Scale (0x7F tap) wiper value of the digital
potentiometer.
The SCL pin is the serial clock pin of the I2C interface.
The terminal A pin is available on the MCP40D18
The MCP40D17/18/19 acts only as a slave and the
devices. The terminal A pin does not have a polarity
SCL pin accepts only external serial clocks. The SCL
relative to the terminal W pin. The terminal A pin can
pin is an open-drain output. Refer to Section 5.0
support both positive and negative current. The voltage
“Serial Interface - I2C Module” for more details of I2C
on terminal A must be between VSS and VDD.
Serial Interface communication.
The terminal A pin is not available on the MCP40D17
3.4 I2C Serial Data (SDA) and MCP40D19 devices. For these devices, the
potentiometer’s terminal A is internally floating.
The SDA pin is the serial data pin of the I2C interface.
The SDA pin has a Schmitt trigger input and an
open-drain output. Refer to Section 5.0 “Serial
Interface - I2C Module” for more details of I2C Serial
Interface communication.
3.5 Potentiometer Terminal B

The terminal B pin (available on some devices) is
connected to the internal potentiometer’s terminal B.
The potentiometer’s terminal B is the fixed connection
to the Zero Scale (0x00 tap) wiper value of the digital
potentiometer.
The terminal B pin is available on the MCP40D17
device. The terminal B pin does not have a polarity
relative to the terminal W pin. The terminal B pin can
support both positive and negative current. The voltage
on terminal B must be between VSS and VDD.
The terminal B pin is not available on the MCP40D18
and MCP40D19 devices. For these devices, the
potentiometer’s terminal B is internally connected to
VSS.

MCP40D17/18/19
4.0 GENERAL OVERVIEW 4.1.1 POWER-ON RESET
The MCP40D17/18/19 devices are general purpose When the device powers up, the device VDD will cross
digital potentiometers intended to be used in the VPOR/VBOR voltage. Once the VDD voltage crosses
applications where a programmable resistance with the VPOR/VBOR voltage, the following happens:
moderate bandwidth is desired. • Volatile wiper register is loaded with the default
This Data Sheet covers a family of three Digital wiper value (3Fh)
Potentiometer and Rheostat devices. The MCP40D18 • The device is capable of digital operation
device is the Potentiometer configuration, while the
MCP40D17 and MCP40D19 devices are the Rheostat 4.1.2 BROWN-OUT RESET
configuration. When the device powers down, the device VDD will
Applications generally suited for the MCP40D17/18/19 cross the VPOR/VBOR voltage. Once the VDD voltage
devices include: decreases below the VPOR/VBOR voltage the following
happens:
• Computer Servers
• Serial Interface is disabled
• Set point or offset trimming
• Sensor calibration If the VDD voltage decreases below the VRAM voltage
the following happens:
• Selectable gain and offset amplifier designs
• Cost-sensitive mechanical trim pot replacement • Volatile wiper registers may become corrupted
As the Device Block Diagram shows, there are four As the voltage recovers above the VPOR/VBOR voltage
main functional blocks. These are: see Section 4.1.1 “Power-on Reset”.
• POR/BOR Operation Serial commands not completed due to a Brown-out

condition may cause the memory location to become
• Serial Interface - I2C Module
corrupted.
• Resistor Network
The POR/BOR operation and the Memory Map are 4.1.3 WIPER REGISTER (RAM)
discussed in this section and the I2C and Resistor The Wiper Register is volatile memory that starts
Network operation are described in their own sections. functioning at the RAM retention voltage (VRAM). The
The Serial Commands commands are discussed in Wiper Register will be loaded with the default wiper
Section 5.4. value when VDD will rise above the VPOR/VBOR voltage.
4.1 POR/BOR Operation 4.1.4 DEVICE CURRENTS

The Power-on Reset is the case where the device is The current of the device can be classified into two
having power applied to it from VSS. The Brown-out modes of the device operation. These are:
Reset occurs when a device had power applied to it, • Serial Interface Inactive (Static Operation)
and that power (voltage) drops below the specified • Serial Interface Active
range.
Static Operation occurs when a Stop condition is
The devices RAM retention voltage (VRAM) is lower received. Static Operation is exited when a Start
than the POR/BOR voltage trip point (VPOR/VBOR). The condition is received.
maximum VPOR/VBOR voltage is less than 1.8V.
When VPOR/VBOR < VDD < 2.7V, the Resistor Network’s
electrical performance may not meet the data sheet
specifications. In this region, the device is capable of
reading and writing to its volatile memory if the proper
serial command is executed.
Table 4-1 shows the digital pot’s level of functionality
across the entire VDD range, while Figure 4-1 illustrates
the Power-up and Brown-out functionality.

MCP40D17/18/19
TABLE 4-1: DEVICE FUNCTIONALITY AT EACH VDD REGION (NOTE 1)
Serial Potentiometer
VDD Level Wiper Setting Comment
Interface Terminals
VDD < VBOR < 1.8V Ignored “unknown” Unknown
VBOR ≤ VDD < 1.8V “Unknown” Operational with Wiper Register loaded
reduced electrical with POR/BOR value
specs
1.8V ≤ VDD < 2.7V Accepted Operational with Wiper Register Electrical performance may not
reduced electrical determines Wiper meet the data sheet specifications.
specs Setting
2.7V ≤ VDD ≤ 5.5V Accepted Operational Wiper Register Meets the data sheet specifications
determines Wiper
Setting
Note 1: For system voltages below the minimum operating voltage, the customer will be recommended to use a
voltage supervisor to hold the system in reset. This will ensure that MCP4017/18/19 commands are not
attempted out of the operating range of the device.
Normal Operation Range Normal Operation Range

VDD Outside Specified
AC/DC Range
2.7V
1.8V
VPOR/BOR
VRAM
VSS
Analog Analog
Characteristics Characteristics not specified
not specified Device’s Serial
Interface is VBOR Delay
“Not Operational” Wiper Forced to Default POR/BOR setting
FIGURE 4-1: Power-up and Brown-out.

MCP40D17/18/19
5.0 SERIAL INTERFACE - 5.1 I2C I/O Considerations
I2C MODULE I2C specifications require active low, passive high
A 2-wire I2C serial protocol is used to write or read the functionality on devices interfacing to the bus. Since
digital potentiometer’s wiper register. The I2C protocol devices may be operating on separate power supply
utilizes the SCL input pin and SDA input/output pin. sources, ESD clamping diodes are not permitted. The
specification recommends using open drain transistors
The I2C serial interface supports the following features: tied to VSS (common) with a pull-up resistor. The
• Slave mode of operation specification makes some general recommendations
• 7-bit addressing on the size of this pull-up, but does not specify the
exact value since bus speeds and bus capacitance
• The following clock rate modes are supported:
impacts the pull-up value for optimum system
- Standard mode, bit rates up to 100 kb/s performance.
- Fast mode, bit rates up to 400 kb/s
Common pull-up values range from 1 kΩ to a maximum
• Support Multi-Master Applications of ~10 kΩ. Power sensitive applications tend to choose
The serial clock is generated by the Master. higher values to minimize current losses during
The I2C Module is compatible with the Phillips I2C communication but these applications also typically
specification. Philips only defines the field types, field utilize lower VDD.
lengths, timings, etc. of a frame. The frame content The SDA and SCL float (are not driving) when the
defines the behavior of the device. The frame content device is powered down.
for the MCP40D17, MCP40D18, and MCP40D19 A "glitch" filter is on the SCL and SDA pins when the pin
devices are defined in this section of the data sheet. is an input. When these pins are an output, there is a
Figure 5-1 shows a typical I2C bus configurations. slew rate control of the pin that is independent of device
frequency.
Single I2C Bus Configuration 5.1.1 SLOPE CONTROL

The device implements slope control on the SDA
Device 1 Device 3 Device n output. The slope control is defined by the fast mode
Host specifications.
Controller For Fast (FS) mode, the device has spike suppression
and Schmidt trigger inputs on the SDA and SCL pins.
Device 2 Device 4
FIGURE 5-1: Typical Application I2C Bus

Configurations.
Refer to Section 2.0 “Typical Performance Curves”,
AC/DC Electrical Characteristics table for detailed input
threshold and timing specifications.

MCP40D17/18/19
5.2 I2C Bit Definitions If the Slave Address is not valid, the Slave Device will
issue a Not A (A). The A bit will have the SDA signal
I2C bit definitions include: high.
• Start Bit If an error condition occurs (such as an A instead of A)
• Data Bit then a START bit must be issued to reset the command
• Acknowledge (A) Bit state machine.
• Repeated Start Bit
• Stop Bit TABLE 5-1: MCP40D17/18/19 A / A
• Clock Stretching RESPONSES
Figure 5-8 shows the waveform for these states. Acknowledge
Event Comment
Bit Response
5.2.1 START BIT
General Call A
The Start bit (see Figure 5-2) indicates the beginning of
Slave Address A
a data transfer sequence. The Start bit is defined as the
valid
SDA signal falling when the SCL signal is “High”.
Slave Address A
not valid
SDA 1st Bit 2nd Bit Bus Collision N.A. I2C Module Resets,
or a “Don’t Care” if
SCL the collision occurs
S on the Masters
“Start bit”.
FIGURE 5-2: Start Bit.
5.2.4 REPEATED START BIT
5.2.2 DATA BIT
The Repeated Start bit (see Figure 5-5) indicates
The SDA signal may change state while the SCL signal the current Master Device wishes to continue
is Low. While the SCL signal is High, the SDA signal communicating with the current Slave Device without
MUST be stable (see Figure 5-3). releasing the I2C bus. The Repeated Start condition is
the same as the Start condition, except that the
Repeated Start bit follows a Start bit (with the Data bits
1st Bit 2nd Bit + A bit) and not a Stop bit.
SDA
The Start bit is the beginning of a data transfer
SCL sequence and is defined as the SDA signal falling when
S the SCL signal is “High”.
FIGURE 5-3: Data Bit. Note 1: A bus collision during the Repeated Start
condition occurs if:
5.2.3 ACKNOWLEDGE (A) BIT
• SDA is sampled low when SCL goes
The A bit (see Figure 5-4) is a response from the Slave from low to high.
device to the Master device. Depending on the context
• SCL goes low before SDA is
of the transfer sequence, the A bit may indicate
asserted low. This may indicate that
different things. Typically the Slave device will supply
another master is attempting to
an A response after the Start bit and 8 “data” bits have
transmit a data "1".
been received. The A bit will have the SDA signal low.
SDA D0 A
SDA 1st Bit
SCL 8 9
FIGURE 5-4: Acknowledge Waveform. SCL
Sr = Repeated Start
FIGURE 5-5: Repeat Start Condition
Waveform.

MCP40D17/18/19
5.2.5 STOP BIT 5.2.7 ABORTING A TRANSMISSION
The Stop bit (see Figure 5-6) Indicates the end of the If any part of the I2C transmission does not meet the
I2C Data Transfer Sequence. The Stop bit is defined as command format, it is aborted. This can be intentionally
the SDA signal rising when the SCL signal is “High”. accomplished with a START or STOP condition. This is
A Stop bit resets the I2C interface of the other devices. done so that noisy transmissions (usually an extra
START or STOP condition) are aborted before they
corrupt the device.
SDA A / A
5.2.8 IGNORING AN I2C TRANSMISSION
SCL AND “FALLING OFF” THE BUS
The MCP40D17/18/19 expects to receive entire, valid
P I2C commands and will assume any command not
defined as a valid command is due to a bus corruption
FIGURE 5-6: Stop Condition Receive or
and will enter a passive high condition on the SDA
Transmit Mode.
signal. All signals will be ignored until the next valid
START condition and CONTROL BYTE are received.
5.2.6 CLOCK STRETCHING
“Clock Stretching” is something that the Secondary
Device can do, to allow additional time to “respond” to
the “data” that has been received.
The MCP40D17/18/19 will not strech the clock signal
(SCL) since memory read accesses occur fast enough.
SDA
SCL
S 1st 2nd 3rd 4th 5th 6th 7th 8th A/A 1st 2nd 3rd 4th 5th 6th 7th 8th A/A P
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
FIGURE 5-7: Typical 16-bit I2C Waveform Format.
SDA
SCL
START Data allowed Data or STOP

Condition to change A valid Condition
FIGURE 5-8: I2C Data States and Bit Sequence.

MCP40D17/18/19
5.2.9 I2C COMMAND PROTOCOL TABLE 5-2: DEVICE I2C ADDRESS
The MCP40D17/18/19 is a slave I2C device which Device I2C Address Comment
supports 7-bit slave addressing. The slave address MCP40D17 ‘0101110’
contains seven fixed bits. Figure 5-9 shows the control
‘0101110’ MCP40D18-xxxE/LT
byte format. MCP40D18
‘0111110’ MCP40D18-xxxAE/LT
5.2.9.1 Control Byte (Slave Address) MCP40D19 ‘0101110’
The Control Byte is always preceded by a START
condition. The Control Byte contains the slave address 5.2.9.2 Hardware Address Pins
consisting of seven fixed bits and the R/W bit. Figure 5- The MCP40D17/MCP40D18/MCP40D19 does not
9 shows the control byte format and Table 5-2 shows support hardware address bits.
the I2C address for the devices.
5.2.10 GENERAL CALL
All devices are offered with the I2C slave address of
“0101110”, while the MCP40D18 also offers a second The General Call is a method that the Master device
standard I2C slave address of “0111110”. can communicate with all other Slave devices.
The MCP40D17/18/19 devices do not respond to
Slave Address General Call address and commands, and therefore
the communications are Not Acknowledged.
S A6 A5 A4 A3 A2 A1 A0 R/W A/A
“0” “1” “0” “1” “1” “1” “0”
Start R/W bit

bit R/W = 0 = write
R/W = 1 = read
A bit (controlled by slave device)
A = 0 = Slave Device Acknowledges byte
A = 1 = Slave Device does not Acknowledge byte
FIGURE 5-9: Slave Address Bits in the
I2C Control Byte (Slave Address = “0101110”).
Second Byte
S 0 0 0 0 0 0 0 0 A X X X X X X X 0 A P
General Call Address “7-bit Command”

Reserved 7-bit Commands (By I2C Specification - Philips # 9398 393 40011, Ver. 2.1 January 2000)
“0000 011”b - Reset and write programmable part of slave address by hardware
“0000 010”b - Write programmable part of slave address by hardware
“0000 000”b - NOT Allowed
The Following is a “Hardware General Call” Format
Second Byte n occurrences of (Data + A / A)
S 0 0 0 0 0 0 0 0 A X X X X X X X 1 A X X X X X X X X A P
General Call Address “7-bit Command” This indicates a “Hardware General Call”
MCP40D17/18/19 will ignore this byte and
all following bytes (and A), until a Stop bit
(P) is encountered.
FIGURE 5-10: General Call Formats.

MCP40D17/18/19
5.3 Software Reset Sequence The Stop bit terminates the current I2C bus activity.
The MCP40D17/18/19 wait to detect the next Start
Note: This technique should be supported by condition.
any I2C compliant device. The 24XXXX
This sequence does not effect any other I2C devices
I2C Serial EEPROM devices support this
which may be on the bus, as they should disregard this
technique, which is documented in
as an invalid command.
AN1028.
At times it may become necessary to perform a 5.4 Serial Commands

Software Reset Sequence to ensure the MCP40D17/
18/19 device is in a correct and known I2C Interface The MCP40D17/18/19 devices support 2 serial
state. This only resets the I2C state machine. commands. These commands are:
This is useful if the MCP40D17/18/19 device powers up • Write Operation

in an incorrect state (due to excessive bus noise, etc), • Read Operations
or if the Master Device is reset during communication. The I2C command formats have been defined so to
Figure 5-11 shows the communication sequence to support the SMBus version 2.0 Write Byte/Word
software reset the device. Protocol formats and Read Byte/Word Protocol
formats. The SMBus specification defines this
operation is Section 5 of the Version 2.0 document
S ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ S P (August 3, 2000).
This protocol format may be convienient for customers
Nine bits of ‘1’ using library routines for the I2C bus, where all they
need to do is specify the command (read, write, ...) with
Start bit
Start the Device Address, the Register Address, and the
bit Stop bit Data.
If higher data throughput is desired, please look at the
FIGURE 5-11: Software Reset Sequence
MCP4017/18/19 devices which have a simplier I2C
Format. command format.
The 1st Start bit will cause the device to reset from a
state in which it is expecting to receive data from the
Master Device. In this mode, the device is monitoring
the data bus in Receive mode and can detect the Start
bit forces an internal Reset.
The nine bits of ‘1’ are used to force a Reset of those
devices that could not be reset by the previous Start bit.
This occurs only if the MCP40D17/18/19 is driving an A
on the I2C bus, or is in output mode (from a Read
command) and is driving a data bit of ‘0’ onto the I2C
bus. In both of these cases, the previous Start bit could
not be generated due to the MCP40D17/18/19 holding
the bus low. By sending out nine ‘1’ bits, it is ensured
that the device will see a A (the Master Device does not
drive the I2C bus low to acknowledge the data sent by
the MCP40D17/18/19), which also forces the
MCP40D17/18/19 to reset.
The 2nd Start bit is sent to address the rare possibility
of an erroneous write. This could occur if the Master
Device was reset while sending a Write command to
the MCP40D17/18/19, AND then as the Master Device
returns to normal operation and issues a Start condition
while the MCP40D17/18/19 is issuing an A. In this case
if the 2nd Start bit is not sent (and the Stop bit was sent)
the MCP40D17/18/19 could initiate a write cycle.
Note: The potential for this erroneous write
ONLY occurs if the Master Device is reset
while sending a Write command to the
MCP40D17/18/19.

MCP40D17/18/19
5.4.1 WRITE OPERATION 5.4.2 READ OPERATIONS
The write operation requires the START condition, The read operation requires the START condition,
Control Byte, Acknowledge, Command Code, Control Byte, Acknowledge, Command Code,
Acknowledge, Data Byte, Acknowledge and STOP (or Acknowledge, Restart Condition, Control Byte,
RESTART) condition. The Control (Slave Address) Acknowledge, Data Byte, the master generating the
Byte requires the R/W bit equal to a logic zero (R/W = A and STOP (or RESTART) condition. The first Control
“0”) to generate a write sequence. The MCP40D17/ Byte requires the R/W bit equal to a logic zero (R/W =
18/19 is responsible for generating the Acknowledge “0”) to write the Command Code, while the second
(A) bits. Control Byte requires the R/W bit equal to a logic one
(R/W = “1”) to generate a read sequence. The
Data is written to the MCP40D17/18/19 after every byte MCP40D17/18/19 will A the Slave Address Byte and A
transfer (during the A bit). If a STOP or RESTART all the Data Bytes. The I2C Master will A the Slave
condition is generated during a data transfer (before Address Byte and the last Data Byte. If there are
the A bit), the data will not be written to MCP40D17/18/ multiple Data Bytes, the I2C Master will A all Data Bytes
19. except the last Data Byte (which it will A).
Data bytes may be written after each Acknowledge. The MCP40D17/18/19 maintains control of the SDA
The command is terminated once a Stop (P) condition signal until all data bits have been clocked out.
occurs. Refer to Figure 5-12 for the single byte write
sequence and Figure 5-13 for the generic (multi-byte) The command is terminated once a Stop (P) or Restart
write sequence. For a single byte write, the master (S) condition occurs. Refer to Figure 5-15 for the read
sends a STOP or RESTART condition after the 1st data command sequence. For a single read, the master
byte is sent. sends a STOP or RESTART condition after the 1st data
byte (and A bit) is sent from the slave.
The MSb of each Data Byte is a don’t care, since the
wiper register is only 7-bits wide. Figure 5-16 shows the I2C read communication
behavior of the Master Device and the MCP40D17/18/
The command is terminated once a Stop (P) or Restart 19 device and the resultant I2C bus values.
(S) condition occurs.
Figure 5-14 shows the I2C write communication Note: A command code with a non-zero value
behavior of the Master Device and the MCP40D17/18/ will cause the data not to be read from the
19 device and the resultant I2C bus values. wiper register
Note: A command code with a non-zero value

will cause the data not to be written to the
wiper register
Fixed
Read/Write bit (“0” = Write) STOP bit
Address
S 0 1 0 1 1 1 0 0 A 0 0 0 0 0 0 0 0 A X D6 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Command Code Data Byte
Legend
S = Start Condition
P = Stop Condition
A = Acknowledge
X = Don’t Care
R/W = Read/Write bit
D6:D0 = Data bits
FIGURE 5-12: I2C Single Byte Write Command Format (Slave Address = “0101110”).

MCP40D17/18/19
Fixed
Read/Write bit (“0” = Write)
Address
S 0 1 0 1 1 1 1 0 A 0 0 0 0 0 0 0 0 A X D6 D5 D4 D3 D2 D1 D0 A
Slave Address Byte Command Code Data Byte
STOP bit
X D6 D5 D4 D3 D2 D1 D0 A X D6 D5 D4 D3 D2 D1 D0 A P
Data Byte Data Byte

Legend
S = Start Condition
P = Stop Condition
A = Acknowledge
X = Don’t Care
R/W = Read/Write bit
D6:D0 = Data bits
FIGURE 5-13: I2C Write Command Format (Slave Address = “0101110”).
Write 1 Byte with Command Code = 00h

R A A A
/ C C C
S Slave Address W K Command Code K Data Byte K P
Master S 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 0 d d d d d d d 1 P
MCP40D17/18/19 0 0 0
I2C Bus S 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 d d d d d d d 0 P
Write 2 Byte with Command Code = 00h
R A A A
/ C C C
S Slave Address W K Command Code K Data Byte K
Master S 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 0 d d d d d d d 1
MCP40D17/18/19 0 0 0
I2C Bus S 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 d d d d d d d 0
A
C
Data Byte K P
Master 0 d d d d d d d 1 P
MCP40D17/18/19 0
I2C Bus 0 d d d d d d d 0 P
FIGURE 5-14: I2C Write Communication Behavior (Slave Address = “0101110”).

MCP40D17/18/19
Read/Write bit (“0” = Write)
S 0 1 0 1 1 1 0 0 A 0 0 0 0 0 0 0 0 A Legend
S = Start Condition
Slave Address Byte Command Code P = Stop Condition
STOP bit
Read/Write bit (“1” = Read) A = Acknowledge
X = Don’t Care
S 0 1 0 1 1 1 0 1 A 0 D6 D5 D4 D3 D2 D1 D0 A(2) P R/W = Read/Write bit
D6:D0 = Data bits
Slave Address Byte Data Byte
Note 1: Master Device is responsible for ACK / NACK signal. If a NACK signal occurs, the MCP40D17/18/19 will
abort this transfer and release the bus.
2: The Master Device will Not ACK, and the MCP40D17/18/19 will release the bus so the Master Device can
generate a Stop or Repeated Start condition.
FIGURE 5-15: I2C Read Command Format (Slave Address = “0101110”).
Read 1 Byte with Command Code = 00h

R A A R A
/ C C R / C
S Slave Address W K Command Code K S Slave Address WK
Master S 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 S 0 1 0 1 1 1 0 1 1
MCP40D17/18/19 0 0 0
I2C Bus S 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 S 0 1 0 1 1 1 0 1 0
A
C
Data Byte K P
Master 1 P
MCP40D17/18/19 0 d d d d d d d 1
I2C Bus 0 d d d d d d d 1 P
Read 2 Byte with Command Code = 00h
R A A R A
/ C C R / C
S Slave Address W K Command Code K S Slave Address WK
Master S 0 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 S 0 1 0 1 1 1 0 1 1
MCP40D17/18/19 0 0 0
I2C Bus S 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 S 0 1 0 1 1 1 0 1 0
A A
C C
Data Byte K Data Byte K P
Master 0 1 P
MCP40D17/18/19 0 d d d d d d d 1 0 d d d d d d d 1
I2C Bus 0 d d d d d d d 0 0 d d d d d d d 1 P
FIGURE 5-16: I2C Read Communication Behavior (Slave Address = “0101110”).

MCP40D17/18/19
6.0 RESISTOR NETWORK
A
The Resistor Network is made up of two parts. These
N = 127 7Fh
are:
(1)
RW
• Resistor Ladder RS
• Wiper
N = 126 7Eh
Figure 6-1 shows a block diagram for the resistive (1)
network. RS RW
Digital potentiometer applications can be divided into N = 125 7Dh

two resistor network categories: RW (1)
RS
• Rheostat configuration
• Potentiometer (or voltage divider) configuration
The MCP40D17 is a true rheostat, with terminal B and W
the wiper (W) of the variable resistor available on pins.
N=1 01h
The MCP40D18 device offers a voltage divider
(1)
(potentiometer) with terminal B internally connected to RS RW
ground.
N=0 00h
The MCP40D19 device is a Rheostat device with
(1)
terminal A of the resistor floating, terminal B internally RW
connected to ground, and the wiper (W) available on B Analog
pin. Mux
Note 1: The wiper resistance is tap dependent.
6.1 Resistor Ladder Module That is, each tap selection resistance
The resistor ladder is a series of equal value resistors has a small variation. This variation has
(RS) with a connection point (tap) between the two more effect on devices with smaller RAB
resistors. The total number of resistors in the resistance (5.0 kΩ).
series (ladder) determines the RAB resistance
FIGURE 6-1: Resistor Network Block
(see Figure 6-1). The end points of the resistor ladder
are connected to the device Terminal A and Terminal B Diagram.
pins. The RAB (and RS) resistance has small variations
over voltage and temperature. TABLE 6-1: WIPER SETTING MAP
The Resistor Network has 127 resistors in a string Wiper Setting Properties
between terminal A and terminal B. This gives 7-bits of 07Fh Full Scale (W = A)
resolution. 07Eh - 040h W=N
The wiper can be set to tap onto any of these 127 03Fh W = N (Mid Scale)
resistors thus providing 128 possible settings 03Eh - 001h W=N
(including terminal A and terminal B). This allows zero
000h Zero Scale (W = B)
scale to full scale connections.
A wiper setting of 00h connects the Terminal W (wiper)
to Terminal B (Zero Scale). A wiper setting of 3Fh is the
Mid scale setting. A wiper setting of 7Fh connects
the Terminal W (wiper) to Terminal A (Full Scale).
Table 6-1 illustrates the full wiper setting map.
Terminal A and B as well as the wiper W do not have a
polarity. These terminals can support both positive and
negative current.

MCP40D17/18/19
Step resistance (RS) is the resistance from one tap A POR/BOR event will load the Volatile Wiper register
setting to the next. This value will be dependent on the value with the default value. Table 6-3 shows the
RAB value that has been selected. Equation 6-1 shows default values offered.
the calculation for the step resistance while Table 6-2
shows the typical step resistances for each device. TABLE 6-3: DEFAULT FACTORY
SETTINGS SELECTION
EQUATION 6-1: RS CALCULATION
Resistance Typical Default POR Wiper
R AB Code RAB Value
R S = --------- Setting Code (1)
127
-502 5.0 kΩ Mid-scale 3Fh
Equation 6-2 illustrates the calculation used to -103 10.0 kΩ Mid-scale 3Fh
determine the resistance between the wiper and -503 50.0 kΩ Mid-scale 3Fh
terminal B.
-104 100.0 kΩ Mid-scale 3Fh
EQUATION 6-2: RWB CALCULATION Note 1: Custom POR/BOR Wiper Setting options
are available, contact the local Microchip
R AB N Sales Office for additional information.
R WB = -------------
- + RW
127 Custom options have minimum volume
N = 0 to 127 (decimal) requirements.
The digital potentiometer is available in four nominal

resistances (RAB) where the nominal resistance is
defined as the resistance between terminal A and
terminal B. The four nominal resistances are 5 kΩ,
10 kΩ, 50 kΩ, and 100 kΩ.
The total resistance of the device has minimal variation
due to operating voltage (see Figure 2-11, Figure 2-29,
Figure 2-47, or Figure 2-65).
TABLE 6-2: STEP RESISTANCES

Resistance (Ω)
Part Number Total
Case Step (RS)
(RAB)
Minimum 4000 31.496
MCP40D17/18/19-
Typical 5000 39.370
502
Maximum 6000 47.244
Minimum 8000 62.992
MCP40D17/18/19-
Typical 10000 78.740
103
Maximum 12000 94.488
Minimum 40000 314.961
MCP40D17/18/19-
Typical 50000 393.701
503
Maximum 60000 472.441
Minimum 80000 629.921
MCP40D17/18/19-
Typical 100000 787.402
104
Maximum 120000 944.882

MCP40D17/18/19
6.2 Resistor Configurations 6.2.2 POTENTIOMETER
CONFIGURATION
6.2.1 RHEOSTAT CONFIGURATION
When used as a potentiometer, all three terminals of
When used as a rheostat, two of the three digital the device are tied to different nodes in the circuit. This
potentiometer’s terminals are used as a resistive allows the potentiometer to output a voltage
element in the circuit. With terminal W (wiper) and proportional to the input voltage. This configuration is
either terminal A or terminal B, a variable resistor is sometimes called voltage divider mode. The
created. The resistance will depend on the tap setting potentiometer is used to provide a variable voltage by
of the wiper (and the wiper’s resistance). The adjusting the wiper position between the two endpoints
resistance is controlled by changing the wiper setting as shown in Figure 6-3. Reversing the polarity of the A
The unused terminal (B or A) should be left floating. and B terminals will not affect operation.
Figure 6-2 shows the two possible resistors that can be
used. Reversing the polarity of the A and B terminals
V1
will not affect operation.
W V3
A
B
W RAW or RBW
V2
B
FIGURE 6-3: Potentiometer
Configuration.
Resistor
The temperature coefficient of the RAB resistors is
FIGURE 6-2: Rheostat Configuration. minimal by design. In this configuration, the resistors all
change uniformly, so minimal variation should be seen.
This allows the control of the total resistance between
the two nodes. The total resistance depends on the The Wiper resistor temperature coefficient is different
“starting” terminal to the Wiper terminal. So at the code to the RAB temperature coefficient. The voltage at node
00h, the RBW resistance is minimal (RW), but the RAW V3 (Figure 6-3) is not dependent on this Wiper
resistance in maximized (RAB + RW). Conversely, at the resistance, just the ratio of the RAB resistors, so this
code 3Fh, the RAW resistance is minimal (RW), but the temperature coefficient in most cases can be ignored.
RBW resistance in maximized (RAB + RW).
The resistance Step size (RS) equates to one LSb of Note: To avoid damage to the internal wiper
the resistor. circuitry in this configuration, care should
be taken to insure the current flow never
exceeds 2.5 mA.
Note: To avoid damage to the internal wiper
circuitry in this configuration, care should
be taken to insure the current flow never
exceeds 2.5 mA.
The pinout for the rheostat devices is such that as the

wiper register is incremented, the resistance of the
resistor will increase (as measured from Terminal B to
the W Terminal).

MCP40D17/18/19
6.3 Wiper Resistance In a potentiometer configuration, the wiper resistance
variation does not effect the output voltage seen on the
Wiper resistance is the series resistance of the analog W pin.
switch that connects the selected resistor ladder node
to the Wiper Terminal common signal (see Figure 6-1). The slope of the resistance has a linear area (at the
higher voltages) and a non-linear area (at the lower
A value in the volatile wiper register selects which voltages). In where resistance increases faster than the
analog switch to close, connecting the W terminal to voltage drop (at low voltages).
the selected node of the resistor ladder.
The resistance is dependent on the voltages on the
analog switch source, gate, and drain nodes, as well as
the device’s wiper code, temperature, and the current
through the switch. As the device voltage decreases,
the wiper resistance increases (see Figure 6-4 and RW
Table 6-4).
The wiper can connect directly to Terminal B or to
Terminal A. A zero scale connections, connects the
Terminal W (wiper) to Terminal B (wiper setting of
000h). A full scale connections, connects the
VDD
Terminal W (wiper) to Terminal A (wiper setting of 7Fh).
In these configurations the only resistance between the Note: The slope of the resistance has a linear
Terminal W and the other Terminal (A or B) is thaΩt of area (at the higher voltages) and a non-
the analog switches. linear area (at the lower voltages).
The wiper resistance is typically measured when the FIGURE 6-4: Relationship of Wiper
wiper is positioned at either zero scale (00h) or full Resistance (RW) to Voltage.
scale (3Fh).
Since there is minimal variation of the total device
The wiper resistance in potentiometer-generated
resistance over voltage, at a constant temperature (see
voltage divider applications is not a significant source
Figure 2-11, Figure 2-29, Figure 2-47, or Figure 2-65),
of error.
the change in wiper resistance over voltage can have a
The wiper resistance in rheostat applications can significant impact on the INL and DNL error.
create significant nonlinearity as the wiper is moved
toward zero scale (00h). The lower the nominal
resistance, the greater the possible error.
In a rheostat configuration, this change in voltage
needs to be taken into account. Particularly for the
lower resistance devices. For the 5.0 kΩ device the
maximum wiper resistance at 5.5V is approximately
3.2% of the total resistance, while at 2.7V it is
approximately 6.5% of the total resistance.
TABLE 6-4: TYPICAL STEP RESISTANCES AND RELATIONSHIP TO WIPER RESISTANCE

Resistance (?) RW / RS (%) ( 1) RW / RAB (%) ( 2)
Typical Wiper (RW)

RW = RW = Max RW = Max RW = RW = Max RW = Max
Total Step Max @ Max @ Typical @ 5.5V @ 2.7V Typical @ 5.5V @ 2.7V
Typical
(RAB) (RS) 5.5V 2.7V
5000 39.37 100 170 325 254.00% 431.80% 825.5% 2.00% 3.40% 6.50%
10000 78.74 100 170 325 127.00% 215.90% 412.75% 1.00% 1.70% 3.25%
50000 393.70 100 170 325 25.40% 43.18% 82.55% 0.20% 0.34% 0.65%
100000 787.40 100 170 325 12.70% 21.59% 41.28% 0.10% 0.17% 0.325%
Note 1: RS is the typical value. The variation of this resistance is minimal over voltage.
2: RAB is the typical value. The variation of this resistance is minimal over voltage.

MCP40D17/18/19
6.4 Operational Characteristics 6.4.1.2 Differential Non-linearity (DNL)
Understanding the operational characteristics of the DNL error is the measure of variations in code widths
device’s resistor components is important to the system from the ideal code width. A DNL error of zero would
design. imply that every code is exactly 1 LSb wide.
6.4.1 ACCURACY
6.4.1.1 Integral Non-linearity (INL) 111

INL error for these devices is the maximum deviation 110 Actual
between an actual code transition point and its transfer
corresponding ideal transition point after offset and 101 function
gain errors have been removed. These endpoints are
Digital 100 Ideal transfer
from 0x00 to 0x7F. Refer to Figure 6-5. Input function
Positive INL means higher resistance than ideal. Code 011
Negative INL means lower resistance than ideal.
010
Wide code, > 1 LSb
001
INL < 0
111 000
Actual Narrow code < 1 LSb
110 transfer
function Digital Pot Output
101
FIGURE 6-6: DNL Accuracy.
Digital 100
Input 6.4.1.3 Ratiometric temperature coefficient
Code 011 Ideal transfer The ratiometric temperature coefficient quantifies the
function error in the ratio RAW/RWB due to temperature drift.
010 This is typically the critical error when using a
potentiometer device (MCP40D18) in a voltage divider
001 configuration.
000 6.4.1.4 Absolute temperature coefficient
INL < 0
The absolute temperature coefficient quantifies the
Digital Pot Output error in the end-to-end resistance (Nominal resistance
RAB) due to temperature drift. This is typically the
FIGURE 6-5: INL Accuracy. critical error when using a rheostat device (MCP40D17
and MCP40D19) in an adjustable resistor
configuration.

MCP40D17/18/19
6.4.2 MONOTONIC OPERATION
Monotonic operation means that the device’s
resistance increases with every step change (from
terminal A to terminal B or terminal B to terminal A).
The wiper resistances difference at each tap location.
When changing from one tap position to the next (either
increasing or decreasing), the ΔRW is less than the
ΔRS. When this change occurs, the device voltage and
temperature are “the same” for the two tap positions.
RS63
0x3F
RS62
0x3E
Digital Input Code
0x3D
RS3
0x03
RS1
0x02
RS0
0x01
0x00
RW n=?
(@ tap)
RBW = RSn + RW(@ Tap n)
n=0
Resistance (RBW)
FIGURE 6-7: RBW.

MCP40D17/18/19
7.0 DESIGN CONSIDERATIONS 7.2 Layout Considerations
In the design of a system with the MCP40D17/18/19 Inductively-coupled AC transients and digital switching
devices, the following considerations should be taken noise can degrade the input and output signal integrity,
into account. These are: potentially masking the MCP40D17/18/19’s
performance. Careful board layout will minimize these
• The Power Supply
effects and increase the Signal-to-Noise Ratio (SNR).
• The Layout Bench testing has shown that a multi-layer board
In the design of a system with the MCP40D17/18/19 utilizing a low-inductance ground plane, isolated inputs,
devices, the following considerations should be taken isolated outputs and proper decoupling are critical to
into account: achieving the performance that the silicon is capable of
• Power Supply Considerations providing. Particularly harsh environments may require
shielding of critical signals.
• Layout Considerations
If low noise is desired, breadboards and wire-wrapped
7.1 Power Supply Considerations boards are not recommended.
The typical application will require a bypass capacitor 7.2.1 RESISTOR TEMPCO
in order to filter high-frequency noise, which can be Characterization curves of the resistor temperature
induced onto the power supply's traces. The bypass coefficient (Tempco) are shown in Figure 2-11,
capacitor helps to minimize the effect of these noise Figure 2-29, Figure 2-47, and Figure 2-65.
sources on signal integrity. Figure 7-1 illustrates an
appropriate bypass strategy. These curves show that the resistor network is
designed to correct for the change in resistance as
In this example, the recommended bypass capacitor temperature increases. This technique reduces the
value is 0.1 µF. This capacitor should be placed as end to end change is RAB resistance.
close to the device power pin (VDD) as possible (within
4 mm).
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS should reside on the analog plane.
VDD
0.1 µF
VDD
0.1 µF
PICmicro® Microcontroller
MCP40D17/18/19
A
SCL
W
B SDA
VSS VSS
FIGURE 7-1: Typical Microcontroller

Connections.

MCP40D17/18/19
NOTES:

MCP40D17/18/19
8.0 APPLICATIONS EXAMPLES
VDD
Digital potentiometers have a multitude of practical
uses in modern electronic circuits. The most popular
uses include precision calibration of set point R1
thresholds, sensor trimming, LCD bias trimming, audio MCP40D18
attenuation, adjustable power supplies, motor control A
overcurrent trip setting, adjustable gain amplifiers and SDA W VOUT
offset trimming. The MCP40D17/18/19 devices can be SCL
used to replace the common mechanical trim pot in
B
applications where the operating and terminal voltages
are within CMOS process limitations (VDD = 2.7V to
5.5V).
FIGURE 8-1: Using the Digital
8.1 Set Point Threshold Trimming Potentiometer to Set a Precise Output Voltage.
Applications that need accurate detection of an input
8.1.1 TRIMMING A THRESHOLD FOR AN
threshold event often need several sources of error
eliminated. Use of comparators and operational
OPTICAL SENSOR
amplifiers (op amps) with low offset and gain error can If the application has to calibrate the threshold of a
help achieve the desired accuracy, but in many diode, transistor or resistor, a variation range of 0.1V is
applications, the input source variation is beyond the common. Often, the desired resolution of 2 mV or
designer’s control. If the entire system can be better is adequate to accurately detect the presence of
calibrated after assembly in a controlled environment a precise signal. A “windowed” voltage divider, utilizing
(like factory test), these sources of error are minimized the MCP40D18, would be a potential solution.
if not entirely eliminated. Figure 8-2 illustrates this example application.
Figure 8-1 illustrates a common digital potentiometer
configuration. This configuration is often referred to as VDD
a “windowed voltage divider”. Note that R1 is not
necessary to create the voltage divider, but its
presence is useful when the desired threshold has
limited range. It is “windowed” because R1 can narrow
the adjustable range of VTRIP to a value much less than
VDD
VDD – VSS. If the output range is reduced, the VCC+
magnitude of each output step is reduced. This Rsense
effectively increases the trimming resolution for a fixed R1
digital potentiometer resolution. This technique may
MCP40D18 A Comparator
allow a lower-cost digital potentiometer to be utilized VTRIP
(64 steps instead of 256 steps). SDA W
SCL MCP6021
The MCP40D18’s low DNL performance is critical to
B VCC-
meeting calibration accuracy in production without 0.1 µF
having to use a higher precision digital potentiometer.
EQUATION 8-1: CALCULATING THE

WIPER SETTING FROM FIGURE 8-2: Set Point or Threshold
THE DESIRED VTRIP Calibration.
R WB
V TRIP = V DD ⎛⎝ -------------------⎞⎠
R1 + R2
RAB = RNominal
RWB = RAB • D
127
VTRIP
D= • (R1 + RAB ) • 127
VDD
D = Digital Potentiometer Wiper Setting (0-127)

MCP40D17/18/19
8.2 Operational Amplifier
Applications MCP40D18
R4
B A
Figure 8-3 and Figure 8-4 illustrate typical amplifier
circuits that could replace fixed resistors with the W
MCP40D17/18/19 to achieve digitally-adjustable
analog solutions. VDD ‚
Op Amp
R1
MCP6291 VOUT
VIN + VIN +
MCP6021
VDD Op Amp A
W
VOUT 1
‚ B fc = -----------------------------
2 π ⋅ R Eq ⋅ C
R1 MCP40D18
A R3
W
B
MCP40D17
Thevenin R = ( R 1 + R AB – R WB ) || ( R 2 + R WB ) + R w
MCP40D18 Equivalent Eq
FIGURE 8-4: Programmable Filter.

FIGURE 8-3: Trimming Offset and Gain in
a Non-Inverting Amplifier.

MCP40D17/18/19
8.3 Temperature Sensor Applications The circuit illustrated by Figure 8-6 utilizes a digital
potentiometer for trimming the offset error. This
Thermistors are resistors with very predictable solution removes RW from the trimming equation along
variation with temperature. Thermistors are a popular with the error associated with RW. R2 is not required,
sensor choice when a low-cost temperature-sensing but can be utilized to reduce the trimming “window” and
solution is desired. Unfortunately, thermistors have reduce variation due to the digital pot’s RAB part-to-part
non-linear characteristics that are undesirable, typically variability.
requiring trimming in an application to achieve greater
accuracy. There are several common solutions to trim
and linearize thermistors. Figure 8-5 and Figure 8-6 VDD
are simple methods for linearizing a 3-terminal NTC
thermistor. Both are simple voltage dividers using a
Positive Temperature Coefficient (PTC) resistor (R1) R1
with a transfer function capable of compensating for the NTC
linearity error in the Negative Temperature Coefficient Thermistor
(NTC) thermistor.
The circuit, illustrated by Figure 8-5, utilizes a digital
rheostat for trimming the offset error caused by the
thermistor’s part-to-part variation. This solution puts the
VOUT
digital potentiometer’s RW into the voltage divider
MCP40D18
calculation. The MCP40D17/18/19’s RAB temperature
coefficient is a low 50 ppm (-20°C to +70°C). RW’s error
is substantially greater than RAB’s error because RW
varies with VDD, wiper setting and temperature. For the
50 kΩ devices, the error introduced by RW is, in most FIGURE 8-6: Thermistor Calibration using
cases, insignificant as long as the wiper setting is > 6. a Digital Potentiometer in a Potentiometer
For the 2 kΩ devices, the error introduced by RW is Configuration.
significant because it is a higher percentage of RWB.
For these reasons, the circuit illustrated in Figure 8-5 is
not the most optimum method for “exciting” and
linearizing a thermistor.
VDD
R1
NTC
Thermistor
VOUT
R2
MCP40D17
FIGURE 8-5: Thermistor Calibration using

a Digital Potentiometer in a Rheostat
Configuration.

MCP40D17/18/19
8.4 Wheatstone Bridge Trimming
Another common configuration to “excite” a sensor
(such as a strain gauge, pressure sensor or thermistor)
is the wheatstone bridge configuration. The
wheatstone bridge provides a differential output
instead of a single-ended output. Figure 8-7 illustrates
a wheatstone bridge utilizing one to three digital
potentiometers. The digital potentiometers in this
example are used to trim the offset and gain of the
wheatstone bridge.
VDD
5 kΩ
MCP40D17
VOUT
MCP40D17 MCP40D17
50 kΩ 50 kΩ
FIGURE 8-7: Wheatstone Bridge

Trimming.

MCP40D17/18/19
9.0 DEVELOPMENT SUPPORT 9.2 Technical Documentation
Several additional technical documents are available to
9.1 Development Tools assist you in your design and development. These
The MCP40D17/18/19 devices can be evaluated with technical documents include Application Notes,
the MCP4XXXDM-PGA board, but it will require the Technical Briefs, and Design Guides. Table 9-1 shows
removal of the MCP4017 device and the installation of some of these documents.
the MCP40D17 device. Please check the Microchip
web site for the release of this board. The board part
number is tentatively MCP4XXXDM-PGA, and is
expected to be available in the fall of 2009.
Note: The MCP40D17 device is identical to the

MCP4017 device with the exception of the
I2C interface protocol format.
TABLE 9-1: TECHNICAL DOCUMENTATION

Application
Title Literature #
Note Number
AN1080 Understanding Digital Potentiometers Resistor Variations DS01080
AN737 Using Digital Potentiometers to Design Low-Pass Adjustable Filters DS00737
AN692 Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect DS00692
AN691 Optimizing the Digital Potentiometer in Precision Circuits DS00691
AN219 Comparing Digital Potentiometers to Mechanical Potentiometers DS00219
— Digital Potentiometer Design Guide DS22017
— Signal Chain Design Guide DS21825

MCP40D17/18/19
NOTES:

MCP40D17/18/19
10.0 PACKAGING INFORMATION
10.1 Package Marking Information
5-Lead SC70 Example:
Part Number Code

MCP40D19T-502E/LT BTNN
XXNN MCP40D19T-103E/LT BUNN ATNN
MCP40D19T-503E/LT BVNN
1 1
MCP40D19T-104E/LT BWNN
6-Lead SC70 Example:
Part Number Code Part Number Code

MCP40D17T-502E/LT AJNN MCP40D18T-502E/LT APNN
XXNN MCP40D17T-103E/LT AKNN MCP40D18T-502AE/LT ATNN AJNN
MCP40D17T-503E/LT ALNN MCP40D18T-103E/LT AQNN
1 1
MCP40D17T-104E/LT AMNN MCP40D18T-103AE/LT AUNN
MCP40D18T-503E/LT ARNN
MCP40D18T-503AE/LT AVNN
MCP40D18T-104E/LT ASNN
MCP40D18T-104AE/LT AWNN
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

MCP40D17/18/19

.
#
#$ #/! - 0 #
1/%#

#!#
##+22---

2/
3 2 1
E1
4 5
e e
A A2 c
A1
L
3# 44" "

4# 5 56 7
5$8
%1 5 (
1# 9()*
6, :# ; <

!!1/ / ; <
#!
%% <
6, =!# " ;

!!1/=!# " ( ( (
6, 4# ; (
.
#4# 4 9

4! / ; < 9
4!=!# 8 ( <

!"!

#$!
!%

# $

!%

# $

#&! !

!#
"'(
)*+ )

#&#,$
--#
$##

- *9)

MCP40D17/18/19
.
#
#$ #/! - 0 #
1/%#

#!#
##+22---

2/

MCP40D17/18/19
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

MCP40D17/18/19

MCP40D17/18/19

MCP40D17/18/19
APPENDIX A: REVISION HISTORY
Revision B (August 2009)

the following is the List of Modifications:
1. Document updated to include the new standard
I2C slave address (“0111110“) for the
MCP40D18 device.
2. Section 10.0 “Packaging Information”: Cor-
rected the Marking codes for 5-lead SC70
Codes shown were for the 6-lead SC70.
Updated Package Outline Drawings.
Revision A (May 2009)

• Original Release of this Document.

MCP40D17/18/19
NOTES:

MCP40D17/18/19
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. XXX X X /XX Examples:

Device Resistance I2C Device Temperature Package a) MCP40D17T-502E/LT: 5 kΩ,
Version Address Range 6-LD SC70
b) MCP40D17T-103E/LT: 10 kΩ,
Device: MCP40D17: Single Rheostat with I2C
interface 6-LD SC70
MCP40D17T:Single Rheostat with I2C interface c) MCP40D17T-503E/LT: 50 kΩ,
(Tape and Reel) 6-LD SC70
MCP40D18: Single Potentiometer to GND with d) MCP40D17T-104E/LT: 100 kΩ,
I2C Interface 6-LD SC70
MCP40D18T:Single Potentiometer to GND with a) MCP40D18T-502E/LT: 5 kΩ,
I2C Interface (Tape and Reel) 6-LD SC70
MCP40D19: Single Rheostat to GND with b) MCP40D18T-103E/LT: 10 kΩ,
I2C Interface 6-LD SC70
MCP40D19T:Single Rheostat to GND with c) MCP40D18T-503E/LT: 50 kΩ,
I2C Interface (Tape and Reel) 6-LD SC70
d) MCP40D18T-104E/LT: 100 kΩ,
Resistance 502 = 5 kΩ 6-LD SC70
Version: 103 = 10 kΩ a) MCP40D18T-502AE/LT: 5 kΩ,
503 = 50 kΩ 6-LD SC70
104 = 100 kΩ
b) MCP40D18T-103AE/LT: 10 kΩ,
6-LD SC70
I2C Device blank = ‘0101110’ c) MCP40D18T-503AE/LT: 50 kΩ,
Address A = ‘0111110’ (1) 6-LD SC70
Version: d) MCP40D18T-104AE/LT: 100 kΩ,
6-LD SC70
Temperature E = -40°C to +125°C a) MCP40D19T-502E/LT: 5 kΩ,
Range: 5-LD SC70
b) MCP40D19T-103E/LT: 10 kΩ,
Package: LT = Plastic Small Outline Transistor (SC70), 5-LD SC70
5-lead, 6-lead c) MCP40D19T-503E/LT: 50 kΩ,
5-LD SC70
Note 1: This address is a standard option on the MCP40D18 d) MCP40D19T-104E/LT: 100 kΩ,
device only. It is a custom device on the MCP40D17 5-LD SC70
and MCP40D19 devices.

MCP40D17/18/19
NOTES:

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
ensure that your application meets with your specifications.
rfPIC and UNI/O are registered trademarks of Microchip
MICROCHIP MAKES NO REPRESENTATIONS OR Technology Incorporated in the U.S.A. and other countries.
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
OTHERWISE, RELATED TO THE INFORMATION, MXDEV, MXLAB, SEEVAL and The Embedded Control
INCLUDING BUT NOT LIMITED TO ITS CONDITION, Solutions Company are registered trademarks of Microchip
QUALITY, PERFORMANCE, MERCHANTABILITY OR Technology Incorporated in the U.S.A.
FITNESS FOR PURPOSE. Microchip disclaims all liability Analog-for-the-Digital Age, Application Maestro, CodeGuard,
arising from this information and its use. Use of Microchip dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
devices in life support and/or safety applications is entirely at ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
the buyer’s risk, and the buyer agrees to defend, indemnify and Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
hold harmless Microchip from any and all damages, claims, logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
suits, or expenses resulting from such use. No licenses are Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
conveyed, implicitly or otherwise, under any Microchip PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
intellectual property rights. Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
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SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

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MCP40D17/18/19: 7-Bit Single I C™ (With Command Code) Digital POT With Volatile Memory in SC70

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7-Bit Single I2C™ (with Command Code) Digital POT

Features Package Types

Device Configuration Options (kΩ) (Ω) Range ( 1) Package

© 2009 Microchip Technology Inc. DS22152B-page 1

Downloaded from Arrow.com.

VDD Power-up/ A (2)

Comparison of Similar Microchip Devices ( 1)

DS22152B-page 2 © 2009 Microchip Technology Inc.

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© 2009 Microchip Technology Inc. DS22152B-page 3

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Parameters Sym Min Typ Max Units Conditions

DS22152B-page 4 © 2009 Microchip Technology Inc.

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Parameters Sym Min Typ Max Units Conditions

© 2009 Microchip Technology Inc. DS22152B-page 5

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Parameters Sym Min Typ Max Units Conditions

DS22152B-page 6 © 2009 Microchip Technology Inc.

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Parameters Sym Min Typ Max Units Conditions

© 2009 Microchip Technology Inc. DS22152B-page 7

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Parameters Sym Min Typ Max Units Conditions

DS22152B-page 8 © 2009 Microchip Technology Inc.

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FIGURE 1-1: I2C Bus Start/Stop Bits Timing Waveforms.

TABLE 1-1: I2C BUS START/STOP BITS REQUIREMENTS

103 100 102

Note 1: Refer to specification D102 (Cb) for load conditions.

FIGURE 1-2: I2C Bus Data Timing.

© 2009 Microchip Technology Inc. DS22152B-page 9

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DS22152B-page 10 © 2009 Microchip Technology Inc.

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© 2009 Microchip Technology Inc. DS22152B-page 11

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DS22152B-page 12 © 2009 Microchip Technology Inc.

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Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.

IDD Interface Inactive (µA)

400 kHz, 5.5V

© 2009 Microchip Technology Inc. DS22152B-page 13

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120 0.3 120 -40C Rw 25C Rw 85C Rw 125C Rw

Wiper Resistance (RW)

Wiper Resistance (RW)

2500 0.35 2500 -40C Rw 25C Rw 85C Rw 125C Rw 44

-40C DNL 25C DNL 85C DNL 125C DNL 2000

DS22152B-page 14 © 2009 Microchip Technology Inc.

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RBW Tempco (PPM)

© 2009 Microchip Technology Inc. DS22152B-page 15

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DS22152B-page 16 © 2009 Microchip Technology Inc.

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120 0.3 120 -40C Rw 25C Rw 85C Rw 125C Rw

Wiper Resistance (RW)