Chapter 3X
Chapter 3X
Chapter 3X
There is a vast proliferation of power switching semiconductor devices, each offering various features,
attributes, and limitations. The principal device families of concern in the power switching semiconductor
range are the diode, transistor, and thyristor. Each family category has numerous different members. The
basic characteristics of the three families and a range of their members, both uni-polar and bipolar carrier
types, will be presented.
minority
Semiconductor device carrier
Si, SiC, GaN majority
Semiconductor device families. carrier
Igbt/iegt diac/triac
The homojunction p-n diode is the simplest semiconductor device, comprising one pn junction. In attempts
to improve both static and dynamic diode electrical properties for different application conditions,
numerous diode types and material technologies have evolved.
The doping concentration on each side of the junction influences the avalanche breakdown voltage, the
contact potential, and the series resistance of the diode. The junction diode normally has the p-side highly
doped compared with the n-side, and the lightly doped n-region determines most of the properties of the
BWW
Chapter 3 Power Switching Devices and their Static Electrical Characteristics 72
device. The n-region gives the device its high-voltage breakdown and under reverse bias, the scl
penetrates deeply into the n-side. The lower the n-type concentration and the wider the n-side, the higher
will be the reverse voltage rating and also, the higher the forward resistance. These n-region requirements
can lead to thermal I R problems in silicon. Larger junction areas help reduce the thermal instability
2
problem.
+
It is usual to terminate the lightly doped n-region with a heavily doped n layer to simplify ohmic contact
and to reduce the access resistance to the scl. For better n-region width control, n-type silicon is epitaxially
+ +
grown on an n substrate. The p anode is diffused or implanted into the epitaxial region, forming an
epitaxial diode.
In devices specifically designed for high reverse bias applications, care must be taken to avoid
premature breakdown across the edge of the die or where the junction surfaces. Premature edge
breakdown is reduced by bevelling the edge as shown in figure 3.1a, or by diffusing a guard ring as shown
in figure 3.1b, which isolates the junction from the edge of the wafer. The scl electric field is lower at the
bevelled edge than it is in the main body of the device. In the case of a lightly doped p-type guard ring, the
+
scl is wider in the p-ring, because of its lower concentration, than in the p region. The maximum electric
field is therefore lower at the pn-ring junction for a given reverse bias voltage. Negatively charged glass
film techniques are also employed to widen the scl near the surface, as shown in figures 3.1c and 3.1d.
cathode
anode
cathode
(a) (b)
anode
anode
+ +
n n
cathode cathode
(c) (d)
(e) (f)
Multiple guard rings are sometimes employed for high breakdown voltage devices. Similar techniques
are extendable to devices other than diodes, such as thyristors. Field control bevelling on more complex
junction structures is achieved with double-negative or double-positive bevelling as shown in parts e and f
73 Power Electronics
of figure 3.1. The bevelling is accomplished by grinding, followed by etching of the bevel surface to restore
the silicon crystalline mechanical and structure quality. The processed area is passivated with a thin layer
of polyimide, which is covered in silicon rubber. Negative (as opposed to positive) bevels tend to be more
stable electrically with ageing.
The foregoing discussion is directly applicable to the rectifier diode, but other considerations are also
important if fast switching properties are required. The turn-on and reverse recovery time of a junction are
minimised by reducing the amount of stored charge in the neutral regions and by minimising carrier
lifetimes. Lifetime killing is achieved by adding gold or platinum, which is an efficient recombination centre.
Electron and proton irradiation are preferred non-invasive lifetime control methods. Irradiation gives the
lowest forward recovery voltage and the lowest reverse leakage current. The improved switching times
must be traded off against increased leakage current and on-state voltage. Switching times are also
improved by minimising the length (thickness) of the n-region.
3.1.2 The p-i-n diode
The transient performance of diodes tends to deteriorate as the thickness of the silicon wafer is
increased in attaining higher reverse voltage ratings. Gold lifetime killing only aggravates the adverse
effects incurred with increased thickness. The p-i-n diode allows a much thinner wafer than its
conventional pn counterpart, thus facilitating improved switching properties.
The p-i-n diode is a pn junction with a doping profile tailored so that an intrinsic layer, the i-region, is
sandwiched between the p-layer and the n-layer, as shown in figure 3.2. In practice, the idealised i-region
is approximated by a high resistivity n-layer referred to as a v-layer. Because of the low doping in the
v-layer, the scl will penetrate deeply and most of the reverse bias potential will be supported across this
region.
n i
p.d. = area
p.d. = area
The power p-i-n diode can be fabricated by using either the epitaxial process or the diffusion of p and
n-regions into a high-resistivity semiconductor substrate. The i-region width Wi , specifies the reverse
voltage breakdown of the p-i-n diode, which is the area under the electric field in figure 3.2b, viz.,
The thickness Wi , along with the distribution of any gold within it, determines the nature of the reverse
and forward-conducting characteristics. These characteristics are more effective and efficient in fast p-i-n
diodes than in the traditional pn structures.
Zener diodes are pn diodes used extensively as voltage reference sources and voltage clamps. The diode
reverse breakdown voltage is used as the reference or clamping voltage level.
The leakage current in a good pn diode remains small up to the reverse breakdown point where the
characteristic has a sharp bend. Such an electrical characteristic is called hard. Premature breakdown at
Chapter 3 Power Switching Devices and their Static Electrical Characteristics 74
weak spots in the junction area or periphery cause high leakage currents before final breakdown, and
such diodes are said to have soft breakdown characteristics.
Zener diodes are especially made to operate in the breakdown range. Above a few volts, the
breakdown mechanism is avalanche multiplication rather than Zener and the breakdown reference
voltage VZ is obtained by proper selection of the pn junction doping levels. Once in breakdown VZ remains
almost constant provided the manufacturer’s power rating, P = VZ I, is not exceeded. Where the break-
down mechanism is due to the Zener effect, the temperature coefficient for silicon devices, is negative,
about -0.1 per cent/K, changing to positive, +0.1 per cent/K, after about 4.5V when the avalanche
multiplication mechanism predominates.
Zener diodes require a hard breakdown characteristic not involving any local hot spots. They are
available in a voltage range from a few volts to 380V (@5W, 1N4996) and with continuous power
dissipations ranging from 250mW to 75W, with heat sinking. Transient suppressing Zener diodes can
absorb up to 50kW, provided energy limits and current limits are not exceeded, as shown in figure 10.35.
Diffused Si pnp surge voltage suppressors rated to in excess of 4.4kV can absorb 700kW for 1μs.
Practically, Zener diodes are difficult to make, less than ideal in application, and should be avoided if
possible. The basic I-V characteristics, and electrical circuit symbol for the different types of diodes, are
shown in figure 3.3.
forward
bias
reverse
bias
Figure 3.3. Diodes: (a) static I-V characteristic; (b) symbol for a rectifier diode;
(c) voltage reference or Zener diode; and (d) Schottky barrier diode.
in figure 3.4b, is also employed which reduces the field at the less than perfect metal-semiconductor
interface and allows the whole interface to go safely into reverse bias breakdown.
There are a number of important differences between Schottky barrier and pn junction diodes.
In a pn diode, the reverse bias leakage current is the result of minority carriers diffusing into the scl
and being swept across it. This current level is highly temperature-sensitive. In the
Schottky-barrier case, reverse current is the result of majority carriers that overcome the barrier. A
much higher leakage value results at room temperature, but is not temperature-dependent.
The forward current is mostly injected from the n-type semiconductor into the metal and little excess
minority charge is able to accumulate in the semiconductor. Since minimal minority carrier
recombination occurs, the Schottky barrier diode is able to switch rapidly from forward conduction
to reverse voltage blocking.
Since under forward bias, barrier injection comes only from the semiconductor, and there is little
recombination in the scl; the device can be represented by the ideal diode equation (2.6).
The majority electrons injected over the barrier into the metal have much higher energy than the
other metal electrons which are in thermal equilibrium. Those injected electrons are therefore
called hot, and the diode in some applications is referred to as a hot electron diode.
(a)
(b)
Figure 3.4. The Schottky barrier diode: (a) basic structure and (b) space charge layer region extending
into the epi-substrate region under reverse bias.
Table of Schottky barrier heights ΦB of silicates on n-type silicon.
An significant point arising from this consideration of the Schottky barrier diode is the importance of the
connection of an n-type semiconductor region to aluminium metallization that occurs in unipolar and
bipolar semiconductor devices. A practical method of forming aluminium ohmic contacts on n-type
19 3
materials where Φb > 0, is by doping the semiconductor heavily (>10 /cm ), above the degeneracy level.
Thus, in the contact region, if a barrier exists, the scl width is small enough (<3nm) to appear transparent,
allowing electron carriers to tunnel through the barrier in both directions. On the other hand, aluminium
+
makes a good ohmic contact on p-type silicon since the required p surface layer is formed during the heat
treatment of the contact after the aluminium is deposited. An ohmic contact acts as a virtual sink for
minority carriers, because it has an enormous supply of majority carriers.
Chapter 3 Power Switching Devices and their Static Electrical Characteristics 76
Figure 3.5. Schottky and epi diode I-V characteristics with different Schottky barrier potentials.
Anode, Aℓ
Implanted edge termination Schottky
barrier
p
Nitride
passivation
n- epi-layer
+
n substrate
NiV/Ag
cathode
Silicon carbide Schottky diodes are attractive for high voltages because the field breakdown of silicon
carbide is eight times that of silicon. Additionally, the wide band gap allows higher operating temperatures.
15 2
Both nickel and titanium can be used as Schottky metals. Boron atoms (a dose of 1 x10 /cm at 30keV)
are implanted to form the edge termination that spreads any field crowding at the edge of the metal
contact, as shown in figure 3.6. The lower barrier height of titanium produces a lower forward voltage
device, but with a higher reverse leakage current, than when nickel is used as the barrier metal.
77 Power Electronics
Two types of transistor are extensively used in power switching circuits, namely the enhancement mode,
power metal oxide semiconductor field effect transistor (MOSFET) and the insulated gate bipolar transistor
(IGBT). Effectively, the IGBT has a pnp bipolar junction transistor (BJT) output stage and an n-channel
MOSFET input stage, in an integrated Darlington pair configuration. Many of the IGBT power handling
properties are associated with BJT limitations. Thus some attention to the BJT’s electrical characteristics is
necessary, even though it is virtually obsolete as a discrete power-switching device. SiC BJTs may offer a
short reprieve, only because of its extremely low on-state voltage characteristics.
The BJT consists of a pnp or npn single-crystal silicon structure. It operates by the
injection and collection of minority carriers, both electrons and holes, and is
therefore termed a bipolar transistor.
The MOSFET depends on the voltage control of a depletion width and is a majority carrier
device. It is therefore a unipolar transistor.
The IGBT has the desirable voltage input drive characteristics of the MOSFET but the
power switching disadvantages of the minority carrier mechanisms of the BJT.
As a discrete electrical device, the high-voltage, Si power-switching bipolar junction transistor, BJT, is
virtually obsolete. The BJT has one unique redeeming electrical characteristic, viz.; it can be designed to
conduct hundreds of amperes with an extremely low on-state voltage of less than 100mV, when both
junctions are forward biased, saturated. Although superseded, its basic electrical operating
characteristics are fundamental to the operation of other power switching devices. Specifically, the
MOSFET has a parasitic npn BJT, as shown in figure 3.14, that can cause false turn-on other than for the
fact that understanding of BJT characteristics allows circumvention of the problem. The fundamental
operation of thyristors (SCR, GTO, and GCT) relies on BJT characteristics and electrical mechanisms. The
IGBT has two parasitic BJTs, as shown in figure 3.16, that form an undesirable pnp-npn SCR structure.
Understanding of BJT gain mechanisms allows virtual deactivation of the parasitic SCR.
The first bipolar transistors were mainly pnp, fabricated by alloying techniques and employed
germanium semiconductor materials. Most transistors are now npn, made of silicon, and utilise selective
diffusion and oxide masking.
A typical high-voltage triple-diffused transistor doping profile is shown in figure 3.7a. The n-collector
+
region is the initial high-resistivity silicon material and the collector n diffusion is performed first, usually
+ +
into both sides. One n diffusion is lapped off and the p-base and n emitter diffusions are sequentially
performed.
A planar epitaxial structure is often used for transistors with voltage ratings of less than 1000V. The
basic structure and processing steps are shown in figure 3.7b. The n-type collector region is an epitaxial
layer grown on an n-substrate. The base and emitter are sequentially diffused into the epitaxy. Ion
implantation is also used. This approach allows greater control on the depth of the n-type collector region,
which is particularly important in specifying device switching and high-voltage properties. Also, the
parasitic series collector resistance of the substrate is minimised without compromising the pellet’s
mechanical strength as a result of a possible reduction in wafer thickness.
αIe
αIe
RLoad
RLoad
Rb
Rb
Figure 3.8. Common emitter junction bias conditions for an npn transistor
and the npn bipolar junction transistor circuit symbol.
ic ic i /i
c b (3.3)
ib ie ic 1 ic / i b
(3.4)
1
The factor β, relating the collector current to the base current, is defined as the base-to-collector
current amplification factor. If α is near unity, β is large, implying the base current is small compared with
the collector current.
Saturation
region
ib=4A
ib=3A
Linear
region
ib=2A
ib=1A
ib=0A Vb
Cut-off Vcbo
region
(3.6)
where the avalanche breakdown voltage Vb is given by equation (2.3);
+
m ≈ 6 for a silicon p n collector junction; and
+
m ≈ 4 for a silicon n p collector junction.
Contradictory device properties are that the higher the forward gain, the lower the breakdown voltage.
A much higher collector emitter breakdown voltage level can be attained if the base emitter junction is
reverse biased in the off-state.
First breakdown need not be catastrophic provided junction temperature limits are not exceeded. If
local hot spots occur because of non-uniform current density distribution as a result of crystal faults,
doping fluctuation, etc., second breakdown occurs. Silicon crystal melting and irreparable damage result,
the collector voltage falls, and the current increases rapidly as shown in figure 3.9.
pinch-off
T
T saturation
region
constant
resistance
constant current
T
An important parameter in mos transistors is the threshold voltage VTh, which is the minimum positive
gate voltage to induce the n-conducting channel. With zero gate voltage the structure is normally off. The
device is considered to operate in the enhancement mode since the application of a positive gate voltage
in excess of VTh induces an n-conducting channel. The typical temperature dependant output
characteristics of the MOSFET are shown in figure 3.10c.
DRAIN
Figure 3.11. Two designs for the n-channel MOSFET and its circuit symbol
(courtesy of Infineon and International Rectifier).
The obtainable drain-to-source breakdown voltage is not limited by the gate geometry. The scl associated
with voltage blocking penetrates mostly in the n-type epitaxial layer. Thickness and doping concentration
of this layer are thus decisive in specifying the blocking capability of the power MOSFET.
The basic drain current versus drain to source voltage static operating characteristics (and their
temperature dependence) of the power MOSFET are illustrated in figure 3.10c. For a given gate voltage,
there are two main operating regions on the drain current-voltage characteristic.
The first is a constant resistance region, where an increase in drain to source voltage results
in a proportional increase in drain current. (In practice, the effective resistance increases at
higher drain currents.)
At a certain drain current level, for a given gate voltage, a channel pinch-off effect occurs and
the operating characteristic moves into a constant current region.
current is essentially defined by the load and the device power dissipation is minimal. Thus for switching
applications, the on-resistance Rds(on) is an important characteristic because it will specify the on-state
power loss for a given drain current. The lower Rds(on), the higher the current-handling capabilities of the
device; thus Rds(on) is one important figure of merit of a power MOSFET.
A quadratic MOSFET model allows the inversion layer charge between the source and the drain to vary.
For power MOSFETs that have short channels, the drain current Id is related to the channel dimensions
st
and the gate voltage Vgs according to (1 order model, as opposed to bulk-charge model)
at high current after electron velocity saturation, the quadratic model is invalid and
I d ½v sat Wc Ca (Vgs VT h ) (A) (3.8)
where Ca is the capacitance per unit area of the gate oxide (ε / tox)
Wc is the width of the channel
6
νsat is the saturation velocity of electrons in silicon, (9.0x10 cm/s)
Lc is the effective channel length
2
µn is the conducting channel carrier mobility, (300 cm / V-s).
In the ohmic (linear) region, where Vgs Vth and Vgs Vth Vds 0 , the drain current is given by
Wc
I d nC V V V ½ Vds2 (3.9)
Lc a gs TH ds
and when the gate voltage is below the threshold level, Vgs VTh ,
Id 0 (3.10)
Figure 3.12a shows that drain current exhibits both a positive and negative temperature coefficient with
the drain current IDQ being the boundary condition. If the drain current is greater than IDQ there is a
possibility of destruction by over-current at low temperatures, while if the drain current is less than IDQ,
over-current can produce thermal runaway and destruction. Operation with a gate voltage corresponding
to IDQ avoids the need for any gate drive temperature compensation.
At high gate voltages, the on-resistance of the resistive region and the drain current in the constant current
region, become somewhat independent of the gate voltage. This phenomenon is best illustrated in the Id
versus Vds characteristic by the curve cramping at high gate voltages in figure 3.10c.
83 Power Electronics
Differentiating equations (3.7) and (3.8), with respect to drain voltage, gives zero, gd = 0, for each case in
the saturation region. In the ohmic (linear) region the output conductance is
Wc
g d n C V V V (3.14)
Lc a gs Th ds
A p-channel device with the same Vb as an n-channel device has an Rds(on) two to three times larger as
given by
Rds (on) 1.6 106 Vb2.5 / A () (3.17)
The factor 1/gfs of Rds(on) is added to give the total Rds(on). On-state drain-source loss can therefore be
based on I d2 Rds on . On-resistance Rds(on) increases with temperature and approximately doubles over the
range 25°C to 200°C, having a positive temperature coefficient of approximately +0.7 per cent/K above
25ºC, as shown in figure 3.13. The temperature dependence of the on-state resistance is approximated by
2.3
T
Rds (on) (T ) Rds (on) (25°C) () (3.18)
300
where the temperature T is in degrees Kelvin. This relationship (as does forward conductance in equation
(3.15)) closely follows the mobility charge dependence on temperature.
Since Rds(on) increases with temperature, current is automatically diverted away from any hot spot. Thus
unlike the bipolar junction transistor, second breakdown cannot occur within the MOSFET. The breakdown
voltage Vb has a positive temperature coefficient of typically 0.1 per cent/K as shown by V(BR)DSS in figure
3.13.
V(BR)DSS
Vgs(TH)
Vgs =0V
ID=1mA
gfs
Vds=50V
A silicon n-channel MOSFET cell has a threshold voltage of VTh = 2V, Wc = 10µm, Lc = 1µm, and an oxide
thickness of tox = 50nm. The device is biased with Vgs = 10V and Vds = 15V.
2
i. Assuming a quadratic model and a surface carrier mobility of 300 cm /V-s, calculate the
drain current, cell dissipation, forward transconductance, and output conductance.
6
ii. Assuming carrier velocity saturation (5x10 cm/s), calculate the drain current, cell
dissipation, forward transconductance, and output conductance.
Solution
i. The MOSFET is biased in saturation since Vds Vgs - VTh . Therefore, from equation (3.7)
the drain current equals:
Wc
I d ½ C a (V V )2 where C a / t ox
Lc gs Th
3.85 8.85 1012 10μm
½ 300 104 (10V 2V)2 6.5 mA
50 109 1μm
The dc power dissipation is 6.5mAx15V=97.5mW.
From equation (3.11), the transconductance is:
Wc
g fs C a (V V )
Lc gs Th
3.85×8.85×10-14 10
= 300×10-4 × × ×(10V - 2V) = 1.64 mho
50×10-9 1
The output conductance gd is zero.
ii. When the electron velocity saturates, the drain current is given by equation (3.8)
I d ½v sat Wc C a (Vgs VT h )
3.85×8.85×10-12
= ½ × 5×104 × 10-5 × × (10V - 2V) = 136 mA
50×10-9
The dc power dissipation is 136mA x 15V=2W, a dc operating condition well in excess of the
cell capabilities.
The transconductance is given by equation (3.12)
g fs ½v satWc C a
3.85×8.85×10-12
= ½ × 5×104 × 10-5 × = 16.1 mho
50×10-9
The output conductance gd is zero.
Drain
+
n
-
n
RD
Cgd Cds
Cgd
+ Rbe
p Cds
Rbe
+
n
Cgs
Idiode
Figure 3.14. MOSFET – n-channel enhancement mode: (a) structure (parasitic diode blocking circuit
and (b) equivalent circuit diagram with parasitic npn bipolar transistor forming an inverse diode.
Whilst retaining the necessary voltage breakdown length properties, two basic approaches have been
pursued to achieve a more vertical gate (channel) structure, viz., the trench gate and vertical
super-junction, as shown in parts b and c of figure 3.15. Both techniques involve increased fabrication
complexity and extra costs.
1 - Trench gate
A channel is formed on the vertical sidewalls of a trench etched into the die surface as shown in figure
3.15b. The JFET resistive region is eliminated, which not only reduces the total resistance but allows
smaller cell size thereby increasing channel density and decreasing the short-circuit capacity. The trench
corners must be rounded to avoid high electric field stress points. By extending the gate into the drift
region, the gate to drain capacitance increases, hence increasing gate charge requirements.
87 Power Electronics
Source gate
n+
p
-
n epi
+
n sub
Drain
n n++
+ p
p
gate
- -
n n p n epi
oxide
+
n n sub
Drain Drain
(b) (c)
Figure 3.15. Three MOSFET channel structures:
(a) conventional planar gate; (b) trench gate; and (c) vertical superjunction.
2 - Vertical super-junction
-
The structure has vertical p-conducting regions in the voltage sustaining n drift area, that are extend to the
p-wells below the gate, as shown in figure 3.15c. In the off-state, the electric field is not only in the vertical
direction but also in the horizontal plane. This means the n-drift region width can be decreased, the
on-state resistance is decreased, and the gate charge is reduced for a given surface area. Up to sixteen
mask steps are needed which involves repeated cycles of n-type epi-layer growth, masked boron
implantation, and finally diffusion. The resultant specific resistance is near linearly related to breakdown
voltage, as opposed to Rds (on) Area Vbr2.5 , equation (3.16). Typically Rds(on) is five times lower than for
the conventional MOSFET, which only uses up to six mask steps.
Whilst the trench gate concept can be readily applied to other field effect devices without voltage rating
limits, the vertical super-junction is confined to the MOSFET, and then at voltage ratings below about
1000V.
The high off-state and low on-state voltage characteristics of the bipolar junction transistor are combined
with the high input impedance properties of the MOSFET to form the insulated gate bipolar transistor, IGBT,
+
as shown in figure 3.16. The basic structure is that of a MOSFET but with a p implanted into the drain
+
region. This p collector provides reverse blocking capabilities of typically 40V, which can be enhanced if
p-wells through the substrate are used to isolate the die periphery.
J1 Ic
is
clo
se Icp
collector Icp Imos
to
J2 1 is
clo
se
J3 to
1
(a) (b)
emitter emitter
gate
Ic
Ic αpnp
Icp
αnpn
Icp
(c) (d)
spaced, so that accumulated holes under the trench, enhance emitter injection of electrons. This injection
enhancement reduces the on-state voltage without degrading the switching performance.
collector
+
p
+ J1
minority carrier injection n
+
n buffer
-
n
J2
p
J3
n
collector
p
J1
minority carrier injection
Ic Imos -
n substrate
J2
p
J3
n
gate (b)
emitter emitter
Figure 3.17. Insulated gate bipolar transistor structures and electric field profile:
(a) fieldstop PT-IGBT and (b) conventional NPT-IGBT.
Further performance enhancement is gained by using the punch through, PT-IGBT, structure shown in
+
figure 3.17a, which incorporates an n buffer region. The conventional non-punch through NPT-IGBT
structure is shown in figure 3.17b. Both collector structures can have the same emitter structure, whether
a lateral gate as shown, or the MOSFET trench gate in figure 3.15b.
Figure 3.17 shows the electric field in the off-state, where the PT-IGBT develops a field as in the pin
diode in figure 3.2b, which allows a thinner wafer. The NPT-IGBT requires a thicker wafer (about 200µm
for a 1200V device) which results in a larger substrate resistance and a slower switching device.
The PT-IGBT has n and p layers formed by epitaxial growth on an n substrate. The
+ + -
electric field plot in figure 3.17a shows that the off-state voltage scl consumes
- +
the n substrate and is rapidly reduced to zero in the n buffer.
The NPT-IGBT has a lightly doped n substrate with the p-regions (p wells and p
-
in the on-state if the current density exceeds a critical level, which adversely
decreases with increased temperature or
during the turn-off voltage rise when the hole current increases in sensitive regions of
the structure due to the charge movement associated with the scl widening.
1 - IGBT on-state SCR static latch-up is related to the temperature dependant transistor gains which are
related to the BJT base transport factor bt and emitter injection efficiency γi, defined for the BJT in equation
(3.2)
pnp npn bt pnp i pnp bt pnp i pnp 1 (3.20)
Since the conductivity of the drift region under the gate electrode is increased by the introduction of
electron current through the channel, most of the holes injected into the drift region are injected at the
+
p-body region under the channel and flow to the source metal along the bottom of n source. This
produces a lateral voltage drop across the shunting resistance (R be in figure 3.16b) of the p-body layer. If
+
this voltage drop becomes greater than the potential barrier of the n source / p body layer junction, J3,
+ +
electrons are injected from the n source to the p-body layer, and the parasitic npn transistor (n source, p
-
body and n drift) is turned-on. If the sum of the two (npn and pnp) parasitic transistors’ current gains reach
unity in equation (3.20), latch-up occurs.
To avoid loss of control and possible IGBT failure, the factors in equation (3.20), which is valid for on-state
latch-up, are judiciously adjusted in the device design.
Common to both device types is the gate structure, hence the base-emitter junction of the npn parasitic
BJT have the same properties. In each structure, the shorting resistor Rbe decreases the injection
+
efficiency of the npn BJT emitter. This resistance is minimized by highly doping the p wells directly below
the n-emitters and by shortening the length of the n-emitter. The gain αnpn in equation (3.20) is decreased
since the injection efficiency γi npn is lowered.
Reduction of the pnp BJT gain of the PT-IGBT and NPT-IGBT is achieved with different techniques.
For the NPT-IGBT, the emitter injection efficiency of holes from the p zone into the n drift
+ -
region is high because of the large difference in doping concentrations at the junction.
Adversely this yields a high injection efficiency γipnp. The base transport factor bt pnp is already
-
low because of the large width of the n drift region, and is further reduced by lifetime killing of
-
minority carriers in the n drift region by using gold doping or electron beam radiation.
For the PT-IGBT, the p emitting junction at the collector is a well-controlled shallow implant
+
-
thus reducing the injection efficiency γi pnp. Charge carrier lifetime killing in the n drift region to
reduce the base transport factor bt pnp, is therefore not necessary.
2 - IGBT turn-off SCR dynamic latch-up can occur while the collector voltage is rising, before the
collector current decreases. When the IGBT is switched off, the depletion layer of the n drift /
-
p-body junction, J2 in figure 3.17, is abruptly extended, and the IGBT latches up due to the
resulting displacement current. This limits the safe operating area. Equation (3.20) is modified by
equation (3.5) to account for voltage avalanche multiplication effects.
Mnpn αnpn Mpnp αpnp 1 (3.21)
1
where, as in equation (3.5), M
1 (v ce /Vb )m
This dynamic latch-up mode is adversely affected by increased temperature and current magnitude during
the voltage rise time at turn-off.
Since v ce Vb , M 1 , and the multiplication effect is not significant in the on-state static latch-up
analysis. IGBTs are designed and rated so that the latch-up current is at least 10 times the rated current.
The conventional IGBT inherently has reverse voltage blocking capabilities, albeit low. Normally, the
collector boron ion p+ implant forms a transparent abrupt junction, optimised for on-state voltage and
turn-off speed.
-
When negative voltage is impressed at the collector in figure 3.16, the p+ substrate / n drift junction, J1, is
-
reverse biased, and the depletion layer expands to the n drift region. An optimal design in resistivity and
-
thickness for the n drift region is necessary in obtaining desirable reverse blocking capability. The width of
91 Power Electronics
-
the n drift region is equivalent to the sum of depletion width at maximum operating voltage and minority
-
carrier diffusion length. It is necessary to optimize the breakdown voltage while maintaining a narrow n
-
drift region width, as the forward voltage drop increases with an increase in n drift region width. The
-
following equation is the calculation for the n drift region width:
2Vb
d1 Lp (3.22)
qN D
-
where d1: n drift region width
Vb: maximum blocking voltage
ND: doping concentration
Lp: minority carrier diffusion length =√Dpp
collector metallization
p+ collector implant
n die edge
Deep p diffusion
p from emitter side
n
emitter
metal
gate 2 p guard rings n channel stop
Structurally, the IGBT can be viewed as a serial connection of the MOSFET and PiN diode. Alternatively, it
is sometimes considered a wide base pnp transistor driven by the MOSFET in a Darlington configuration.
The former view can be used to interpret the behaviour of the device, but the latter better describes the
IGBT.
The width of the undepleted n- drift region does not change rapidly with the increase in the collector
voltage due to the high concentration of the buffer layer, but maintains the same width as the n+ buffer
layer for all collector voltages. This results in a constant value of the pnp transistor’s current gain.
Additionally, the n+ buffer layer reduces the injection efficiency of the p+ substrate / n+ buffer junction, J1.
This reduces the current gain of the pnp transistor. Also, the collector output resistance can be increased
with electron irradiation to shorten the minority carrier lifetime, which reduces the diffusion length. The
IGBT saturated collector current expression involves the MOSFET current given by equation (3.7), giving:
1 W
Id ½ c C a (V gs VTh )2 (A) (3.23)
1 pnp Lc
Transconductance in the active region is obtained by differentiating the drain current with respect to Vge.
The IGBT’s saturated collector current and transconductance are higher than those of the power
MOSFETs of the same aspect ratio (Wc /Lc). This is because the pnp transistor’s current gain αpnp is
significantly less than 1.
Chapter 3 Power Switching Devices and their Static Electrical Characteristics 92
I d 1 Wc
g fs C a (V gs VTh ) (mho) (3.24)
V gs 1 pnp Lc
Vds constant
source source
- + -
gate gate
metal
+ + +
n n n
- + + -
n p p n
channel
+
n
s
metal
drain
g
+ p + d
+ n n +
p p
-
n drift region
(b)
n buffer
4H n+ substrate
body diode
drain
Figure 3.19. Cross-section of the SiC vertical junction field effect transistor:
(a) trench gate with channel shown and (b) variation incorporating a pn body diode.
3.3 Thyristors
The name thyristor is a generic term for a bipolar semiconductor device which comprises four
semiconductor layers and operates as a switch having a latched on-state and a stable off-state. Numerous
members of the thyristor family exist. The simplest device structurally is the silicon-controlled rectifier
(SCR) while the most complicated is the triac.
The two-transistor model of the SCR shown in figure 3.21 can be used to represent the p2-n2-p1-n1
structure and explain its electrical and thermal characteristics. Transistor T1 is an npn BJT formed from
regions n2-p1-n1 while T2 is a co-joined pnp BJT formed from SCR regions p2-n2-p1.
The application of a positive voltage between the anode and cathode does not result in conduction
because the SCR central junction J2 is reverse-biased and blocking. Both equivalent circuit transistors
have forward-biased emitter junctions and with reverse-biased collector junctions, both BJT’s can be
considered to be cut off.
Ib2 = 1IK
Ib1
At high voltages, to account for avalanche multiplication effects, the gains are replaced by Mα, where M is
the avalanche multiplication coefficient in equation (3.21). Hence, GT becomes M1α1 + M2α2. By inspection
of equation (3.25) a large anode current results when GT → 1, whence the circuit regenerates with each
transistor driving its counterpart into saturation. All junctions are forward-biased and the total device
voltage is approximately that of a single pn junction, with the anode current limited by the external circuit.
The n2-p1-n1 device acts like a saturated transistor and provides a remote contact to the n2 region.
Therefore the device behaves essentially like a p-i-n diode (p2-i-n1), where the voltage drop across the
i-region is inversely proportional to the recombination rate. Typical SCR static I-V characteristics are
shown in figure 3.22.
At low current levels, α1 and α2 are small because of carrier recombination effects, but increase rapidly
as the current increases. The conventional gate turn-on mechanism is based on these current gain
properties. External gate current starts the regeneration action and the subsequent increase in anode
current causes the gains to increase, thus ensuring a high loop gain, whence the gate current can be
removed. The I-V characteristics in figure 3.22 show this property, where a minimum anode current
(latching current) IL is necessary for the loop gain to increase sufficiently to enable the SCR to latch on by
the regeneration mechanism.
The SCR can be brought into conduction by a number of mechanisms other than via the gate (excluding
the light triggered SCR used in high-voltage dc converters).
If the anode-cathode voltage causes avalanche multiplication of the central junction, the
increased current is sufficient to start the regenerative action. The forward anode-cathode
breakover voltage VBF is dependent on the central junction J2 avalanche voltage and the loop
gain GT according to
VBF Vb (1 - 1 - 2 )1/m Vb (1 - G T )1/m (V) (3.26)
Chapter 3 Power Switching Devices and their Static Electrical Characteristics 96
+
where the avalanche breakdown voltage, at room temperature, for a typical SCR p n central
junction J2 is given by equation (2.3)
V b 5.34 1013 N D-¾ (V) (3.27)
13 14
where ND is the concentration of the high resistivity n2 region when 10 < ND < 5x10 /cc.
Turn-on can also be induced by means of an anode-to-cathode applied dv/dt where the peak
ramp voltage is less than VBF. The increasing voltage is supported by the central blocking
junction J2. The associated scl width increases and a charging or displacement current flows
according to i = d(Cv)/dt. The charging current flows across both the anode and cathode
junctions, causing hole and electron injection respectively. The same mechanism occurs at the
cathode if gate current is applied; hence if the terminal dvldt is large enough, SCR turn-on
occurs.
The forward SCR leakage current, which is the reverse-biased pn junction J2 leakage current,
doubles approximately with every 8K temperature rise. At elevated temperatures, the thermally
generated leakage current (in conjunction with the gains increasing with temperature and
current) can be sufficient to increase the SCR loop gain such that turn-on occurs.
+
The cathode-anode, reverse breakdown voltage VBR is shown in figure 3.22. The anode p2 n2 junction J1
characterises SCR reverse blocking properties and VBR is given by (equation (3.6))
VBR Vb (1 - 2 )1/m
If a high resistivity n2 region, NDn2, is used (in conjunction with low temperature) and breakdown is due to
punch-through to J2, then the terminal breakdown voltage will be approximated by (equation (2.2))
VPT 7.67 10-16 N Dn2 Wn22
where Wn2 is the width of the n2 region. This relationship is valid for both forward and reverse SCR voltage
breakdown arising from punch-through.
97 Power Electronics
An important property of the SCR is that once latched on, the gate condition is of little importance. The
regenerative action holds the device on and SCR turn-off can only be achieved by reducing the anode
current externally to a level below which the loop gain is significantly less than unity.
The doping profiles and cross-sectional views comparing the asymmetrical SCR and conventional SCR are
shown in figure 3.25. In each case the electric field ξ within the p1n2 junction reverse-bias scl is shown and
because the n2 region is lightly doped, the scl extends deeply into it. The scl applied reverse-bias voltage
is mathematically equal to the integral of the electric field, ξ (area under the curve).
+
If, in the conventional SCR, the scl edge reaches the p2 layer, then punch-through has occurred and the
-
SCR turns on. To prevent such a condition and to allow for manufacturing tolerances, the n2 region is kept
thick with the unfortunate consequence that on-state losses, which are proportional to n2 layer thickness,
are high.
-
In the case of the ASCR, a much thinner n2 region is possible since a highly doped n layer adjacent to the
+
p2 anode is utilised as an electric field stopper. The penalty for this layer construction is that in the reverse
+
voltage blocking mode, the n2p2 junction avalanches at a low voltage of a few tens of volts. Thus the
ASCR does not have any usable repetitive reverse-blocking ability, hence the name asymmetrical SCR. By
sacrificing reverse-blocking ability, significant improvements in lower on-state voltage, higher
forward-blocking voltage, and faster turn-off characteristics are attained.
Chapter 3 Power Switching Devices and their Static Electrical Characteristics 98
Figure 3.25. Doping profile, cross-section, and the electric field of J2 in the forward biased off-state for:
(a) and (b) the conventional SCR; (c) and (d) the asymmetrical SCR.
The RCT is electrically equivalent to an SCR in anti-parallel with a diode, but both are integrated into the
same wafer. The reason for integrating the SCR and diode is to minimise external interconnecting lead
inductance. The circuit symbol, cross-sectional wafer view, and doping profile are shown in figure 3.26.
Since no reverse voltage will be applied to the RCT there is only the cathode-side deep p-diffused layer.
This and the ASCR n-region type field stopper result in low forward voltage characteristics. As in the ASCR
case, the highly n-type doped anode end of the wide n-region also allows higher forward voltages to be
blocked. Both anode and cathode shorts can be employed to improve thermal and dv/dt properties. As
shown in figure 3.26a, an amplifying gate can be used to improve initial di/dt capability.
The integral anti-parallel diode comprises an outer ring and is isolated from the central SCR section by
a diffused guard ring, or a groove, or by irradiation lifetime control techniques. The guard ring is important
in that it must confine the carriers associated with the reverse-blocking diode to that region so that these
carriers do not represent a forward displacement current in the SCR section. If the carriers were to spill
over, the device dv/dt rating would be reduced - possibly resulting in false turn-on.
Gold or irradiation lifetime killing can be employed to reduce the turn-off time without significantly
increasing the on-state voltage.
99 Power Electronics
Two anti-parallel connected SCRs can be integrated into one silicon wafer, as shown in figure 3.27. As a
result of integrated symmetry, both devices have near identical electrical properties. The mechanical
feature different to the triac, is that there are two gates – one on each side of the wafer. Also, unlike the
triac, the two SCR sections are physically separated in the wafer to minimise carrier diffusion interaction.
The equivalent circuit comprises two SCRs connected in anti-parallel. As such, one device turning off and
supporting a negative voltage, represents a positive dv/dt impressed across the complementary device,
tending to turn it on. Also, any charge carries which diffusion from the SCR previously on, exasperate the
dv/dt stress experienced by the off SCR.
The two central amplifying gate structures are as for the RCT, in figure 3.26a. A separation of a few
minority carrier lateral diffusion lengths, along with an increased density of cathode shorts along the
separating edge of each cathode and in the amplifying gate region close to the anode of the
complementary SCR, enhance the physical separation. The amplifying gate fingers are angled away from
the separation regions to minimise the shorting effect of the complementary SCR anode emitter shorting.
The on-state voltage of each SCR is fine tuned, match for on-state loss, using electron irradiation.
The gate turn-off thyristor is an SCR that is turned on by forward-biasing the cathode junction and turned
off by reverse-biasing the same junction, thereby preventing the cathode from injecting electrons into the
p1 region. Other than its controlled turn-off properties, the GTO’s characteristics are similar to the
conventional SCR. The basic structure and circuit symbol are shown in figure 3.28.
Chapter 3 Power Switching Devices and their Static Electrical Characteristics 100
The turn-off gain of the GTO, βQ, is defined as the ratio of anode current IA to reverse gate current IGQ, that
is
Q IT / I GQ
(3.28)
1 / (1 2 - 1) 1 / (GT - 1)
Thus for high turn-off gain it is important to make α1 for the npn section as close to unity as possible, while
α2 of the pnp section should be small. A turn-off current gain of 5 is typical.
During the turn-off process, the conducting plasma is squeezed to the centre of the cathode finger,
since the lateral p1 region resistance causes this region to be last in changing from forward to reverse
bias. This region has the least reverse bias and for reliable GTO operation, the final area of the squeezed
plasma must be large enough to prevent an excessive current density. Device failure would be imminent
because of localised overheating.
The doping profile is characterised by a low p1 region sheet resistance and an inter-digitated cathode
region to ensure even distribution of the reverse bias across the cathode junction at turn-off. Both turn-off
and temperature properties are enhanced by using an anode shorting and defocusing technique as shown
in figure 3.29a, but at the expense of reverse-blocking capability and increased on-state voltage.
The shown two-level cathode and gate metallization used on large-area devices allow a flat metal disc
plate for the cathode connection. As with the conventional SCR, a reverse conducting diode structure can
be integrated, as shown in figure 3.29b.
GTO frequency limitations and the need for an external parallel connected capacitive turn-off snubber (to
limit re-applied dv/dt), have motivated its enhancement, resulting in the gate commutated thyristor, GCT.
As shown in figure 3.29c, a number of processing and structural variations to the basic GTO result in a
more robust, snubberless, and versatile high power switch.
n-type buffer
An n-type buffer layer allows a thinner n-drift region. A 40% thinner silicon wafer, for the same
blocking voltage, reduces switching losses and the on-state voltage. An integral reverse
conducting diode is also possible, as with the conventional SCR and GTO.
transparent emitter
A thin lightly doped anode p-emitter is used instead of the normal GTO anode shorts. Some
electrons pass through the layer as if the anode were shorted and recombine at the anode contact
metal interface, without causing hole emission into the n-base. Effectively, a reduced emitter
injection efficiency is achieved without anode shorts. Consequently, gate current triggering
requirements are an order of magnitude lower than for the conventional GTO.
low inductance
A low inductance gate structure, contact, and wafer assembly (<2μH) allow the full anode current
to be shunted from the gate in less than ½µs, before the anode voltage rises at turn-off.
gate
cathode
J3
n+ J2
p
J1
-
n
+
n p n+ p n+ p n+ p n+
anode
diode GTO
(a) (b)
gate anode
n+
p p
-
n
n n+ (c)
p+
The light triggered thyristor is series connected in HVDC applications. Five inch wafers, after 16 major
processing steps (as opposed to 10 for the conventional high voltage thyristor), offer 8kV ratings with
on-state voltages of 2.3V at 3000A, with surge ratings of up to 63kA. Turn-off time is 350μs, and turn-on
requires about 40mW of light power for 10μs, with a half microsecond rise time. The light causes the
generation of hole-electron pairs and these free charges create a change in the electrical characteristics of
the semiconductor region. Consequently a current flows across the exposed junction which is equivalent
to gate current. Because of the low turn-on energy, multiple cascaded amplifying gates are laterally
integrated to achieve modest initial current rises limited to 300A/μs. Reapplied voltages are limited to
3500V/μs.
A temperature dependant over voltage protection mechanism is also integrated into the wafer, the
characteristics of which suffer from a wide production spread.
Pictorial representations of the triac are shown in figure 3.30. The triac is a thyristor device that can switch
current in either direction by applying a low-power trigger current pulse of either polarity between the gate
and main terminal M1. The main terminal I-V characteristics, device symbol, and four trigger modes for
the triac are shown in figure 3.31.
The triac comprises two SCR structures, p1-n1-p2-n2 and p2-n1-p1-n4 which utilise the n3 and p2 regions
for turn-on. It should be noted that n2-p2, p1-n4, and p2-n3 are judiciously connected by terminal
metallizations, but are laterally separated from their associated active parts.
103 Power Electronics
The four different trigger modes of the triac are illustrated in figure 3.32 and the turn-on mechanism for
each mode is as follows.
The various turn-on mechanisms are highly reliant on the judicious lateral separation of the various
contacts and regions. The main advantage of the triac lies in the fact that two anti-parallel SCR’s in the one
silicon structure can be triggered into conduction from the one gate. Because of the need for extra
structure layers, hence processing steps, some conventional SCR characteristics are sacrificed and poor
device area utilisation results. Two anti-parallel SCRs therefore tend to be more robust than a triac but
unlike the BCT device in section 3.3.4, only one gate drive circuit is needed for the triac.
Chapter 3 Power Switching Devices and their Static Electrical Characteristics 104
M2 positive
positive half cycle
IGT IGT
negative positive
IGT IGT
negative positive
M2 negative
negative half cycle
Figure 3.32. Current flow for the four different turn-on triggering modes of the triac.
Power thyristors are usually encapsulated as a floating disk in a ceramic package with Cu connection
disks, as in figure 3.33a and figure 6.29. This offers the following features compared with high current
IGBT modules.
increased reliability with power cycling failure decreased by a factor of 10
lower packaging connection and internal inductance
explosion rated and stable short circuit failure mode
suitable for liquid immersion
lower thermal resistance due to double sided cooling
Chapter 3 Power Switching Devices and their Static Electrical Characteristics 106
Typical thermal and mechanical properties for a 4.5kV, 2.4kA igbt 16.8cm diameter, 26mm thick 2kg
capsule are 19kW dissipation with associated thermal resistances of 8.5K/kW from the collector,
13.5K/kW for the emitter side, giving a double side cooling figure of 5.2k/kW (0.0052K/W).
Advantageous features of high current IGBT modules, as in figure 3.33b, are an electrically isolated base
plate (based on a Aℓ3N4 or Aℓ203 substrate) and low cost connections and heatsink mounting (see figures
5.8 and 5.22). The relative features of aluminium oxide and aluminium nitride substrates can be found in
Chapter 5.8. No isolated pressure clamping arrangement is necessary with flat pack IGBT modules.
Typical thermal and mechanical properties for a 6.5kV, 1000A IGBT 190x140x48mm thick 1.8kg capsule
are 10.2kW dissipation with associated thermal resistances of 11K/kW for the IGBT die and 17K/kW for
the diodes, with a maximum junction temperature of 150°C.
The emergence of SiC power switching devices has presented packaging challenges. Package internal
substrate and base plate assemblies currently prevent the high temperature capabilities of SiC from being
exploited at junction temperatures above 300°C.
Details of high temperature die and substrate attachment can be found in Chapter 5.12.
Reading list
Baliga, B. J., Modern Power Devices, John Wiley-Interscience, 1987.
Ghandhi, S. K., Semiconductor Power Devices, John Wiley-Interscience, New York, 1977.
Grafham, D. R. et al., SCR Manual, General Electric Company, 6th edition, 1979.
Van Zeghbroeck, B., Principles of Semiconductor Devices,
http://ece-www.colorado.edu/~bart/book, 2004.
Chapter 3 Power Switching Devices and their Static Electrical Characteristics 108
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