GA-Z87X-D3H Rev 1.

Structure Introductions
Power Sequence
Measure Points

JEFF.KO
 Curriculum Content
● Z87X-D3H Structure Introductions :
• Intel Shark Bay Platform Introduction
• Z87X-D3H Structure Introduction
• Z87X-D3H Power Sequence & Timing
• Z87X-D3H All Voltage Block Diagram
• Z87X-D3H PWOK / RESET Block Diagram
• Clock Generator Integrated Z87
• 6 PCI Express Slot Connectivity Circuit / PCI Express Gen.3
• On board DVI/HDMI/VGA block diagram
● Z87X-D3H Check Points :
• Z87X-D3H Main voltage signal check points list
• Z87X-D3H Power Sequence check points list

P.1
 Intel Shark Bay Platform Introduction
1. Introduction : The Shark Bay platform based on the Haswell processor and Lynx Point Platform
Controller Hub (PCH) , The Haswell Processor along with the Lynx Point PCH is designed for a 2-chip
platform enabling higher performance, lower cost, easier validation and improved x-y footprint.

– The Haswell Processor: The processor has the Memory Interface, PCI Express* and the Direct
Media Interface (DMI) integrated into the processor .The processor includes Integrated Display Engine,
GPU , Integrated memory controller and three DDI ports. Each DDI port supports Display Port or HDMI
or DVI. The processor supports two channels of DDR3/DDR3L @ 1.5V with a maximum of two UDIMMs
per channel. Denlow-WS supports UDIMM ECC. The PCI Express* port(s) are fully-compliant with the
PCI Express Base Specification, Revision 3.0.
– The Lynx Point PCH : The Lynx Point PCH connects to the processor via the Direct Media
Interface and Flexible Display Interface. The PCH is ACPI compliant and can support the Full-on,
Suspend to RAM, Suspend to Disk, Soft-Off and Deep Sx power management states. The PCH is
capable of supporting up to 8 PCI Express 2.0 compliant root ports; up to 6 SATA ports at 1.5 Gbps, 3
Gbps and 6 Gbps; and up to 14 USB 2.0 ports that can be mapped to a single xHCI controller or shared
across two separate EHCI controllers.
Furthermore, up to 6 of the 14 possible USB 2.0 ports can be configured as USB 3.0 ports mapped to
the xHCI controller. Flexible IO technology allows some high speed signals to be used as PCI Express
ports, SATA ports or USB 3.0 ports. Refer to the Lynx Point External Design Specification for more
details about supported features and capabilities.

P.2
 System Block Diagram (Haswell + Lynx Point)

P.3
 Fully Integrated Voltage Regulator (FIVR)

P.4
 Lynx Point Overview

P.5
 Z87X-D3H Block Diagram
PCIE-16 GEN3 CHANNEL A
PCI EXPRESS X16 DDRIII DDRIII DIMM X 2
INTEL LGA1150 BUS

DISPLAY
(Haswell) CHANNEL B
DVI HDMI DDRIII DIMM X 2

FDI DMI2.0
DISPLAY
RGB SATA III / II
SATA III X6
PCI EXPRESS X 4 PCIE-1 GEN2
SPI BUS

PCI EXPRESS X1 1/2

PCIE-1 GEN2
PCH (Lynx Point) SPI Dual BIOS (64M)
LPC BUS
(Z87/H87)
PCIE-1 GEN2
Intel I217 LAN
TPM
USB2.0
USB2.0 PORTS 0~13
USB3.0 LPC I/O ITE8728
USB3.0 PORTS 0~5

PCIE-1 GEN2 AZALIA BUS

RENESAS UPD720210
I/O PORTS :
PCI Realtek ALC892 COMA KB/PS2
PCI SLOT 1/2 ITE8892

FRONT PANEL/
CLOCK GENERATOR AUDIO PORTS:FRONT AUDIO ,LIN_OUT, CPU / SYS FAN
LINE_IN,MIC,CD_IN,SURR,SURR BACK,CEN/LFE

P.6
 Z87X-D3H Power Sequence Rev 1.0
25MHz

4. 3VDUAL_PCH 3. FET
14. N_PCH_VRMPWRGD
Z87
N_PCH_DPWROK
DPWROK CIRCUIT
O_PWROK1
O_-RSMRST 4.. 3VDUAL 3.
N_ME_PWROK
(Lynx Point) FET
Output Clock
17. 2.
PCI
18.
6. 5. 8.19. WGI217LM
IT8892E

O_PWRBTSW
VCC15_EN,
VCC1_05_EN 20. TPM G_-PCIRST

-PFMRST
16. VTT_PWRGD, PCIEX1_1,2,3 FET
CIRCUIT

PWR_EN PCIEX16,8,4
N_CPUPWROK

21. -DPCIE_RST
ITE_PWROK
ITE -PWRBTSW 7.
IT8728F PWOK 15.
ATXPG
POWER
1. 5VSB
CIRCUIT BUTTON

-PSON 9.
10.
11. 10.
ATX
POWER
MAIN POWER

VTT_PWRGD VCC3
13. SYSTEM VOLTAGE
VR_RDY

1.CPU:VCORE,VCCST,DDR_15V,CPU_VTT_OR,
IR3563 LGA1150 2.Z87 :VCC1_05_PCH,VCC1_5_PCH,VCC1_05_ME,VC
CIO2PCH,VCC3,VCC3,_ME,VCC3_DAC,3VDUAL_PCH
IR3553
(Haswell) ,3VDUAL,N_RTCVDD
12. VCORE 3. IT8728F : 3VDUAL_PCH,3VDUAL,VCC3,VBAT
9. 6. 5. VCCST_PWRGD 4. DDR III : DDRVTT,DDR_15V,VCC3

7
 Z87 Power Sequencing and Timing - 1
PSU T1< 500ms
PS_ON_N
VSB MAIN
5VDUAL

SLP_S4#

SLP_S3# PCI/PCIe Spec: 100ms min

PSU Power rails
Rise: 0.2 – 20ms
12V , 5V PSU: <= 20ms

3V PCH t205a
>1us*2
VDDQ (1.5V)
<25ms*1
PCH Core (1.05V) >1us*2 >1ms*2
(VCCST) PCH t205a
PCH t205a
1.5V IO (V_1P5_IO)
<25ms*1
PCH_DAC & TS (1.5v) PCH t205a CPU Pwrgood assertion
TA VRD12.5 <5ms Reset deassertion
12V & SLP_S3#
VR_EN TB VID Based
VRD12.5: < 1ms VBOOT
TA
VCC / VCORE
VRD12.5: < 5ms
TC
VR_READY VRD12.5: <100us
PSU T3:
PWRGD_PSU 100ms - 500ms
Edge 10ms max
PCH_PWROK VR_READY &
PSU_PWRGD
(VCCST_PWRGD) PCH t206

PCH_DRAMPWROK (1ms)
NOTE: DDR spec requires that DDR RESET# be asserted during VDDQ power ramp cycle
SM_DRAMRST# SYS_PWROK CPU PWRGOOD
Reset#/PLTRST#

P.8
 Z87 Power Sequencing and Timing - 2

PCH_PWROK
(VCCST_PWRGD)
PCH_DRAMPWROK
SM_DRAMRST#
BCLK , PCIe
CLKS
PWRGOOD PCH t209
(1, 5, 50, or 100ms)
(PCH PROCPWRGD)
CFG[x] Strapping option Driven

(Straps)
Inactive / Disabled Enabled
THERMTRIP#
VCCIO_Out
VCOMP_Out
SYS_PWROK PROCPWRGD
PCH t210
SYS_PWROK
(30us, 1, 2, or 5ms)
RESET# / PLTRST# PLTRST# Deassertion = PCH PWROK & SYS_PWROK & t210 Timer expired

DMI

P.9
 VCCST Power Rail Sequencing

Source Destination Signal

VRs CPU VDDQ(1.5V)

VRs CPU VccST
(VCC1_05_PCH)

VRs CPU VCCIN

Logic CPU VccST_PWRGD

Logic PCH PWROK

P.10
 Z87X-D3H All Voltage Block Diagram
VCORE0
VCORE
V12 IR3563 IR3553*8 CPU_VAXG
LGA1150
5VDUAL DDR_15V VCCIOA_L
IR3570 IR3598*1 Haswell
CPU_VTT_OR

DDR3

VCC1_05_PCH VCCIO2PCH
CIRCUIT

VCC1_05_ME

VCC1_5_PCH Z87
VCC3 CIRCUIT
VCC3 Lynx
Point
VCC3_ME
3VDUAL_PCH
5VSB FET

5VDUAL 3VDUAL
FET FET

VCC3_DAC
2N7002

P.11
 Z87X-D3H PWOK / RESET Block Diagram

ATX POWER 4.
-PFMRST
1.
PWOK
DRAM_PWROK

ITE
ME_PWROK 3.
2. PWROK1
Z87 CPUPWROK
IT8728F Lynx
Point
5. -CPURST
-PFMRST2

LAN TPM
PCIEX1_1,2,3
-PCIE_RST VCCST_PWRGD
PCIEX16 IT8892E
LGA1150
PCIEX8
Haswell
PCIEX4 -PCIRST
PCI
 25MHz Z87X-D3H Clock Generator Integrated
N_LPC33 (I/O CLK IN) ITE
O_LPCCLK48 (K/B CLK IN) 8728F
C_ACZ_BITCLK
ALC
Clock Generator Integrated Z87
N_PCHCLK14 Mount for integrated clock Generation mode
892

N_CLK_GND,N_-CLK_GND N_ICH_SPI_CLK SPI BIOS

N_PCH33 CLKIN_PCILOOPBACK
T_TPMCLK TPM
G_PBCLK ,G_-PBCLK ITE 25MHz
8892
LB_SRCCLK_LAN,LB_-SRCCLK_LAN LAN
WGI217LM
PA_SRCCLK_3GIO,PA_-SRCCLK_3GIO PCIEX16

PI_PCIE_CLK1, PI_-PCIE_CLK1
PCIEX1_1
PJ_PCIE_CLK2, PJ_-PCIE_CLK2
PCIEX1_2
PJ_PCIE_CLK3, PJ_-PCIE_CLK3 PCIEX1_3
PE_SRCCLK_3GPIO1,PE_-SRCCLK_3GPIO1
PCIEX8
PCIEX4
N_CPUCLK ,N_-CPUCLK DCLKA [0;3]+/- DDR3 CHANNEL A,B
N_DP_CLK,N_-DP_CLK LGA1150 DCLKB[0;3] +/-
N_CK_DPCLK, N_-CK-DPCLK
Haswell
N_CLK_RCOMP
VCC1_5_PCH

P.13
 6 PCI Express Slot Connectivity Circuit
PCIEX1_1 PCIEX1_3 PCIEX1_2 PCIEX4 PCIEX8 PCIEX16

Z87 PI_PCIE_TN/P1
PI_PCIE_IN/P1
Lynx Point PK_PCIE_TN/P2
PK_PCIE_IN/P2
U1
U14,U3,
PI3PCIE2415ZHE U4,U5
SEL PCIEX4/X1 SWITCH
CBT04083BBS*4
PCI Express Gen 3 Switch
X4_SW SEL

*
PCH_PCIE_ON/P4 PCH_PCIE_ON/P4C
PCH_PCIE_IN/P4

PP_PCIEX4_ON/P[1;3]
PP_PCIEX4_IN/P[1;3]
*
A_DMI_[0;3]TXP
A_DMI_[0;3]TXN
LGA1150
A_DMI_[0;3]RXP
A_DMI_[0;3]RXN Haswell

P.14
 HDMI Block Diagram
HDMI

LGA1150 VCC3
HU1
PTN3360D
Haswell
HDMI_TXC HDMI_CLK_P OUT_D1+ HDMITXCP
HDMI_TXC- HDMI_CLK_N OUT_D1- HDMITXCN
HDMI_TX1 HDMI_DAT_P1 HDMITXP1
OUT_D2+
HDMI_TX1- OUT_D2- HDMITXN1
HDMI_DAT_N1
HDMI_TX2- HDMI_DAT_N2 OUT_D3+ HDMITXN2

HDMI_TX2 OUT_D3- HDMITXP2

HDMI_DAT_P2
OUT_D4+ HDMITXN0
HDMI_TX0- HDMI_DAT_N0
OUT_D4- HDMITXP0
HDMI_TX0 HDMI_DAT_P0
N_HDMI_HDP_F

PCH N_DDPC_CTRLCLK
HDMI_SCLDDC
N_DDPC_CTRLDATA
HDMI_SDADDC
OE
HDMI_PLUG
VCC3 DDC_EN
OC_0,1,2,3 FUSEVCC_R1
EQ_0,1

P.15
 DVI Block Diagram
DVI

LGA1150 VCC3 HU2

Haswell ASM1442
DVI_TX0 DVI_DAT_P0 OUT_D1+ DVITX0+
DVI_TX0- DVI_DAT_N0 OUT_D1- DVITX0-
DVI_TXC DVI_CLK_P DVITXC+
OUT_D2+
DVI_TXC- OUT_D2- DVITXC-
DVI_CLK_N
DVI_TX2- DVI_DAT_N2 OUT_D3+ DVITX2-
OUT_D3- DVITX2+
DVI_TX2 DVI_DAT_P2
DVI_TX1- DVI_DAT_N1 OUT_D4+ DVITX1-

DVI_TX1 OUT_D4- DVITX1+

DVI_DAT_P1
DVI_HDP_F
N_DDPB_CTRLCLK
PCH N_DDPB_CTRLDATA
DVI_SCL
DVI_SDA
OE
DVI_HP
DVI_EN
VCC3 DDC_EN
OC_0,1,2,3 FUSEVCC_RB
EQ_0,1

P.16
 VGA Block Diagram
VCC
VCC3

VGA
Z87 VCC3 VCC

VCC
Lynx Point VGADDCDATA
N_DDCDATA

VCC
VGADDCCLK
N_DDCCLK

N_R VGA_R
N_G VGA_G
N_B VGA_B

H_SYNC N_GHSYNC

V_SYNC N_GVSYNC

N_VGA_RSET
FUSEVCC_RB

17