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    Question Bank - M5 To M7

    Uploaded by

    Pieter Marker
    This document contains questions from modules 5-7 related to computer organization topics like parallel processing, pipelining, hazards, CISC vs RISC architectures, I/O interfaces, memory hierarchy including cache mapping techniques, and virtual memory. Specifically, it asks about Flynn's taxonomy of parallel computers, configuring a pipeline to perform arithmetic operations on data streams, analyzing space-time diagrams of pipeline processing, calculating speedup from pipelining, the stages of floating point addition/subtraction in a pipeline, instruction pipelining, types of pipeline hazards and solutions, differences between CISC and RISC ISAs, I/O devices, bus connections, synchronous vs asynchronous transfer, interrupt handling including daisy chain priority

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    © All Rights Reserved
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    Question Bank - M5 To M7

    Uploaded by

    Pieter Marker
    59 views2 pages
    This document contains questions from modules 5-7 related to computer organization topics like parallel processing, pipelining, hazards, CISC vs RISC architectures, I/O interfaces, memory hierarchy including cache mapping techniques, and virtual memory. Specifically, it asks about Flynn's taxonomy of parallel computers, configuring a pipeline to perform arithmetic operations on data streams, analyzing space-time diagrams of pipeline processing, calculating speedup from pipelining, the stages of floating point addition/subtraction in a pipeline, instruction pipelining, types of pipeline hazards and solutions, differences between CISC and RISC ISAs, I/O devices, bus connections, synchronous vs asynchronous transfer, interrupt handling including daisy chain priority

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    Question Bank - M5 to M7

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    This document contains questions from modules 5-7 related to computer organization topics like parallel processing, pipelining, hazards, CISC vs RISC architectures, I/O interfaces, memory hierarchy including cache mapping techniques, and virtual memory. Specifically, it asks about Flynn's taxonomy of parallel computers, configuring a pipeline to perform arithmetic operations on data streams, analyzing space-time diagrams of pipeline processing, calculating speedup from pipelining, the stages of floating point addition/subtraction in a pipeline, instruction pipelining, types of pipeline hazards and solutions, differences between CISC and RISC ISAs, I/O devices, bus connections, synchronous vs asynchronous transfer, interrupt handling including daisy chain priority

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    59 views2 pages

    Question Bank - M5 To M7

    Uploaded by

    Pieter Marker
    This document contains questions from modules 5-7 related to computer organization topics like parallel processing, pipelining, hazards, CISC vs RISC architectures, I/O interfaces, memory hierarchy including cache mapping techniques, and virtual memory. Specifically, it asks about Flynn's taxonomy of parallel computers, configuring a pipeline to perform arithmetic operations on data streams, analyzing space-time diagrams of pipeline processing, calculating speedup from pipelining, the stages of floating point addition/subtraction in a pipeline, instruction pipelining, types of pipeline hazards and solutions, differences between CISC and RISC ISAs, I/O devices, bus connections, synchronous vs asynchronous transfer, interrupt handling including daisy chain priority

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    B Tech – II : Computer Organization(SECE2040)

    Question Bank for modules covered after Second Internal

    Module 5
    1. What is parallel processing? How Flynn’s classification divides computers into four
    major components?
    2. In certain scientific computations it is necessary to perform the arithmetic operations
    (Ai + Bi) (Ci + Di) with a stream of numbers. Specify a pipeline configuration to carry
    out this task. List the contents of all registers in the pipeline for i=1 through 6
    3. Draw a space-time diagram for a six-segment pipeline showing the time it takes to
    process eight tasks. Determine the number of clock cycles that it takes to process 200
    tasks in a six-segment pipeline.
    4. A non-pipeline system takes 50ns to process a task. The same task can be processed
    in a six-segment pipeline with a clock cycle of 10 ns. Determine the speedup ration of
    the pipeline for 100 tasks. What is the maximum speed that can be achieved?
    5. What are the sub-operations that are performed in the four segments pipeline of
    floating point addition and subtraction?Explain by addition of following two
    numbers:
    X = 3.25 x 10 3
    Y = 2.63 x 10-1

    Draw a flowchart for floating-point addition and subtraction.

    6. What are the four-segments in instruction pipeline? Draw a flow-chart to show the
    processing of instruction cycle in CPU with a four-segment pipeline.
    7. What are the different types of hazards (conflicts) that can be found in pipeline
    processing? What are the possible solutions for resolving each hazard?
    8. Differentiate between CISC and RISC.

    Module 6

    9. What do you mean by Peripherals? What are the various types of peripherals?
    10. What is the purpose of Input-Output Interface? What are the differences between CPU
    and I/O Device that can be resolved by Input-Output Interface?
    11. Explain the connection of I/O bus to input-output device? What are the various types
    of commands that are received by I/O interface for particular I/O device?
    12. Differentiate the following:
    a. Isolated vs. Memory-Mapped I/O
    b. Synchronous Data Transfer vs. Asynchronous Data Transfer
    c. Strobe vs. Handshaking
    d. Source-initiated Strobe vs. Destination-initiated Strobe
    e. Source-initiated Handshaking vs. Destination-initiated Handshaking
    13. What are the various types of Data Transfer? Explain in brief.
    14. What do you mean by Priority Interrupt? Show the stage of daisy-chain priority
    arrangement. What happens in the daisy-chain priority interrupt, when device 1
    request an interrupt after device 2 has sent an interrupt request to the CPU but before
    CPU responds with the interrupt acknowledge?
    15. What is the advantage of DMA (Direct Memory Transfer)? Explain the following terms
    with respect DMA transfer.
    a. Bus Request
    b. Bus Grant
    c. Burst Transfer
    d. Cycle- Stealing
    16. With the supporting diagram, explain the functionality of DMA controller with the use
    of all registers and control logics.

    Module 7
    17. Draw a neat diagram of memory hierarchy of computer system. Also indicate relative
    variation of size, speed and cost per bit in the hierarchy.
    18. What is main Memory? Draw the block diagram and function table of typical RAM chip
    (128*8) and ROM chip (512*8).
    19. How many 128*8 RAM chips are needed to provide a memory capacity of 2048 bytes?
    How many lines of the address bus must be used to access 2048 bytes of memory?
    How many of these lines will be common to all chips?
    How many lines must be decoded for chip select? Specify the size of the decoders.
    20. What is associative memory (Content Addressable Memory)? Explain the working of
    Associative Memory with Block Diagram.
    21. What do you mean by locality of reference? How cache memory used that concept to
    achieve faster speed in program execution.
    22. What are the three types of mapping procedures in organization of cache memory?
    23. Consider a system with main memory of size 32K*12. The cache memory of size
    512*12.The CPU communicates with both memories. Direct mapping is implemented
    in organization of cache. What will be size of Tag and Index? Explain the addressing
    relationships between main and cache memories for given memory organization.
    24. Distinguish between the following: Direct Mapping and Set-Associative Mapping.
    25. In Virtual Memory, An address space is specified by 24 bits and the corresponding
    memory space by 16 bits. How many words are there in address space? How many
    words are there in the memory space? If a page consists of 2K words, how many pages
    and blocks are there in the system?

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