INSTRUCTION SET

CHARACTERISTICS AND
FUNCTIONS
CHAPTER # 7 Computer Organization & Architecture
 What is an Instruction Set?
S H E H E R YAR MALI K

 The complete collection of different instructions that

the processor can execute or understand is referred
to as the processor’s instruction set
 Machine Code
 Binary
 Usually represented by assembly codes

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 Elements of an Instruction
S H E H E R YAR MALI K

 Operation code (Op code)

 Specifies the operation to be performed
 Source Operand reference
 To this
 The operation may involve one or more source operands
 Result Operand reference
 Put the answer here
 Next Instruction Reference
 This tells the processor where to fetch the next instruction
after the execution of this instruction is complete

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 Instruction Cycle State Diagram
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 Where the Source and Result Operands can be
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 Main or virtual memory

 As with next instruction references, the main or virtual
memory address must be supplied
 I/O device
 The instruction must specify the I/O module and device for
the operation
 Processor register
 A processor contains one or more registers that may be
referenced by machine instructions
 Immediate
 The value of the operand is contained in a field in the
instruction being executed
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 Instruction Representation
S H E H E R YAR MALI K

 In machine code each instruction has a unique bit

pattern
 For human consumption (well, programmers
anyway) a symbolic representation is used
 e.g. ADD, SUB, LOAD
 Operands can also be represented in this way
 ADD A,B

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 Simple Instruction Format
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 Instruction Types
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 Data processing
 Data storage (main memory)
 Data movement (I/O)
 Program flow control

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 Number of Addresses
S H E H E R YAR MALI K

 3 addresses
 Operand 1, Operand 2, Result
 a = b + c;
 ADD a, b, c
 May be a forth - next instruction (usually implicit)
 Not common
 Needs very long words to hold everything

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 Number of Addresses
S H E H E R YAR MALI K

 2 addresses
 One address doubles as operand and result
 a=a+b
 ADD a, b
 Reduces length of instruction
 Requires some extra work
 Temporary storage to hold some results

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 Number of Addresses
S H E H E R YAR MALI K

 1 address
 Implicit second address
 ADD a
 Usually a register (accumulator)
 Common on early machines

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 Number of Addresses
S H E H E R YAR MALI K

 0 (zero) addresses
 All addresses implicit
 Uses a stack
 e.g. c = a + b
 push a
 push b
 Add
 pop c

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 Number of Addresses
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 How Many Addresses
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 More addresses
 More complex (powerful?) instructions
 More registers
 Inter-register operations are quicker
 Fewer instructions per program
 Fewer addresses
 Less complex (powerful?) instructions
 More instructions per program
 Faster fetch/execution of instructions

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 Instruction Set Design Decisions
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 Operation range
 How many ops?
 What can they do?
 How complex are they?
 Data types
 The various types of data upon which operations are performed
 Instruction formats
 Instruction length in bits
 Length of op code field
 Number of addresses
 Size of various fields, etc.

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 Instruction Set Design Decisions
S H E H E R YAR MALI K

 Registers
 Number of CPU registers available
 Which operations can be performed on which registers?
 Addressing modes
 RISC v CISC

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 Types of Operand
S H E H E R YAR MALI K

 Addresses
 Numbers
 Integer/floating point
 Characters
 ASCII etc.
 Logical Data
 Bits or flags

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 x86 Data Types
S H E H E R YAR MALI K

 8 bit Byte
 16 bit word
 32 bit double word
 64 bit quad word
 128 bit double quadword
 Addressing is by 8 bit unit
 Words do not need to align at even-numbered
address
 Data accessed across 32 bit bus in units of double
word read at addresses divisible by 4
 Little endian
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 x86 Numeric Data Formats
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 ARM Data Types
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 8 (byte), 16 (halfword), 32 (word) bits

 Halfword and word accesses should be word aligned
 Unsigned integer interpretation supported for all
types
 Twos-complement signed integer interpretation
supported for all types
 Majority of implementations do not provide floating-
point hardware
 Saves power and area
 Floating-point arithmetic implemented in software
 Optional floating-point coprocessor
 Single- and double-precision IEEE 754 floating point data
types

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 Types of Operation
S H E H E R YAR MALI K

 Data Transfer
 Arithmetic
 Logical
 Conversion
 I/O
 System Control
 Transfer of Control

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 Types of Operation
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 Types of Operation
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 Data Transfer
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 Specify
 Source
 Destination
 Amount of data
 May be different instructions for different
movements
 e.g. IBM 370
 Or one instruction and different addresses
 e.g. VAX

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 Arithmetic
S H E H E R YAR MALI K

 Add, Subtract, Multiply, Divide

 Signed Integer
 Floating point
 May include
 Increment (a++)
 Decrement (a--)
 Negate (-a)

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 Logical
S H E H E R YAR MALI K

 Bitwise operations
 AND
 OR
 NOT
 Test
 Compare

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 Conversion
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 E.g. Binary to Decimal

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 Input/Output
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 May be specific instructions

 May be done using data movement instructions
(memory mapped)
 May be done by a separate controller (DMA)
 Examples
 Input
 Output
 Start I/O

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 Systems Control
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 Privileged instructions
 CPU needs to be in specific state
 Ring 0 on 80386+
 Kernel mode
 For operating systems use

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 Transfer of Control
S H E H E R YAR MALI K

 Branch
 e.g. branch to x if result is zero
 Skip
 e.g. increment and skip if zero
 ISZ Register1
 Branch xxxx
 ADD A
 Subroutine call
 c.f. interrupt call

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 Branch Instruction
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  x86 Operation Types
S H E H E R YAR MALI K

Chapter # 7 Computer Organization & Architecture 32

  x86 Operation Types
S H E H E R YAR MALI K

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 x86 Single-Instruction, Multiple-Data (SIMD)
Instructions
S H E H E R YAR MALI K

 1996 Intel introduced MMX technology into its Pentium

product line
 MMX is a set of highly optimized instructions for multimedia tasks
 Video and audio data are typically composed of large
arrays of small data types
 Three new data types are defined in MMX
 Packed byte
 Packed word
 Packed doubleword
 Each data type is 64 bits in length and consists of multiple
smaller data fields, each of which holds a fixed-point
integer

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 MMX Instruction Set
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Chapter # 7 Computer Organization & Architecture 35

 ARM Operation Types
S H E H E R YAR MALI K

 Load and store instructions

 Branch instructions
 Data-processing instructions
 Multiply instructions
 Parallel addition and subtraction instructions
 Extend instructions
 Status register access instructions

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 Byte Order (A portion of chips?)
S H E H E R YAR MALI K

 What order do we read numbers that occupy more

than one byte
 e.g. (numbers in hex to make it easy to read)
 12345678 can be stored in 4x8bit locations as
follows
 Address Value (1) Value(2)
 184 12 78
 185 34 56
 186 56 34
 186 78 12

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 Byte Order Names
S H E H E R YAR MALI K

 The problem is called Endian

 Big endian
 In big endian, you store the most significant byte in the
smallest address.
 Little-endian
 In little endian, you store the least significant byte in the
smallest address

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 Example of C Data Structure
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Chapter # 7 Computer Organization & Architecture 39

 Alternative View of Memory Map
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Chapter # 7 Computer Organization & Architecture 40

 Byte Order Standard
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 Pentium (x86), VAX are little-endian

 IBM 370, Motorola 680x0 (Mac), and most RISC are
big-endian
 Internet is big-endian
 Makes writing Internet programs on PC more awkward!
 WinSock provides htoi and itoh (Host to Internet & Internet
to Host) functions to convert

Chapter # 7 Computer Organization & Architecture 41