Datasheet

RT3662AC
Dual-Output PWM Controller with 3 Integrated Drivers for

AMD SVI2 Mobile CPU Power Supply
General Description Features
RT3662AC is a dual-output PWM controller with 3  2/1-Phase (VDD) + 1/0-Phase (VDDNB) PWM
integrated drivers, and it is compliant with AMD SVI2 Controller
Voltage Regulator Specification to support both CPU  3 Embedded MOSFET Drivers
core (VDD) and Northbridge portion of CPU (VDDNB).  G-NAVPTM Topology
The RT3662AC features CCRCOT (Constant Current  Support Dynamic Load-Line and Zero Load-Line
Ripple Constant On-Time) with G-NAVP (Green-Native  Diode Emulation Mode at Light Load Condition
AVP), which is Richtek's proprietary topology. G-NAVP  SVI2 Interface to Comply with AMD Power
makes it an easy setting controller to meet all AMD Management Protocol
AVP (Adaptive Voltage Positioning) VDD/VDDNB  Adjustable Current Gain Capability
requirements. The droop is easily programmed by  DVID Enhancement
setting the DC gain of the error amplifier. With proper  0.5% DAC Accuracy
compensation, the load transient response can achieve  Differential Remote Voltage Sensing
optimized AVP performance. The controller also uses  Build-in ADC for Pin Setting Programming,
the interface to issue VOTF Complete and to send Thermal Indication and VOUT, IOUT Reporting
digitally encoded voltage and current values for the  Fast Transient Response
VDD/VDDNB domains. The RT3662AC can operate in  Power Good Indicator
diode emulation mode to enhance the light load  Thermal Indicator (VRHOT_L)
efficiency. And it provides the current gain adjustment  OVP, UVP and UVLO
capability by pin setting. RT3662AC provides power  Over Current Protection
good indication, thermal indication (VRHOT_L), and it
features complete fault protection functions including
Applications
 AMD SVI2 Mobile CPU
over current, over voltage and under voltage.
 Laptop Computer
Marking Information
RT3662ACGQW : Product Number
RT3662AC YMDNN : Date Code
GQW
YMDNN
Simplified Application Circuit
RT3662AC
VRHOT_L PHASE1 MOSFET VVDD
SVC
To CPU PHASE2 MOSFET
SVD
SVT PHASE_NB MOSFET VVDDNB
Copyright © 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
DS3662AC-00 March 2016 www.richtek.com
1
RT3662AC
Ordering Information Pin Configurations
RT3662AC (TOP VIEW)
Package Type
UGATE_NB
PHASE_NB
LGATE_NB
QW : WQFN-40L 5x5 (W-Type)
UGATE1
PHASE2
PHASE1
LGATE2
LGATE1
Lead Plating System
BOOT1
PVCC
G : Green (Halogen Free and Pb Free)
Note : 40 39 38 37 36 35 34 33 32 31
UGATE2 1 30 BOOT_NB
Richtek products are : 29 EN
BOOT2 2
 RoHS compliant and compatible with the current PGOOD 3 28 VIN

RGND 4 27 COMP_NB
requirements of IPC/JEDEC J-STD-020. COMP 5 26 FB_NB
GND
FB 6 25 ISENP_NB
 Suitable for use in SnPb or Pb-free soldering processes. ISENN_NB
ISEN2P 7 24
VSEN 8
41
23 TSEN_NB
ISEN1P 9 22 VDDIO
ISEN1N 10 21 SVT
11 12 13 14 15 16 17 18 19 20
VRHOT_L
TSEN
SET1
IMON
VREF_PINSET
IMON_NB
VCC
PWROK
SVC
SVD
WQFN-40L 5x5
Functional Pin Description

Pin No. Pin Name Pin Function
Upper Gate Driver Output of Phase 2 for VDD Controller. Connect this pin to
1 UGATE2
the gate input of high side MOSFET.
Bootstrap Supply of VDD Controller for Phase 2 High Side MOSFET. This
2 BOOT2
pin powers high side MOSFET driver.
Power Good Indicator for the VDD and VDDNB Controller. This pin is an
3 PGOOD
open drain output.
Return Ground of VDD and VDDNB Controllers. This pin is the common
4 RGND negative input of output voltage differential remote sense of VDD and
VDDNB controllers.
5 COMP Error Amplifier Output Pin of the VDD Controller.
Output Voltage Feedback Input of VDD Controller. This pin is the negative
6 FB
input of the error amplifier for the VDD controller.
7 ISEN2P Positive Current Sense Input of Phase 2 for VDD Controller.
VDD Controller Voltage Sense Input. This pin is connected to the terminal of
8 VSEN
VDD controller output voltage.
9 ISEN1P Positive Current Sense Input of Phase 1 for VDD Controller.
Common Negative Current Sense Input of Phase1 and Phase 2 for VDD
10 ISEN1N
Controller.
11 VRHOT_L Thermal Indicator. This pin is an open drain output. (Active low)
www.richtek.com DS3662AC-00 March 2016
2
RT3662AC
This Pin Provides Two Functions: Platform Setting, Platform can use this pin
to set frequency of VDD and VDDNB Controllers, initial offset and per-phase
12 TSEN OCP threshold of VDD Controller. The other function is thermal sense input
for VRHOT indicator. Connect the NTC network for thermal sensing to this
pin.
Platform Setting Pin. Platform can use this pin to set the AI gain of VDD and
13 SET1 VDDNB Controllers, VDDNB Voltage Reporting Compensation bit1~bit3 and
VDD Controller QRTH.
Current Monitor Output for the VDD Controller. This pin outputs a voltage
14 IMON
proportional to the output current.
This Pin Provides Two Functions: The 3.2V power supply for pin setting
function divided resistors. The other function is fixed 0.8V output reference
15 VREF_PINSET voltage, and the voltage is only used to offset the output voltage of IMON
and IMON_NB pins. Connect a RC circuit from this pin to GND. The
recommended resistor is from 3.9 to 10, and the capacitor is 0.47F.
Current Monitor Output for the VDDNB Controller. This pin outputs a voltage
16 IMON_NB
proportional to the output current.
Controller Power Supply. Connect this pin to 5V and place a decoupling
17 VCC capacitor 2.2F at least. The decoupling capacitor is as close controller as
possible.
System Power Good Input. If PWROK is low, the SVI interface is disabled
and VR returns to BOOT-VID state with initial load-line slope and initial
18 PWROK
offset. If PWROK is high, the SVI interface is running and the DAC decodes
the received serial VID codes to determine the output voltage.
19 SVC Serial VID Clock Input.
20 SVD Serial VID Data Input. This pin is a serial data line.
21 SVT Serial VID Telemetry Output from VR. This pin is a push-pull output.
Processor Memory Interface Power Rail and Serves as the Reference for
22 VDDIO PWROK, SVD, SVC and SVT. This pin is used by the VR to reference the
SVI pins.
This Pin Provides Two Functions: Platform Setting, Platform can use this pin
to set initial offset, BOOT VID, Voltage Reporting Compensation bit0 and
23 TSEN_NB per-phase OCP threshold of VDDNB Controller. The other function is
thermal sense input for VRHOT indicator. Connect the NTC network for
thermal sensing to this pin.
24 ISENN_NB Negative Current Sense Input for VDDNB Controller.
25 ISENP_NB Positive Current Sense Input for VDDNB Controller.
Output Voltage Feedback Input of VDDNB Controller. This pin is the
26 FB_NB
negative input of the error amplifier for the VDDNB controller.
27 COMP_NB Error Amplifier Output Pin of the VDDNB Controller.
28 VIN VIN Input Pin. Connect a low pass filter to this pin.
29 EN Controller Enable Input Pin.
Bootstrap Supply of VDDNB Controller for High Side MOSFET. This pin
30 BOOT_NB
powers high side MOSFET driver.
Upper Gate Driver Output of VDDNB Controller. Connect this pin to the gate
31 UGATE_NB
input of high side MOSFET.
3
RT3662AC
Switch Nodes of High Side Driver for VDDNB Controller. Connect this pin to
32 PHASE_NB high side MOSFET Source together with the low side MOSFET Drain and
the inductor.
Lower Gate Driver Output of VDDNB Controller. Connect this pin to the gate
33 LGATE_NB
input of low side MOSFET.
Driver Power Supply. Connect this pin to GND by the 2.2F ceramic
34 PVCC capacitor at least. The decoupling capacitor is as close controller as
possible.
Lower Gate Driver Output of Phase 1 for VDD Controller. Connect this pin to
35 LGATE1
the gate input of low side MOSFET.
Phase 1 Switch Nodes of High Side Driver for VDD Controller. Connect this
36 PHASE1 pin to high side MOSFET Source together with the low side MOSFET Drain
and the inductor.
Upper Gate Driver Output of Phase 1 for VDD Controller. Connect this pin to
37 UGATE1
the gate input of high side MOSFET.
Bootstrap Supply of VDD Controller for Phase 1 High Side MOSFET. This
38 BOOT1
pin powers high side MOSFET driver.
Lower Gate Driver Output of Phase 2 for VDD Controller. Connect this pin to
39 LGATE2
the gate input of low side MOSFET.
Phase 2 Switch Nodes of High Side Driver for VDD Controller. Connect this
40 PHASE2 pin to high side MOSFET Source together with the low side MOSFET Drain
and the inductor.
Ground. The exposed pad must be soldered to a large PCB and connected
41 (Exposed Pad) GND
to GND for maximum power dissipation.
4
RT3662AC
Function Block Diagram
TSEN_NB
VRHOT_L
PWROK
PGOOD
VSEN
VDDIO
SET1
TSEN
VCC
SVC
SVD
SVT
EN
ISENN_NB
IMONI_NB
IMONI
UVLO
GND
MUX
SVI2 Interface
Loop Control
Configuration Registers
From Control Logic ADC AI_VDD, AI_VDDNB Protection
Control Logic
QR_TH Logic
TONSET
OFFSET
RGND DAC PHOCP_TH
VDDNB Voltage
Reporting Compensation VIN
ERROR
VSET
Soft Start& AMP
Slew Rate Control + Offset
- Cancellation +
FB + - PWM1 BOOTx
PWM
COMP TON UGATEx
CMP PWM2 Driver
GEN PHASEx
1.867m QR_TH LGATEx
ISEN1P + IB1 0.75 x AI_VDD RAMP
ISEN1N - TONSET
+
1.867m
-
ISEN2P + IB2 Current
Balance
- VSEN
IMON IMONI
IB1 Driver
IB2 PVCC
POR
VREF_PINSET OV/UV
From Control Logic
OC
+
To Protection Logic
OCP_SPIKE -
RGND DAC VIN
ERROR
Soft Start& VSET_NB AMP PWM
Slew Rate Control + Offset CMP
Cancellation +
-
+ - PWM BOOT_NB
FB_NB
TON _NB UGATE_NB
COMP_NB Driver
GEN
PHASE_NB
TONSET
1.867m LGATE_NB
RAMP
ISENP_NB + 0.75 x AI_VDDNB
ISENN_NB -
+
VREF_PINSET -
ISENN_NB
IMON_NB IMONI_NB
OV/UV
+ OC_NB
To Protection Logic
OCP_SPIKE_NB -
5
RT3662AC
Operation
The RT3662AC adopts G-NAVPTM (Green Native Error Amplifier
AVP) which is Richtek's proprietary topology derived Error amplifier generates COMP/COMP_NB signal by
from finite DC gain of EA amplifier with current mode the difference between VSET/VSET_NB and
control, making it easy to set the droop to meet all FB/FB_NB.
AMD CPU requirements of AVP (Adaptive Voltage
Positioning). The G-NAVPTM controller is one type of Offset Cancellation
current mode constant on-time control with DC offset This block cancels the output offset voltage from
cancellation. The approach can not only improve DC voltage ripple and current ripple to achieve accurate
offset problem for increasing system accuracy but output voltage.
also provide fast transient response. When current
UVLO
feedback signal reaches COMP signal, it generates
an on-time width to achieve PWM modulation. Detect the VCC pin voltage for under voltage lockout
protection and power on reset operation.
MUX and ADC
Current Balance
The MUX supports the inputs from SET1, TSEN,
TSEN_NB, IMONI, IMONI_NB, ISENN_NB and Each phase current sense signal is sent to the current
VSEN. The ADC converts these analog signals to balance circuit which adjusts the on-time of each
digital codes for reporting or performance adjustment. phase to optimize current sharing.
SVI2 Interface/Configuration Registers/Control PWM CMP

Logic The PWM comparator compares COMP signal
The SVI2 interface uses the SVC, SVD, and SVT pins (COMP/COMP_NB) and current feedback signal to
to communicate with CPU. The configuration generate a signal for TONGEN.
registers save the digital data from ADC output for TONGEN
reporting or performance adjustment. The Control
This block generates an on-time pulse which high
Logic controls the ADC timing and generates the
interval is based on the on-time setting.
digital code of the VID for VDD/VDDNB voltage.
RAMP
Loop Control Protection Logic
The Ramp generator is designed to improve noise
Loop control protection logic detects EN and UVLO
immunity and reduce jitter.
signals to initiate the soft-start function, and the
PGOOD and VRHOT_L will be controlled after the OC/OV/UV
soft-start is finished. When VRHOT indication event Output voltage and output current are sensed for over
occurs, the VRHOT_L pin voltage will be pulled low. current, over voltage and under voltage protection.
DAC
The DAC receives VID codes from the SVI2 control
logic to generate an internal reference voltage
(VSET/VSET_NB) for controller.
Soft-Start and Slew-Rate Control

This block controls the slew rate of the internal
reference voltage when output voltage changes.
6
RT3662AC
Table 1. Serial VID Codes
SVID [7:0] Voltage (V) SVID [7:0] Voltage (V) SVID [7:0] Voltage (V) SVID [7:0] Voltage (V)
0000_0000 1.55000 0010_0111 1.30625 0100_1110 1.06250 0111_0101 0.81875
0000_0001 1.54375 0010_1000 1.30000 0100_1111 1.05625 0111_0110 0.81250
0000_0010 1.53750 0010_1001 1.29375 0101_0000 1.05000 0111_0111 0.80625
0000_0011 1.53125 0010_1010 1.28750 0101_0001 1.04375 0111_1000 0.80000
0000_0100 1.52500 0010_1011 1.28125 0101_0010 1.03750 0111_1001 0.79375
0000_0101 1.51875 0010_1100 1.27500 0101_0011 1.03125 0111_1010 0.78750
0000_0110 1.51250 0010_1101 1.26875 0101_0100 1.02500 0111_1011 0.78125
0000_0111 1.50625 0010_1110 1.26250 0101_0101 1.01875 0111_1100 0.77500
0000_1000 1.50000 0010_1111 1.25625 0101_0110 1.01250 0111_1101 0.76875
0000_1001 1.49375 0011_0000 1.25000 0101_0111 1.00625 0111_1110 0.76250
0000_1010 1.48750 0011_0001 1.24375 0101_1000 1.00000 0111_1111 0.75625
0000_1011 1.48125 0011_0010 1.23750 0101_1001 0.99375 1000_0000 0.75000
0000_1100 1.47500 0011_0011 1.23125 0101_1010 0.98750 1000_0001 0.74375
0000_1101 1.46875 0011_0100 1.22500 0101_1011 0.98125 1000_0010 0.73750
0000_1110 1.46250 0011_0101 1.21875 0101_1100 0.97500 1000_0011 0.73125
0000_1111 1.45625 0011_0110 1.21250 0101_1101 0.96875 1000_0100 0.72500
0001_0000 1.45000 0011_0111 1.20625 0101_1110 0.96250 1000_0101 0.71875
0001_0001 1.44375 0011_1000 1.20000 0101_1111 0.95625 1000_0110 0.71250
0001_0010 1.43750 0011_1001 1.19375 0110_0000 0.95000 1000_0111 0.70625
0001_0011 1.43125 0011_1010 1.18750 0110_0001 0.94375 1000_1000 0.70000
0001_0100 1.42500 0011_1011 1.18125 0110_0010 0.93750 1000_1001 0.69375
0001_0101 1.41875 0011_1100 1.17500 0110_0011 0.93125 1000_1010 0.68750
0001_0110 1.41250 0011_1101 1.16875 0110_0100 0.92500 1000_1011 0.68125
0001_0111 1.40625 0011_1110 1.16250 0110_0101 0.91875 1000_1100 0.67500
0001_1000 1.40000 0011_1111 1.15625 0110_0110 0.91250 1000_1101 0.66875
0001_1001 1.39375 0100_0000 1.15000 0110_0111 0.90625 1000_1110 0.66250
0001_1010 1.38750 0100_0001 1.14375 0110_1000 0.90000 1000_1111 0.65625
0001_1011 1.38125 0100_0010 1.13750 0110_1001 0.89375 1001_0000 0.65000
0001_1100 1.37500 0100_0011 1.13125 0110_1010 0.88750 1001_0001 0.64375
0001_1101 1.36875 0100_0100 1.12500 0110_1011 0.88125 1001_0010 0.63750
0001_1110 1.36250 0100_0101 1.11875 0110_1100 0.87500 1001_0011 0.63125
0001_1111 1.35625 0010_0110 1.11250 0110_1101 0.86875 1001_0100 0.62500
0010_0000 1.35000 0100_0111 1.10625 0110_1110 0.86250 1001_0101 0.61875
0010_0001 1.34375 0100_1000 1.10000 0110_1111 0.85625 1001_0110 0.61250
0010_0010 1.33750 0100_1001 1.09375 0111_0000 0.85000 1001_0111 0.60625
0010_0011 1.33125 0100_1010 1.08750 0111_0001 0.84375 1001_1000 0.60000
0010_0100 1.32500 0100_1011 1.08125 0111_0010 0.83750 1001_1001 0.59375
7
RT3662AC
SVID [7:0] Voltage (V) SVID [7:0] Voltage (V) SVID [7:0] Voltage (V) SVID [7:0] Voltage (V)
0010_0101 1.31875 0100_1100 1.07500 0111_0011 0.83125 1001_1010 0.58750
0010_0110 1.31250 0100_1101 1.06875 0111_0100 0.82500 1001_1011 0.58125
1001_1100 0.57500 1011_0101 * 0.41875 1100_1110 * 0.26250 1110_0111* 0.10625
1001_1101 0.56875 1011_0110 * 0.41250 1100_1111 * 0.25625 1110_1000* 0.10000
1001_1110 0.56250 1011_0111 * 0.40625 1101_0000 * 0.25000 1110_1001* 0.09375
1001_1111 0.55625 1011_1000 * 0.40000 1101_0001 * 0.24375 1110_1010* 0.08750
1010_0000 0.55000 1011_1001 * 0.39375 1101_0010 * 0.23750 1110_1011* 0.08125
1010_0001 0.54375 1011_1010 * 0.38750 1101_0011 * 0.23125 1110_1100* 0.07500
1010_0010 0.53750 1011_1011 * 0.38125 1101_0100 * 0.22500 1110_1101* 0.06875
1010_0011 0.53125 1011_1100 * 0.37500 1101_0101 * 0.21875 1110_1110* 0.06250
1010_0100 0.52500 1011_1101 * 0.36875 1101_0110 * 0.21250 1110_1111* 0.05625
1010_0101 0.51875 1011_1110 * 0.36250 1101_0111 * 0.20625 1111_0000* 0.05000
1010_0110 0.51250 1011_1111 * 0.35625 1101_1000 * 0.20000 1111_0001* 0.04375
1010_0111 0.50625 1100_0000 * 0.35000 1101_1001 * 0.19375 1111_0010* 0.03750
1010_1000 * 0.50000 1100_0001 * 0.34375 1101_1010 * 0.18750 1111_0011* 0.03125
1010_1001 * 0.49375 1100_0010 * 0.33750 1101_1011 * 0.18125 1111_0100* 0.02500
1010_1010 * 0.48750 1100_0011 * 0.33125 1101_1100 * 0.17500 1111_0101* 0.01875
1010_1011 * 0.48125 1100_0100 * 0.32500 1101_1101 * 0.16875 1111_0110* 0.01250
1010_1100 * 0.47500 1100_0101 * 0.31875 1101_1110 * 0.16250 1111_0111* 0.00625
1010_1101 * 0.46875 1100_0110 * 0.31250 1101_1111 * 0.15625 1111_1000* 0.00000
1010_1110 * 0.46250 1100_0111 * 0.30625 1110_0000* 0.15000 1111_1001* OFF
1010_1111 * 0.45625 1100_1000 * 0.30000 1110_0001* 0.14375 1111_1010* OFF
1011_0000 * 0.45000 1100_1001 * 0.29375 1110_0010* 0.13750 1111_1011* OFF
1011_0001 * 0.44375 1100_1010 * 0.28750 1110_0011* 0.13125 1111_1100* OFF
1011_0010 * 0.43750 1100_1011 * 0.28125 1110_0100* 0.12500 1111_1101* OFF
1011_0011 * 0.43125 1100_1100 * 0.27500 1110_0101* 0.11875 1111_1110* OFF
1011_0100 * 0.42500 1100_1101 * 0.26875 1110_0110* 0.11250 1111_1111* OFF
* Indicates TOB is 80mV for this VID code; unconditional VR controller stability required at all VID codes
8
RT3662AC
Table 2. SET1 Pin Setting for VDD Controller AI Gain Ratio and VDDNB Voltage Reporting Offset
 RD 
SET1 Pin Setting Voltage  VSET1_DIV  3.2   VDDNB_RPT_OFS
 RU  RD  AI_VDD
[3:1] bits
Min Typical Max Unit
0 23 47 mV 000
50 74 97 mV 001
100 124 147 mV 010
150 174 197 mV 011
25%
200 224 247 mV 100
250 274 297 mV 101
300 324 347 mV 110
350 374 397 mV 111
400 424 447 mV 000
450 474 497 mV 001
500 524 547 mV 010
551 574 597 mV 011
50%
601 624 648 mV 100
651 674 698 mV 101
701 724 748 mV 110
751 774 798 mV 111
801 824 848 mV 000
851 874 898 mV 001
901 924 948 mV 010
951 974 998 mV 011
100%
1001 1024 1048 mV 100
1051 1074 1098 mV 101
1101 1125 1148 mV 110
1151 1175 1198 mV 111
1201 1225 1248 mV 000
1251 1275 1298 mV 001
1301 1325 1348 mV 010
1351 1375 1398 mV 011
0LL
1401 1425 1448 mV 100
1451 1475 1498 mV 101
1501 1525 1548 mV 110
1552 1575 1598 mV 111
9
RT3662AC
Table 3. SET1 Pin Setting for VDDNB Controller AI Gain Ratio, VDD Controller QR Threshold
 RU  RD 
SET1 Pin Setting Voltage  VSET1_IR  80μ   QR Threshold
 RU  RD  AI_VDDNB
(VDD)
0 49 97 Disable
200 249 297 25% 20mV
300 349 397 25mV
400 449 497 Disable
601 650 698 50% 20mV
701 750 798 25mV
mV
801 850 898 Disable
1001 1050 1098 100% 20mV
1101 1150 1198 25mV
1201 1250 1298 Disable
1401 1450 1498 0LL 20mV
1501 1550 1598 25mV
Table 4. TSEN Pin Setting for the Frequency of VDD/VDDNB Controller, VDD Controller Initial Offset and
PHOCP Setting Ratio
 RD  VDD PHOCP
TSEN Pin Setting Voltage  VTSEN_DIV  3.2   Frequency Initial Offset Setting Ratio
 RU  RD 
(VDD/VDDNB) (VDD) (Percentage of
Min Typical Max Unit OCP_SPIKE)
0 23 47 mV 150%
25mV
50 74 97 mV 200%
200 224 247 mV 150%
0mV
250 274 297 mV 200%
300kHz
400 424 447 mV 150%
25mV
450 474 497 mV 200%
601 624 648 mV 150%
50mV
651 674 698 mV 200%
801 824 848 mV 150%
25mV
851 874 898 mV 200%
1001 1024 1048 mV 150%
0mV
1051 1074 1098 mV 200%
400kHz
1201 1225 1248 mV 150%
25mV
1251 1275 1298 mV 200%
1401 1425 1448 mV 150%
50mV
1451 1475 1498 mV 200%
PHOCP_TH = OCP_SPIKE × (PHOCP Setting Ratio) / M (M : Phase Number)
10
RT3662AC
Table 5. TSEN_NB Pin Setting for VDDNB Controller Initial Offset, Voltage Reporting Offset and PHOCP
Setting Ratio
TSEN_NB Pin Setting Voltage

VDDNB PHOCP
 RD  Initial Offset VDDNB_RPT Setting Ratio
 VTSEN_NB_DIV  3.2  
 RU  RD  (VDDNB) _OFS [0] (Percentage of
OCP_SPIKE_NB)
0 23 47 mV 150%
0
50 74 97 mV 25mV 200%
100 124 147 mV (PS0) 150%
1
150 174 197 mV 200%
200 224 247 mV 150%
0
250 274 297 mV 0mV 200%
300 324 347 mV (PS0) 150%
1
350 374 397 mV 200%
400 424 447 mV 150%
0
450 474 497 mV 25mV 200%
500 524 547 mV (PS0) 150%
1
551 574 597 mV 200%
601 624 648 mV 150%
0
651 674 698 mV 50mV 200%
701 724 748 mV (PS0) 150%
1
751 774 798 mV 200%
801 824 848 mV 150%
0
851 874 898 mV Fixed 1.5V 200%
901 924 948 mV (PS2) 150%
1
951 974 998 mV 200%
1001 1024 1048 mV 150%
0
1051 1074 1098 mV Fixed 1.35V 200%
1101 1125 1148 mV (PS2) 150%
1
1151 1175 1198 mV 200%
1201 1225 1248 mV 150%
0
1251 1275 1298 mV Fixed 1.25V 200%
1301 1325 1348 mV (PS2) 150%
1
1351 1375 1398 mV 200%
1401 1425 1448 mV 150%
0
1451 1475 1498 mV 0mV 200%
1501 1525 1548 mV (PS2) 150%
1
1552 1575 1598 mV 200%
11
RT3662AC
Table 6. VDDNB Voltage Reporting Offset Table
VDDNB Voltage Reporting Offset
VDDNB_RPT_OFS [3:0]
(VDDNB_RPT_OFS) (Bits)
0000 DIMON_NB x 1/128
0001 DIMON_NB x 2/128
0010 DIMON_NB x 3/128
0011 DIMON_NB x 4/128
0100 DIMON_NB x 5/128
0101 DIMON_NB x 6/128
0110 DIMON_NB x 7/128
0111 DIMON_NB x 8/128
1000 DIMON_NB x 9/128
1001 DIMON_NB x 10/128
1010 DIMON_NB x 11/128
1011 DIMON_NB x 12/128
1100 DIMON_NB x 13/128
1101 DIMON_NB x 14/128
1110 DIMON_NB x 15/128
1111 DIMON_NB x 16/128
VIMON_NB  0.8
DIMON_NB   255 (Bits)
0.8
DIMON_NB : VDDNB Current Reporting Digital Code
12
RT3662AC
Absolute Maximum Ratings (Note 1)
 VCC to GND ------------------------------------------------------------------------------------------------- 0.3V to 6.5V
 PVCC to GND ----------------------------------------------------------------------------------------------- 0.3V to 6V
 RGND to GND ----------------------------------------------------------------------------------------------- 0.3V to 0.3V
 BOOTx to PHASEx ----------------------------------------------------------------------------------------- 0.3V to 6V
 PHASEx to GND
DC -------------------------------------------------------------------------------------------------------------- 0.3V to 32V
< 20ns --------------------------------------------------------------------------------------------------------- 8V to 38V
 UGATEx to PHASEx
DC -------------------------------------------------------------------------------------------------------------- 0.3V to 6V
< 20ns --------------------------------------------------------------------------------------------------------- 5V to 7.5V
 LGATEx to GND
DC -------------------------------------------------------------------------------------------------------------- 0.3V to 6V
<20ns ---------------------------------------------------------------------------------------------------------- 2.5V to 7.5V
 Other Pins ---------------------------------------------------------------------------------------------------- 0.3V to (VCC + 0.3V)
 Power Dissipation, PD @ TA = 25C
WQFN-40L 5x5 ---------------------------------------------------------------------------------------------- 3.63W
 Package Thermal Resistance (Note 2)
WQFN-40L 5x5, JA ---------------------------------------------------------------------------------------- 27.5C/W
WQFN-40L 5x5, JC---------------------------------------------------------------------------------------- 6C/W
 Lead Temperature (Soldering, 10 sec.)---------------------------------------------------------------- 260C
 Junction Temperature -------------------------------------------------------------------------------------- 150C
 Storage Temperature Range ----------------------------------------------------------------------------- 65C to 150C
 ESD Susceptibility (Note 3)
HBM (Human Body Model) ------------------------------------------------------------------------------- 2kV
Recommended Operating Conditions (Note 4)

 Supply Voltage, VCC--------------------------------------------------------------------------------------- 4.5V to 5.5V
 Supply Voltage, PVCC------------------------------------------------------------------------------------- 4.5V to 5.5V
 Supply Voltage, VIN ---------------------------------------------------------------------------------------- 4.5V to 26V
 Ambient Temperature Range ---------------------------------------------------------------------------- 40C to 85C
 Junction Temperature Range ---------------------------------------------------------------------------- 40C to 125C
Electrical Characteristics
(VCC = 5V, TA = 25C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Input Power Supply
Supply Voltage VCC 4.5 5 5.5 V
Supply Current IVCC EN = 3V, Not Switching -- 9 15 mA
13
RT3662AC
Shutdown Current ISHDN EN = 0V -- 5 -- A
PVCC Supply Voltage VPVCC 4.5 5 5.5 V
PVCC Supply Current IPVCC VBOOTX = 5V, Not Switching -- 150 -- A
Driver Power On Reset (Driver POR)
VPOR_r PVCC POR Rising -- 3.85 4.1 V
Driver POR Threshold
VPOR_f PVCC POR Falling 3.4 3.65 -- V
Driver POR Hysteresis VPOR_Hys 100 200 350 mV
Reference and DAC
Reference Voltage Output VREF 0.795 0.8 0.805 V
VDAC = 1.0000 to 1.5500
0.5 0 0.5 %SVID
(No Load, CCM Mode)
VDAC = 0.8000 to 1.0000 5 0 5 mV
DC Accuracy VFB
VDAC = 0.3000 to 0.8000 8 0 8 mV
VDAC = 0.2500 to 0.3000 80 0 80 mV
Reference and DAC
RGND Current IRGND EN = 3V, Not switching 150 200 250 A
Slew Rate
Dynamic VID Slew Rate SR SetVID Fast 7.5 10 15 mV/s
Error Amplifier
Input Offset VEAOFS 4 -- 4 mV
DC Gain ADC RL = 47k 70 80 -- dB
Gain-Bandwidth Product GBW CLOAD = 5pF -- 5 - MHz
Output Voltage Range VCOMP RLOAD = 47k 0.3 -- 3.6 V
IEA,SRC /
EA Source/Sink Current -- 5 -- mA
IEA,SNK
Current Sense Amplifier
Input Offset Voltage VOSCS 0.4 -- 0.4 mV
Impedance at Neg. Input RISENxN 1 -- -- M
Impedance at Pos. Input RISENxP 1 -- -- M
VDAC = 1.1V,
Input range VISEN_IN 40 -- 40 mV
(ISENxP  ISENxN)
Current Sense Gain Error AISEN_Err VDAC = 1.1V 2 -- 2 %
EN and Logic Inputs
VIH_EN 2 -- --
EN Threshold V
VIL_EN -- -- 0.8
Leakage Current of EN ILEK_EN 1 -- 1 A
VIH_SVI Respect to VDDIO 70 -- 100
SVC, SVD, PWROK %
VIH_SVI Respect to VDDIO 0 -- 35
Hysteresis of SVC, SVD,
VHYS_SVI Respect to VDDIO 10 -- -- %
PWROK
14
RT3662AC
SVI2 Bus
SVC Frequency f SVC (Note 5) 0.1 -- 30 MHz
Thermal Management
VRHOT Indicator Threshold VTH_VRHOT 2.16 2.2 2.24 V
VRHOT Indicator Hysteresis VHYS_VRHOT 50 75 100 mV
TON Setting
VIN = 19V,VDAC = 1V,
On-Time Setting TON [PSI0_L:PSI1_L] = 11 150 175 200 ns
(Note 6)
Minimum Off Time TOFF VDAC = 1V -- 250 400 ns
ITSEN
TSEN Source Current ITSEN VCC = 5V -- 80 -- A
Protection
Under Voltage Lockout
VUVLO VCC Falling edge 3.9 4.1 4.3 V
Threshold
Under Voltage Lockout
VUVLO -- 200 -- mV
Hysteresis
Over Voltage Protection
VOVP 1.8 1.85 1.9 V
Threshold
VSEN Rising above
Delay of OVP TOVP 0.3 1 3 s
Threshold
Under Voltage Protection
VUVP Respect to VID Voltage 600 500 400 mV
Threshold
VSEN Falling below
Delay of UVP TUVP 0.5 3 7 s
Threshold
DCR = 1.1m, KAG = 0.6,
OCP_SPIKE Threshold IOCP_SPIKE 73.15 77 80.85 A
RIMON = 8.433k
TOCPSPIKE
OCP_SPIKE Trigger Delay 8 14 20 s
_DLY
Delay of Per Phase OCP TPHOCP 0.1 0.5 1 s
VRHOT_L and PGOOD
Output Low Voltage at
VVRHOT_L IVRHOT_L = 4mA 0 -- 0.2 V
VRHOT_L
VRHOT_L Assertion Time TVRHOTL 2 -- -- s
Output Low Voltage at PGOOD VPGOOD IPGOOD = 4mA 0 -- 0.2 V
PGOOD Threshold VTH_PGOOD Respect to BOOT VID -- 300 -- mV
PGOOD Delay Time TPGOOD BOOT VID to PGOOD High 60 110 160 s
Current Report
%IDD_
Maximum Reported Current
-- 100 -- SPIKE
(FFh = OCP_SPIKE)
_OCP
%IDD_
Minimum Reported Current
-- 0 -- SPIKE
(00h)
_OCP
IDDSPIKE Current Accuracy -- -- 3 %
15
RT3662AC
Voltage Report
Maximum Reported Voltage
-- 3.15 -- V
(0_00h)
Minimum Reported Voltage
-- 0 -- V
(1_F8h)
Voltage Accuracy 2 -- 2 LSB
Switching Time
UGATEx Rise Time tUGATEr 3nF Load -- 8 -- ns
UGATEx Fall Time tUGATEf 3nF Load -- 8 -- ns
LGATEx Rise Time tLGATEr 3nF Load -- 8 -- ns
LGATEx Fall Time tLGATEf 3nF Load -- 4 -- ns
UGATEx Turn-On Propagation
TUGATEpdh Output Unloaded -- 20 -- ns
Delay
LGATEx Turn-On Propagation
TLGATEpdh Output Unloaded -- 20 -- ns
Delay
Output
UGATEx Driver Source
RUGATEsr 100mA Source Current -- 1 -- 
Resistance
UGATEx Driver Source Current IUGATEsr VUGATE  VPHASE = 2.5V -- 2 -- A
UGATEx Driver Sink
RUGATEsk 100mA Sink Current -- 1 -- 
Resistance
UGATEx Driver Sink Current IUGATEsk VUGATE  VPHASE = 2.5V -- 2 -- A
LGATEx Driver Source
RLGATEsr 100mA Source Current -- 1 -- 
Resistance
LGATEx Driver Source Current ILGATEsr VLGATE = 2.5V -- 2 -- A
LGATEx Driver Sink Resistance RLGATEsk 100mA Sink Current -- 0.5 -- 
LGATEx Driver Sink Current ILGATEsk VLGATE = 2.5V -- 4 -- A
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. JA is measured at TA = 25C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. JC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Min. SVC frequency defined in electrical spec. is related with different application. As min. SVC < 1MHz, VR can’t
support telemetry reporting function. As min. SVC < 400kHz, VR can’t support telemetry reporting function and VOTF
complete function.
Note 6. TON[PSI0_L:PSI1_L=00,01,10] = 0.8 * TON[PSI0_L:PSI1_L=11]
16
RT3662AC
Typical Application Circuit
4.7 RT3662AC
28 8
VIN VIN VSEN
0.1μF 39pF 270pF
VVDD_SENSE
2.2 22
VDDIO VDDIO
VREF 1μF 5
COMP
41.2k 10k Reserved
4.7
17 FB 6 VSS_SENSE
5V VCC
2.2μF
0 RGND 4
37.4k 68k 324k 34 VIN
5V PVCC
2.2μF 10 10
38 2.2 0.1μF
300 4.02k 1.8k BOOT1 10μF x 2
13
SET1 UGATE1 37 VVDD
0.36μH/1.1m 
187k 12 36
TSEN PHASE1
35 0.47μF
RNTC LGATE1 1 1.5k LOAD
100k/  = 4485
3.3nF
2.26k POSCAP : 470μF/4.5m  x 3
187k 23 TSEN_NB ISEN1P 9
MLCC : 22μF x 14
RNTC ISEN1N 10
14k 33k 24k VIN 0.1μF
100k/  = 4485
0.1μF
2 2.2
180 300 487 BOOT2 10μF x 2
UGATE2 1
0.36μH/1.1m 
PHASE2 40
VREF 15
VREF_PINSET 39 0.47μF
LGATE2 1 1.5k
8.699k
3.9
3.3nF
0.47μF 15.8k RNTC 390 2.26k
14 ISEN2P 7
IMON 0.1μF
100k/  = 4485
11.755k
RNTC 56pF 270pF
12.78k 4.75k 16 VVDDNB_SENSE
IMON_NB
100k/  = 4485 27
COMP_NB
VDDIO 59k 10k
3.3V Reserved VSS_SENSE
FB_NB 26
4.7k 4.7k 10k VIN

11 0.1μF 10 10
VRHOT_L 30 2.2
BOOT_NB 10μF x 2
18
PWROK UGATE_NB 31 VVDDNB
3 0.36μH/1.1m 
32
PGOOD PHASE_NB
19 33 0.47μF
SVC LGATE_NB 1 768 LOAD
To CPU 20 SVD
3.3nF
21 SVT
POSCAP : 470μF/4.5m 
ISENP_NB 25
29 EN MLCC : 22μF x 6
Enable Reserved
41 (Exposed Pad)
GND ISENN_NB 24
0.1μF
Timing Diagram
LGATEx
1.5V 1.5V
1.5V 1.5V
UGATEx
tUGATEpdh tLGATEpdh
17
RT3662AC
Typical Operating Characteristics
CORE VR Power On from EN CORE VR Power Off from EN
Boot VID = 0.8V VDD Boot VID = 0.8V

(500mV/Div)
VDD
(500mV/Div)
EN
EN (3V/Div)
(3V/Div)
PGOOD PGOOD
(3V/Div) (3V/Div)
UGATE1
UGATE (20V/Div)
(20V/Div)
Time (500μs/Div) Time (200μs/Div)
CORE VR Thermal Monitoring CORE VR OCP_SPIKE
ILoad = 60A to 90A
ILoad
(16A/Div)
TSEN PGOOD
(1V/Div) (3V/Div)
LGATE
(10V/Div)
VRHOT_L UGATE
(1V/Div) (30V/Div)
Time (10ms/Div) Time (10μs/Div)
CORE VR OVP CORE VR UVP
VID = 1.1V VDD VID = 1.1V

(500mV/Div)
VDD
(800mV/Div)
PGOOD
(3V/Div) PGOOD
(3V/Div)
UGATE UGATE
(30V/Div) (30V/Div)
LGATE LGATE
(10V/Div) (10V/Div)
18
RT3662AC
CORE VR Dynamic VID Up CORE VR Dynamic VID Up
VDD
VDD
(400mV/Div)
SVD
SVD (2V/Div)
(2V/Div)
SVT
SVT (2V/Div)
(2V/Div)
VDD
VID = 0.4V to 1V, ILoad = 3.9A (200mV/Div) VID = 1V to 1.06875V, ILoad = 19.5A
CORE VR Dynamic VID Up CORE VR Dynamic VID Up
VDD VDD
SVD SVD
(2V/Div) (2V/Div)
SVT SVT
(2V/Div) (2V/Div)
VDD VDD
(200mV/Div) VID = 1V to 1.1V, ILoad = 19.5A (200mV/Div) VID = 1V to 1.2V, ILoad = 19.5A
CORE VR Dynamic VID Up CORE VR Load Transient

VDD
(30mV/Div)
ILoad
VDD (20A/Div)
SVD
(2V/Div)
VDD
SVT
(2V/Div)
VDD
(300mV/Div) VID = 1V to 1.4V, ILoad = 19.5A fLoad = 10kHz, ILoad = 20A to 55A
19
RT3662AC
CORE VR Load Transient NB VR Thermal Monitoring
ILoad
(20A/Div)
TSEN_NB
(1V/Div)
VDD
(30mV/Div)
VRHOT_L
(1V/Div)
fLoad = 10kHz, ILoad = 55A to 20A
Time (5μs/Div) Time (10ms/Div)
NB VR Power On from EN NB VR Power Off from EN
Boot VID = 0.8V Boot VID = 0.8V
VDDNB VDDNB
(500mV/Div) (500mV/Div)
EN
(3V/Div)
EN
(3V/Div)
PGOOD
PGOOD (3V/Div)
(3V/Div)
UGATE_NB
UGATE_NB
(20V/Div)
(20V/Div)
NB VR OCP_SPIKE NB VR OVP
ILoad = 15A to 40A VID = 1.1V
ILoad
(20A/Div)
VDDNB
(800mV/Div)
PGOOD PGOOD
(3V/Div) (3V/Div)
UGATE_NB UGATE_NB
(30V/Div) (30V/Div)
LGATE_NB LGATE_NB
(10V/Div) (10V/Div)
20
RT3662AC
NB VR UVP NB VR Dynamic VID Up
VID = 1.1V
VDDNB VDDNB
PGOOD SVD
(3V/Div) (2V/Div)
UGATE_NB
(30V/Div)
SVT
LGATE_NB (2V/Div)
(10V/Div) VID = 0.4V to 1V, ILoad = 1.2A
NB VR Dynamic VID Up NB VR Dynamic VID Up
VDDNB VDDNB
SVD
SVD
(2V/Div)
(2V/Div)
SVT
SVT
(2V/Div)
(2V/Div)
VDDNB
VDDNB (200mV/Div)
(200mV/Div) VID = 1V to 1.06875V, ILoad = 6A VID = 1V to 1.1V, ILoad = 6A
NB VR Dynamic VID Up NB VR Dynamic VID Up
VDDNB
SVD VDDNB
(2V/Div)
SVD
(2V/Div)
SVT
(2V/Div) SVT
(2V/Div)
VDDNB
(200mV/Div) VDDNB
VID = 1V to 1.2V, ILoad = 6A VID = 1V to 1.4V, ILoad = 6A
(300mV/Div)
21
RT3662AC
NB VR Load Transient NB VR Load Transient
VDDNB VDDNB
ILoad ILoad
(10A/Div) (10A/Div)
fLoad = 10kHz, ILoad = 7A to 17A fLoad = 10kHz, ILoad = 17A to 7A
22
RT3662AC
Application Information
Power Ready (POR) Detection Boot VID
During start-up, the RT3662AC will detect the voltage When EN goes high, both VDD and VDDNB output
at the voltage input pins: VCC, PVCC and EN. When begin to soft-start to the Boot VID in CCM. Table 7
VCC > 4.3V and PVCC > 3.85V, the IC will recognize shows the Boot VID setting. The Boot VID is
the power state of system to be ready (POR = high) determined by the SVC and SVD input states at EN
and wait for enable command at the EN pin. After POR rising edge and it is in the internal register. The digital
= high and VEN > 2V, the IC will enter start-up soft-start circuit ramps up the reference voltage at a
sequence for both VDD and VDDNB rail. If the voltage controlled slew rate to reduce inrush current during
of VCC and EN pin drop below low threshold, the IC will start-up. When all the output voltages are above power
enter power down sequence and all the functions will good threshold (300mV below Boot VID) at the end of
be disabled. Normally, connecting system power to the soft-start, the controller asserts power good (PGOOD)
EN pin is recommended. The SVID will be ready in 2ms after a time delay.
(max) after the chip has been enabled. All the Table 7. 2-Bit Boot VID Code
protection latches (OVP, OCP, UVP) will be cleared
Initial Startup VID (Boot VID)
only after POR = low. The condition of VEN = low will
SVC SVD VDD/VDDNB Output Voltage (V)
not clear these latches.
0 0 1.1
VCC + CMP 0 1 1.0
4.3V -
CMP 1 0 0.9
PVCC + POR
3.85V - 1 1 0.8
EN + CMP Chip EN
2V - Start-Up Sequence
After EN goes high, the RT3662AC starts up and
Figure 1. Power Ready (POR) Detection
operates according to the initial settings. Figure 2
shows the simplified sequence timing diagram. The
detailed operation is described in the following.
23
RT3662AC
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
VIN
VDDIO
PVCC, VCC
SVID
SVID
Send
Send
SVC Byte
Byte
SVD
VOTF VOTF
Complete Complete
SVT
EN
PWROK
Boot VID Boot VID
CCM VID VID
CCM
CCM CCM CCM CCM CCM
VDD/
VDDNB
PGOOD
Figure 2. Simplified Sequence Timing Diagram

Description of Figure 2 :
T0: When the VIN power is ready, the RT3662AC will and send a VOTF Complete if the VID is greater than
wait for VCC and PVCC POR. BOOT VID and reaches target VID.
T1: VDDIO power is ready, and the BOOT VID can be T7: The PWROK pin goes low and the SVI2 interface
set by SVC pin and SVD pin, and latched at EN rising stops running. All output voltages go back to the Boot
edge. SVT is driven high by the RT3662AC. VID in CCM.
T2: The enable signal goes high and all output voltages T8: The PWROK pin goes high again and the SVI2
ramp up to the Boot VID in CCM. The soft-start slew interface starts running. The RT3662AC waits for SVID
rate is 2.5mV/s. command from processor.
T3: All output voltages are within the regulation limits T9: A valid SVID command transaction occurs between
and the PGOOD signal goes high. the processor and the RT3662AC.
T4: The PWROK pin goes high and the SVI2 interface T10: The action is same with T6. The RT3662AC starts
starts running. The RT3662AC waits for SVID VID on-the-Fly transition and send a VOTF Complete if
command from processor. the VID up and reaches target VID.
T5: A valid SVID command transaction occurs between T11: The enable signal goes low and all output
the processor and the RT3662AC. voltages enter soft-shutdown mode. The soft-shutdown
T6: The RT3662AC starts VOTF (VID on-the-Fly) slew rate is 2.5mV/s.
transition according to the received SVID command
24
RT3662AC
Power-Down Sequence SVI2 Wire Protocol
If the voltage at the EN pin falls below the enable falling The RT3662AC complies with AMD's Voltage
threshold, the controller is disabled. The voltage at the Regulator Specification, which defines the Serial VID
PGOOD pin will immediately go low when EN pin signal Interface 2.0 (SVI2) protocol. With SVI2 protocol, the
goes low, and the controller executes soft-shutdown processor directly controls the reference voltage level
operation. The internal digital circuit ramps down the of each individual controller channel and determines
reference voltage at the same slew rate as that of in which controller operates in power saving mode. The
soft-start, making VDD and VDDNB output voltages SVI2 interface is a three-wire bus that connects a
gradually decrease in CCM. The Boot VID information single master to one or above slaves. The master
stored in the internal register is cleared at POR. This initiates and terminates SVI2 transactions and drives
event forces the RT3662AC to check the SVC and SVD the clock, SVC, and the data, SVD, during a transaction.
inputs for a new boot VID when the EN voltage goes The slave drives the telemetry, SVT during a
high again. transaction. The AMD processor is always the master.
The voltage regulator controller (RT3662AC) is always
PGOOD
the slave. The RT3662AC receives the SVID code and
The PGOOD is open-drain logic output. It provides the acts accordingly. The SVI protocol supports 20MHz
power good signal when VDD and VDDNB output high speed mode I2C, which is based on SVD data
voltage are within the regulation limits and no packet. Table 8 shows the SVD data packet. A SVD
protection is triggered. The pin is typically tied to 3.3V packet consists of a “Start” signal, three data bytes
or 5V power source through a pull-high resistor. During after each byte, and a “Stop” signal. The 8-bit serial
shutdown state (EN = low) and the soft-start period, the VID codes are listed in Table1. After the RT3662AC
PGOOD voltage is pulled low. After a successful has received the stop sequence, it decodes the
soft-start and VDD and VDDNB output voltages are received serial VID code and executes the command.
within the regulation limits, the PGOOD is released The controller has the ability to sample and report
high. voltage and current for the VDD and VDDNB domains.
The voltage at the PGOOD pin will be pulled low when any The controller reports this telemetry serially over the
of the following events occurs : over-voltage protection, SVT wire which is clocked by the processor driven SVC.
under-voltage protection, over-current protection, and logic A bit TFN at SVD packet along with the VDD and
low EN voltage. If one rail triggers protection, the PGOOD VDDNB domain selector bits are used by the processor
will be pull low. to change the telemetry functionality. The telemetry bit
definition is listed in Figure 3. The detailed SVI2
specification is outlined in the AMD Voltage Regulator
and Voltage Regulator Module (VRM) and Serial VID
Interface 2.0 (SVI2) Specification.
Table 8. SVD Data Packet

Bit Time Description
1:5 Always 11000b
VDD domain selector bit, if set then the following two data bytes contain the VID, the PSI state,
6
and the load-line slope trim and offset trim state for VDD.
VDDNB domain selector bit, if set then the following two data bytes contain the VID, the PSI
7
state, and the load-line slope trim and offset trim state for VDDNB.
8 Always 0b
10 PSI0_L
11 : 17 VID Code bits [7:1]
19 VID Code bit [0]
25
RT3662AC
Bit Time Description
20 PSI1_L
21 TFN (Telemetry Functionality)
22 : 24 Load Line Slope Trim [2:0]
25 : 26 Offset Trim [1:0]
Voltage and Current VDDNB Voltage Bit in Voltage Only Mode;

VDD Voltage Bits
Mode Selection Current Bit in Voltage and Current Mode
Bit Time…… START STOP

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
SVC
SVT
Figure 3. Telemetry Bit Definition
PWROK and SVI2 Operation VID on-the-Fly Transition

The PWROK pin is an input pin, which is connected to After the RT3662AC has received a valid SVID code, it
the global power good signal from the platform. Logic executes the VID on-the-Fly transition by stepping
high at this pin enables the SVI2 interface, allowing up/down the reference voltage of the required
data transaction between processor and the controller channel in a controlled slew rate, hence
RT3662AC. Once the RT3662AC receives a valid SVID allowing the output voltage to ramp up/down to target
code, it decodes the information from processor to VID.
determine which output plane is going to move to the During the VID on-the-Fly transition, the RT3662AC will
target VID. The internal DAC then steps the reference force CCM operation in high performance mode. If the
voltage in a controlled slew rate, making the output controller channel operates in the power-saving mode
voltage shift to the required new VID. Depending on the prior to the VID on-the-Fly transition, it will change to
SVID code, more than one controller channel can be high performance mode and implement CCM operation
targeted simultaneously in the VID transition. For when the controller implement VID up, and then remain
example, VDD and VDDNB voltages can ramp in high performance mode; if the controller implement
up/down at the same time. VID down in power-saving mode, it will decay down
If the PWROK input goes low during normal operation, and keep in power-saving mode. The voltage at the
the SVI2 protocol stops running. The RT3662AC PGOOD pin will keep high during the VID on-the-Fly
immediately drives SVT high and modifies all output transition. The RT3662AC send a VOTF complete only
voltages back to the Boot VID, which is stored in the at the end of VID up transition. In the event of receiving
internal register right after the controller is enabled. The a VID off code, the RT3662AC steps the reference
controller does not read SVD and SVC inputs after the voltage of required controller channel down to zero,
loss of PWROK. If the PWROK input goes high again, hence making the required output voltage decrease to
the SVI2 protocol resumes running. The RT3662AC zero, and the voltage at the PGOOD pin will remain
then waits to decode the SVID command from high since the VID code is valid.
processor for a new VID and acts as previously
Power State Transition
described. The SVI2 protocol is only runs when the
PWROK input goes high after the voltage at the EN pin The RT3662AC supports power state transition
goes high. function in VDD and VDDNB VR for the PSI[x]_L
command from AMD processor. The PSI[x]_L bit in the
26
RT3662AC
SVI2 protocol controls the operating mode of the VSS_SENSE. For VDD controller, connect FB to
RT3662AC controller channels. The default operation VDD_SENSE with a resistor to build the negative input
mode of VDD and VDDNB VR is full-phase CCM. path of the error amplifier. Connect FB_NB to
When the VDD VR is in N phase configuration and VDDNB_SENSE with a resistor using the same way in
receives PSI0_L = 0 and PSI1_L = 0 or 1, the VDD VR VDD controller. Connect VSS_SENSE to RGND using
will entry 1-phase diode emulation mode. When the separate trace as shown in Figure 4. The precision
VDD VR receives PSI0_L = 1 and PSI1_L = 0, the VDD reference voltages refer to RGND for accurate remote
VR remains 1-phase diode emulation mode. In reverse, sensing.
the VDD VR goes back to N phase operation in CCM Processor
upon receiving PSI0_L = 1 and PSI1_L = 1, see Table VDD_SENSE VDDNB_SENSE
9. When the VDDNB VR receives PSI0_L = 0 and FB FB_NB
VDD VDDNB
PSI1_L = 0 or 1, it enters 1-phase diode emulation Controller Controller
RGND RGND
mode. If the VDDNB VR receives PSI0_L = 1 and VSS_SENSE
PSI1_L = 0, it remains 1-phase diode emulation mode.
The VDDNB VR will go back to 1-phase CCM operation Figure 4. Differential Remote Voltage Sense
after receiving PSI0_L = 1 and PSI1_L = 1, see Table Connection
10.
SET1 Pin Setting
Table 9. VDD VR Power State
The RT3662AC provides the SET1 pin for platform users
Full Phase
PSI0_L : PSI1_L Mode to set the VDD and VDDNB controller current gain ratio
Number
11 2 phase CCM (AI_VDD, AI_VDDNB), VDD controller QR threshold
(QR_TH) and VDDNB voltage reporting offset bit[1:3]
10
2 (VDDNB_RPT_OFS). Platform designers should use
01 1 phase DEM
resistive voltage divider on the pin, refer to Figure 5. The
00
voltage (VREF) at VREF_PINSET pin will be pulled up to
11 1 phase CCM
3.2V for SET1 pin setting after power ready (POR), and
10
1 then the voltage will change and fix to 0.8V with a delay
01 1 phase DEM time for normal operation.
00
The divided voltage at the SET1 pin as below :
Table 10. VDDNB VR Power State
RD
Full Phase VSET1_DIV  3.2  (1)
PSI0_L : PSI1_L Mode RU  RD
Number
11 1 phase CCM The ADC monitors and decodes the voltage at this pin
10 only once after power up. After ADC decoding (only
1
01 1 phase DEM once), a 80A current (when VCC = 5V) will be
00 generated at the SET1 pin for pin setting. That is the
voltage at SET1 pin described as below :
Differential Remote Sense Setting
R  RD
The VDD and VDDNB controllers have differential, VSET1_IR  80  U (2)
RU  RD
remote-sense inputs to eliminate the effects of voltage
drops along the PC board traces, processor internal From equation (1) and (2) and Table 2 and 3, platform
power routes and socket contacts. The processor users can set the above described pin setting
contains on-die sense pins, including of VDD_SENSE, functions.
VDDNB_SENSE and VSS_SENSE. Connect RGND to
27
RT3662AC
Thermal Indicator
VDDNB_RPT AI_VDD,
_COMP[1:3] AI_VDDNB Refer to Figure 6, the RT3662AC provides the thermal
80µA indicator function. The VRHOT_L pin is an open-drain
QR_TH (VCC = 5V)
output which is used for VR thermal indicator. When
VREF
ADC the sensed voltage at TSEN or TSEN_NB pin is less
VSET1_DIV
RU
than 2.2V, the VRHOT_L signal will be pulled low to
SET1 SET1 notify CPU that the temperature is over the VRHOT
Register
RD temperature threshold.
VSET1_IR
After TSEN and TSEN_NB pin setting, a 80A current
Figure 5. SET1 Pin Setting (when VCC = 5V) will be generated at the TSEN and
TSEN_NB pin for thermal indicator function. And the
TSEN and TSEN_NB Pin Setting voltage at TSEN and TSEN_NB pin as below :
The RT3662AC provides the TSEN and TSEN_NB pins  R  R   Rp1  Rp2    Rp2 
VTSEN  80 A   1 NTC       VREF    (5)
for platform users to set the pin setting functions,  R1  RNTC   Rp1  Rp2    Rp1  Rp2 
including the VDD and VDDNB controller switching
 R  R   Rp3  Rp4    Rp4 
frequency (FSW ), Initial offset, Per-phase over current VTSEN_NB  80 A   2 NTC       VREF    (6)
 R2  RNTC   Rp3  Rp4    Rp3  Rp4 
protection (PHOCP) and VDDNB voltage reporting
offset bit[0] (VDDNB_RPT_OFS). Platform designers Due to the VREF reference voltage cause the thermal
should use resistive voltage divider on the pins, refer to compensation become complex. In this way, the
Figure 6. The voltage (VREF) at VREF_PINSET pin will sensed voltage related VREF will be eliminated in ADC
be pulled up to 3.2V for TSEN and TSEN_NB pin block. The actual sensed voltage at TSEN and
setting after power ready (POR), and then the voltage TSEN_NB pin described as below:
will change and fix to 0.8V with a delay time for normal
operation.  R  R   Rp1  Rp2  
VTSEN_ADC  80 A   1 NTC      (7)

The divided voltage at the TSEN and TSEN_NB pin  R1  RNTC   Rp1  Rp2  
described as below:
 R  R   Rp3  Rp4 
Rp2 (3) VTSEN_NB_ADC  80 A   2 NTC      (8)
VTSEN_DIV  3.2   R2  RNTC   Rp3  Rp4  
Rp1  Rp2
VDDIO
Rp4
VTSEN_NB_DIV  3.2  (4) VDDNB_RPT Initial
Rp3  Rp4 _COMP[0] Offset VRHOT_L
PROCHOT_L
PHOCP
FSW Thermal 80µA
The ADC monitors and decodes the voltage at this pin Monitor (VCC = 5V)
only once after power up. After ADC decoding (only ADC VREF
2.2V RNTC
once), a 80A current (when VCC = 5V) will be Rp1
VTSEN
TSEN
generated at the TSEN and TSEN_NB pin for thermal Register
R1
VTSEN_DIV Rp2
indicator and protection functions. 80µA
(VCC = 5V)
From equation (3) and (4) and Table 4 and 5, platform VTSEN_NB
VREF
users can set the above described pin setting RNTC
VTSEN_NB_DIV
Rp3
functions. TSEN_NB
R2
Rp4
Figure 6. TSEN and TSEN_NB Circuit
28
RT3662AC
VDD Controller Current Signal Sensing
Refer to Figure 7, for different RSENSE resistor, the
Active Phase Determination
current sense method can classify as two types. The
The number of active phases is determined by the
method1 only use RX1 for lower RSENSE application,
internal circuitry that monitors the ISEN2P voltage
and the method2 use RX1 and RX2 to divide the current
during start-up. Normally, the VDD controller operates
signal for higher RSENSE application. Richtek also
as a 2-phase PWM controller. Pulling ISEN2P to VCC
provide Excel based design tool to let user choose the
programs a 1-phase operation. At EN rising edge, VDD
appropriate components quickly.
controller detects whether the voltage of ISEN2P is
The current sense topology of the VDD controller is
higher than “VCC  0.5V” to decide how many phases
continuous inductor current sensing. Therefore, the
should be active and the active phase number is
controller has less noise sensitive. Low offset amplifiers
determined and latched. The unused ISEN2N pin is
are used for current balance, loop control and over
recommended to be connected to VCC.
current detection. The ISENxP and ISEN1N pins
Loop Control denote the positive and negative input of the current
The VDD controller adopts Richtek's proprietary sense amplifier.
G-NAVPTM topology. The G-NAVPTM is based on the In order to optimize transient performance, the
finite gain peak current mode with CCRCOT (Constant recommended Req and CX will be set according to the
Current Ripple Constant On-Time) topology. The equations as below,  recommended set to 1.1.
output voltage, VVDD will decrease with increasing
Req  CX    L (9)
output load current. The control loop consists of PWM RSENSE
modulators with power stages, current sense amplifiers
Method1 : Req = RX1 (10)
and an error amplifier as shown in Figure 7.
R X1  R X2
Similar to the peak current mode control with finite Method2 : Req  (11)
R X1  R X2
compensator gain, the HS_FET on-time is determined
by CCRCOT on-time generator. When load current Considering the inductance tolerance, the resistor Req
increases (VCS increases), the steady state COMP has to be tuned on board by examining the transient
voltage also increases and induces VVDD_SENSE to voltage. If the output voltage transient has an initial dip
decrease, thus achieving AVP. A near-DC offset below the minimum load-line requirement and the
canceling is added to the output of EA to eliminate the response time is too fast causing a ring back, the value
inherent output offset of finite gain peak current mode of resistance should be increased. Vice versa, with a
controller. high resistance, the output voltage transient has only a
VIN small initial dip with a slow response time.
HS_FET VVDD
CCRCOT L RSENSE Droop Setting
PWM Driver
RX1 CX It is very easy to achieve Active Voltage Positioning
CMP
Logic
RC
+
-
VCS LS_FET RX2 (AVP) by properly setting the error amplifier gain due to
COMP2
0.75 x AI_VDD ISENxP C

+
1.867m ISENxN
the native droop characteristics as shown in Figure 8.
-
Offset IMON RIMON This target is to have
Canceling
VREF_PINSET C2 C1 VVDD = VDAC  ILOAD x RDROOP (12)
COMP R2 R1
VVDD_SENSE
FB
-
EA RGND
+
+
VSS_SENSE
-
VDAC
Figure 7. VDD Controller: Simplified Schematic with

Voltage Loop and Current Loop
29
RT3662AC
Then solving the switching condition VCOMP2 = VCS in The pole frequency of the compensator must be set to
Figure 7 yields the desired error amplifier gain as compensate the output capacitor ESR zero:
GI fP  1
A V  R2  (13) 2  C  RC
(16)
R1 RDROOP
Method1 : Where C is the capacitance of output capacitor, and RC

GI  RSENSE 1.867m  RIMON  0.75  AI_VDD (14) is the ESR of output capacitor. C2 can be calculated as
follows:
Method2 :
C  RC
GI  RSENSE 
R X2
1.867m  RIMON  0.75  AI_VDD C2  (17)
RX1  RX2 R2
(15) The zero of compensator has to be placed at half of the

Where GI is the current sense amplifier gain. RSENSE is switching frequency to filter the switching related noise.
the current sense resistor. If no external sense resistor Such that,
present, it is the equivalent resistance of the inductor. 1
C1  (18)
RIMON is the IMON equivalent resistance. For the R1   fSW
PHOCP accuracy, the RIMON resistor need to set in
C2 C1
8k to 70k. AI_VDD is the VDD controller current
gain ratio set by SET1 pin setting. RDROOP is the COMP R2 R1
VVDD_SENSE
equivalent load-line resistance as well as the desired FB
-
EA RGND
static output impedance. + VSS_SENSE
+
-
VDAC
VVDD
AV2 > AV1
Figure 9. VDD Controller: Compensation Circuit
Current Balance
AV2
The VDD controller implements internal current
AV1
balance mechanism in the current loop. The VDD
0 Load Current controller senses and compares per-phase current
Figure 8. VDD Controller: Error Amplifier gain (AV) signal with average current. If the sensed current of any
Influence on VVDD Accuracy particular phase is larger than average current, the
on-time of this phase will be adjusted to be shorter.
Loop Compensation
Optimized compensation of the VDD controller allows Initial and Dynamic Offset
for best possible load step response of the regulator's The VDD controller features initial and dynamic offset
output. A type-I compensator with one pole and one function. The VDD rail initial offset function can be
zero is adequate for proper compensation. Figure 9 implemented through the TSEN pin setting. And the
shows the compensation circuit. Previous design dynamic offset can be implemented by SVI2 interface,
procedure shows how to select the resistive feedback it controlled by CPU. Consider the offset factor, the
components for the error amplifier gain. Next, C1 and VDD output voltage described as below :
C2 must be calculated for compensation. The target is VVDD  VDAC  ILOAD  RDROOP  VINI_OFS  VDYN_OFS (19)
to achieve constant resistive output impedance over VINI_OFS is the initial offset voltage set by pin setting
the widest possible frequency range. function, and the dynamic offset voltage, VDYN_OFS,
controlled by CPU, and it can be set through the SVI2
interface.
30
RT3662AC
Dynamic VID Enhancement Current Monitoring and Reporting
During a dynamic VID event, the charging (dynamic The VDD controller provides current monitoring
VID up) or discharging (dynamic VID down) current function via inductor current sensing. In the G-NAVPTM
causes unwanted load-line effect which degrades the technology, the output voltage is dependent on output
settling time performance. The RT3662AC will hold the current, and the current monitoring function is achieved
inductor current to hold the load-line during a dynamic by this characteristic of output voltage. The equivalent
VID event. The VDD controller will always enter output current will be sensed from inductor current
full-phase configuration when it receives dynamic VID sensing and mirrored to the IMON pin. The resistor
up command; If VDD controller receives dynamic VID connected to the IMON pin determines voltage of the
down command, it will hold the operating state. IMON output.
When the VID CCM down on light loading condition, For Method1 current sensing :
the negative inductor current will be produced, and it VIMON  IL,SUM  DCRL 1.867m  RIMON  0.8 (20)
may cause the audio noise and phase ring effect. For
Where IL,SUM is the VDD output current, DCRL is the
improving the problems, the controller set the dynamic
current sense resistance, RIMON is the IMON pin
VID down slew rate to 0.625mV/s, the action will
equivalent setting resistor, and the current sense gain
reduce the negative current and phase ring effect.
equal to 1.867m.
Ramp Compensation The ADC circuit of the VDD controller monitors the
TM voltage variation at the IMON pin, and this voltage is
G-NAVP topology is one type of ripple based control
that has fast transient response. However, ripple based decoded into digital format and stored into output
control usually don't have good noise immunity. The current register.
RT3662AC provides a ramp compensation to increase VIMON  0.8
noise immunity and reduce jitter at the switching node, DIMON   255 (Bits) (21)
0.8
refer to Figure 10 shows the ramp compensation.
Quick Response
When the VDD controller takes phase shedding
operation and enters diode emulation mode, the When the transient load step-up becomes quite large, it is
internal ramp of VDD controller will be modified for the difficult for loop response to meet the energy transfer.
reason of stability. Hence, the output voltage generate undershoot to fail
specification. RT3662AC has Quick Response (QR)
W/O ramp compensation
mechanism which is able to improve this issue. It adopts a
nonlinear control mechanism which can disable
VO
interleaving function and simultaneously turn on all UGATE
VREF
Noise Margin
one pulse at instantaneous step-up transient load to
VCOMP - VCS restrain the output voltage drooping. The output voltage
signal behavior needs to be detected so that QR
PWM mechanism can be trigged. Refer to Figure 11, the output
voltage signal is via a remote sense line to connect at the
With ramp compensation
VSEN pin. The QR threshold can be set by SET1 pin
setting for VDD controller refers to Table 3.
VO
Noise Margin QR_TH

QR Pulse
-
+
VSEN
-
VRAMP
Generation CMP
Circuit +
VCOMP - VCS
PWM
Figure 11. VDD Controller : Quick Response

Figure 10. Ramp Compensation Triggering Circuit
31
RT3662AC
Over-Current Protection MOSFETs. When UVP is triggered by one rail, the
The RT3662AC provides the over current protection other rail will also enter soft shutdown sequence. A 3s
function. The OCP_SPIKE threshold will be set by the delay is used in UVP detection circuit to prevent false
current monitor resistor RIMON as below : trigger.
For Method1 current sensing : Under-Voltage Lock Out (UVLO)

1.6  0.8 During normal operation, if the voltage at the VCC pin
OCP_SPIKE  (22)
DCRL  1.867m  RIMON drops below IC POR threshold, the VDD controller will
trigger UVLO. The UVLO protection forces all high-side
For prevent the OCP false trigger, the trigger delay is
requirement, refer to Electrical Characteristics. When and low-side MOSFETs off by shutting down internal
output current is still higher than the OCP_SPIKE after PWM logic drivers. A 3s delay is used in UVLO
the trigger delay time, the OCP will be latched, and detection circuit to prevent false trigger.
then the VDD controller will turn off both high-side and VDDNB Controller
low-side MOSFETs of all channels.
VDDNB Controller Disable
Per-Phase Over Current Protection The VDDNB controller can be disabled by connecting
The VDD controller provides per-phase over current ISENP_NB to a voltage higher than “VCC  0.5V”. If
protection (PHOCP) function in each phase. If the VDD not in use, ISENN_NB is recommended to be
controller force 1 phase operation by pulling ISEN2P connected to VCC. When VDDNB controller is disabled,
pin to 5V, it only detected at soft-start duration when all SVID commands related to VDDNB controller will be
VR power on. The VDD PHOCP threshold is set by rejected.
TSEN pin setting described as below :
(23) Loop Control
N
PHOCP_TH  OCP_SPIKE  The VDDNB controller adopts Richtek's proprietary
M
G-NAVPTM topology. The G-NAVPTM is based on the
N is the VDD PHOCP setting ratio, M is the operation
finite gain peak current mode with CCRCOT (Constant
phase number.
Current Ripple Constant On-Time) topology. The
If the PHOCP is triggered, the controller will turn off all
output voltage, VVDDNB will decrease with increasing
high-side and low-side MOSFETs to protect CPU. output load current. The control loop consists of PWM
Over-Voltage Protection (OVP) modulators with power stages, current sense amplifiers
and an error amplifier as shown in Figure 12.
The OVP circuit of the VDD controller monitors the
output voltage via the VSEN pin after POR. When the Similar to the peak current mode control with finite
VSEN voltage exceeds the OVP threshold 1.85V, OVP compensator gain, the HS_FET on-time is determined
is triggered and latched. The VDD controller will try to by CCRCOT on-time generator. When load current
turn on low-side MOSFET and turn off high-side increases, VCS increases, the steady state COMP
MOSFET of all active phases to protect the CPU. When voltage also increases and induces VVDDNB_SENSE to
OVP is triggered by one rail, the other rail will also enter decrease, thus achieving AVP. A near-DC offset
soft shut down sequence. A 1s delay is used in OVP canceling is added to the output of EA to eliminate the
detection circuit to prevent false trigger. inherent output offset of finite gain peak current mode
controller.
Under-Voltage Protection (UVP)
The VDD controller implements UVP of VSEN pin. If
VSEN voltage is less than the internal reference by
500mV, the VDD controller will trigger UVP latch. The
UVP latch will turn off both high-side and low-side
32
RT3662AC
VIN high resistance, the output voltage transient has only a
small initial dip with a slow response time.
HS_FET VVDDNB
CCRCOT L RSENSE
PWM Driver Droop Setting
RX1 CX
CMP
Logic
RC
+
-
VCS LS_FET RX2 It is very easy to achieve Active Voltage Positioning

COMP2
0.75 x AI_VDDNB ISENP_NB C

+
1.867m ISENN_NB
(AVP) by properly setting the error amplifier gain due to
-
Offset IMON_NB RIMON_NB the native droop characteristics as shown in Figure 13.
Canceling
VREF_PINSET C2 C1 This target is to have
COMP_NB R2 R1 VVDDNB = VDAC  ILOAD x RDROOP (27)

VVDDNB_SENSE
FB_NB
-
EA RGND Then solving the switching condition VCOMP2 = VCS in
+
+
VSS_SENSE
-
VDAC Figure 12 yields the desired error amplifier gain as

GI
Figure 12. VDDNB Controller : Simplified Schematic A V  R2 
R1 RDROOP
(28)
with Voltage Loop and Current Loop
Method1 :
Current Sense Setting GI  RSENSE 1.867m  RIMON  0.75  AI_VDDNB (29)
Refer to Figure 12, for different RSENSE resistor, the Method2 :
current sense method can classify as two types. The
RX2
GI  RSENSE  1.867m  RIMON  0.75  AI_VDDNB
method1 only use RX1 for lower RSENSE application, RX1  RX2 (30)
and the method2 use RX1 and RX2 to divide the current
signal for higher RSENSE application. Richtek also Where GI is the current sense amplifier gain. RSENSE is
provide Excel based design tool to let user choose the the current sense resistor. If no external sense resistor
appropriate components quickly. present, it is the equivalent resistance of the inductor.
RIMON_NB is the IMON_NB equivalent resistance. For
The current sense topology of the VDDNB controller is
the PHOCP accuracy, the RIMON_NB resistor need to
continuous inductor current sensing. Therefore, the
set in 8k to 70k. AI_VDDNB is the VDDNB
controller has less noise sensitive. Low offset amplifiers
controller current gain ratio set by SET1 pin setting.
are used for loop control and over current detection.
RDROOP is the equivalent load-line resistance as well
The ISENP_NB and ISENN_NB pins denote the
as the desired static output impedance.
positive and negative input of the current sense
amplifier. VVDDNB
AV2 > AV1
In order to optimize transient performance, the
recommended Req and CX will be set according to the
equation as below, and  recommended set to 1.1.
AV2
Req  CX    L
(24) AV1
RSENSE
Method1 : Req  R X1 (25) 0 Load Current
R X1  R X2 Figure 13. VDDNB Controller : Error Amplifier gain (AV)

Method2 : Req  (26)
R X1  R X2 Influence on VVDDNB Accuracy
Considering the inductance tolerance, the resistor Req
Loop Compensation
has to be tuned on board by examining the transient
Optimized compensation of the VDDNB controller
voltage. If the output voltage transient has an initial dip
allows for best possible load step response of the
below the minimum load-line requirement and the
regulator’s output. A type-I compensator with one pole
response time is too fast causing a ring back, the value
and one zero is adequate for proper compensation.
of resistance should be increased. Vice versa, with a
33
RT3662AC
Figure 14 shows the compensation circuit. Previous VINI_OFS is the initial offset voltage set by pin setting
design procedure shows how to select the resistive function, and the dynamic offset voltage, VDYN_OFS,
feedback components for the error amplifier gain. Next, controlled by CPU, and it can be set through the SVI2
C1 and C2 must be calculated for compensation. The interface.
target is to achieve constant resistive output
Dynamic VID Enhancement
impedance over the widest possible frequency range.
During a dynamic VID event, the charging (dynamic
The pole frequency of the compensator must be set to
VID up) or discharging (dynamic VID down) current
compensate the output capacitor ESR zero :
causes unwanted load-line effect which degrades the
fP  1 (31) settling time performance. The RT3662AC will hold the
2  C  RC
inductor current to hold the load-line during a dynamic
Where C is the capacitance of output capacitor, and RC VID event. The VDDNB controller will always enter
is the ESR of output capacitor. C2 can be calculated as CCM operation when it receives dynamic VID up
follows : command; If VDD controller receives dynamic VID
down command, it will hold the operating state.
C x RC
C2  (32)
When the VID CCM down on light loading condition,
R2
the negative inductor current will be produced, and it
The zero of compensator has to be placed at half of the may cause the audio noise and phase ring effect. For
switching frequency to filter the switching related noise. improving the problems, the controller set the dynamic
Such that, VID down slew rate to 0.625mV/s, the action will
1 reduce the negative current and phase ring effect.
C1  (33)
R1   fSW
Ramp Compensation
C2 C1
G-NAVPTM topology is one type of ripple based control
COMP_NB R2 R1 that has fast transient response. However, ripple based
VVDDNB_SENSE
FB_NB control usually don't have good noise immunity. The
-
EA RGND
+ VSS_SENSE RT3662AC provides a ramp compensation to increase
+
-
VDAC noise immunity and reduce jitter at the switching node

refer to Figure 10 shows the ramp compensation.
Figure 14. VDDNB Controller : Compensation Circuit
When the VDDNB controller takes phase shedding
Initial and Dynamic Offset operation and enters diode emulation mode, the
internal ramp of VDDNB controller will be modified for
The VDDNB controller features initial and dynamic
the reason of stability.
offset function. The initial offset function can be
implemented through the TSEN pin setting. And the Current Monitoring and Reporting
Dynamic offset can be implemented by SVI2 interface,
The VDDNB controller provides current monitoring
it controlled by CPU. Consider the offset factor, the
function via inductor current sensing. In the G-NAVPTM
VDDNB output voltage described as below :
technology, the output voltage is dependent on output
VVDDNB  VDAC  ILOAD  RDROOP  current, and the current monitoring function is achieved
(34)
VINI_OFS  VDYN_OFS by this characteristic of output voltage. The equivalent
output current will be sensed from inductor current
sensing and mirrored to the IMON_NB pin. The resistor
connected to the IMON_NB pin determines voltage of
the IMON_NB output.
34
RT3662AC
For Method1 current sensing : Over-Current Protection
VIMON_NB  IL,SUM  DCRL 1.867m  RIMON_NB  0.8 (35) The RT3662AC provides the over current protection
function. The OCP_SPIKE_NB threshold will be set by
Where IL,SUM is the VDDNB output current, DCRL is
the current monitor resistor RIMON_NB as below :
the current sense resistance, RIMON_NB is the
IMON_NB pin equivalent setting resistor, and the For Method1 current sensing :
current sense gain equal to 1.867m. 1.6  0.8
OCP_SPIKE_NB  (38)
The ADC circuit of the VDDNB controller monitors the DCRL  1.867m  RIMON_NB
voltage variation at the IMON_NB pin, and this voltage For prevent the OCP false trigger, the trigger delay is
is decoded into digital format and stored into output requirement, refer to Electrical Characteristics. When
current register. output current is still higher than the OCP_SPIKE_NB
VIMON_NB  0.8 after the trigger delay time, the OCP will be latched,
DIMON_NB   255 (Bits) (36)
0.8 and then the VDDNB controller will turn off both
high-side and low-side MOSFETs.
VDDNB Voltage Reporting Offset
Per-Phase Over Current Protection
The VDDNB controller senses the ISENN_NB voltage
The VDDNB controller provides per-phase over current
for voltage reporting. In Figure 15, due to the PCB trace
protection (PHOCP) function, it only detected at
(RPCB) from ISENN_NB to output capacitor, it will
soft-start duration when VR power on. The PHOCP
cause the voltage drop on loading, as the loading
threshold is set by TSEN_NB pin setting described as
current become bigger, the drop will affect the voltage
below :
reporting seriously. Through the voltage reporting
offset function, it can be improved, and the voltage (39)
PHOCP_TH  OCP_SPIKE_NB  N
reporting of VDDNB controller (VVDDNB_RPT) can be
described as below : N is the VDDNB PHOCP setting ratio.
VVDDNB_RPT(d)  VISENN_NB_ADC(d)  VVDDNB_RPT_OFS(d) If the PHOCP is triggered, the controller will turn off all
(37) high-side and low-side MOSFETs to protect CPU.
VVDDNB_RPT is the VDDNB voltage reporting digital Over-Voltage Protection (OVP)

code, VISENN_NB_ADC is the ISENN_NB sensed voltage
The OVP circuit of the VDDNB controller monitors the
digital code and VVDDNB_RPT_OFS is the VDDNB
output voltage via the ISENN_NB pin after POR. When
voltage reporting offset bits.
the ISENN_NB voltage exceeds the OVP threshold
VIN
1.85V, OVP is triggered and latched. The VDDNB
30
BOOT_NB controller will try to turn on low-side MOSFET and turn
UGATE_NB 31 VVDDNB
32
RPCB off high-side MOSFET of all active phases to protect
PHASE_NB
LGATE_NB
33
LOAD
the CPU. When OVP is triggered by one rail, the other
rail will also enter soft shut down sequence. A 1s
ISENP_NB 25 delay is used in OVP detection circuit to prevent false
ISENN_NB 24
trigger.
Under-Voltage Protection (UVP)

Figure 15. The Description of PCB trace from
The VDDNB controller implements UVP of ISENN_NB pin.
ISENN_NB to Output Capacitor
If ISENN_NB voltage is less than the internal reference by
500mV, the VDDNB controller will trigger UVP latch. The
UVP latch will turn off both high-side and low-side
MOSFETs. When UVP is triggered by one rail, the other
rail will also enter soft shutdown sequence. A 3s delay is
35
RT3662AC
used in UVP detection circuit to prevent false trigger. The maximum power dissipation depends on the
operating ambient temperature for fixed TJ(MAX) and
Under-Voltage Lock Out (UVLO)
thermal resistance, JA. The derating curve in Figure
During normal operation, if the voltage at the VCC pin 16 allows the designer to see the effect of rising
drops below IC POR threshold, the VDDNB controller ambient temperature on the maximum power
will trigger UVLO. The UVLO protection forces all dissipation.
high-side and low-side MOSFETs off by shutting down
4.0
internal PWM logic drivers. A 3s delay is used in
Maximum Power Dissipation (W)1

Four-Layer PCB
UVLO detection circuit to prevent false trigger. 3.5
3.0
Thermal Considerations
2.5
For continuous operation, do not exceed absolute
2.0
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC 1.5
package, PCB layout, rate of surrounding airflow, and 1.0

difference between junction and ambient temperature.
0.5
The maximum power dissipation can be calculated by
0.0
the following formula : 0 25 50 75 100 125
PD(MAX) = (TJ(MAX)  TA) / JA Ambient Temperature (°C)
where TJ(MAX) is the maximum junction temperature,
Figure 16. Derating Curve of Maximum Power
TA is the ambient temperature, and JA is the junction
Dissipation
to ambient thermal resistance.
For recommended operating condition specifications,
the maximum junction temperature is 125C. The
junction to ambient thermal resistance, JA, is layout
dependent. For WQFN-40L 5x5 package, the thermal
resistance, JA, is 27.5C/W on a standard JEDEC
51-7 four-layer thermal test board. The maximum
power dissipation at TA = 25C can be calculated by
the following formula :
PD(MAX) = (125C  25C) / (27.5C/W) = 3.63W for
WQFN-40L 5x5 package
36
RT3662AC
Outline Dimension
Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.150 0.250 0.006 0.010
D 4.950 5.050 0.195 0.199
D2 3.250 3.500 0.128 0.138
E 4.950 5.050 0.195 0.199
E2 3.250 3.500 0.128 0.138
e 0.400 0.016
L 0.350 0.450 0.014 0.018
W-Type 40L QFN 5x5 Package
Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume
responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and
reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
37

Datasheet

Uploaded by

Copyright:

Available Formats

Datasheet

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Datasheet

Uploaded by

Copyright:

Available Formats

RT3662AC

Dual-Output PWM Controller with 3 Integrated Drivers for

Simplified Application Circuit

 RoHS compliant and compatible with the current PGOOD 3 28 VIN

Functional Pin Description

SVI2 Interface/Configuration Registers/Control PWM CMP

Soft-Start and Slew-Rate Control

TSEN_NB Pin Setting Voltage

Recommended Operating Conditions (Note 4)

4.7k 4.7k 10k VIN

CORE VR Power On from EN CORE VR Power Off from EN

Boot VID = 0.8V VDD Boot VID = 0.8V

Time (500μs/Div) Time (200μs/Div)

CORE VR Thermal Monitoring CORE VR OCP_SPIKE

ILoad = 60A to 90A

Time (10ms/Div) Time (10μs/Div)

CORE VR OVP CORE VR UVP

VID = 1.1V VDD VID = 1.1V

Time (10μs/Div) Time (10μs/Div)

CORE VR Dynamic VID Up CORE VR Dynamic VID Up

Time (20μs/Div) Time (10μs/Div)

CORE VR Dynamic VID Up CORE VR Dynamic VID Up

Time (10μs/Div) Time (10μs/Div)

CORE VR Dynamic VID Up CORE VR Load Transient

Time (10μs/Div) Time (5μs/Div)

CORE VR Load Transient NB VR Thermal Monitoring

Time (5μs/Div) Time (10ms/Div)

NB VR Power On from EN NB VR Power Off from EN

Boot VID = 0.8V Boot VID = 0.8V

Time (500μs/Div) Time (200μs/Div)

ILoad = 15A to 40A VID = 1.1V

Time (10μs/Div) Time (10μs/Div)

NB VR UVP NB VR Dynamic VID Up

Time (10μs/Div) Time (20μs/Div)

NB VR Dynamic VID Up NB VR Dynamic VID Up

Time (10μs/Div) Time (10μs/Div)

NB VR Dynamic VID Up NB VR Dynamic VID Up

Time (10μs/Div) Time (10μs/Div)

NB VR Load Transient NB VR Load Transient

Time (5μs/Div) Time (5μs/Div)

Figure 2. Simplified Sequence Timing Diagram

Table 8. SVD Data Packet

Voltage and Current VDDNB Voltage Bit in Voltage Only Mode;

Bit Time…… START STOP

Figure 3. Telemetry Bit Definition

PWROK and SVI2 Operation VID on-the-Fly Transition

Figure 6. TSEN and TSEN_NB Circuit

0.75 x AI_VDD ISENxP C

Figure 7. VDD Controller: Simplified Schematic with

Method1 : Where C is the capacitance of output capacitor, and RC

(15) The zero of compensator has to be placed at half of the

Noise Margin QR_TH

Figure 11. VDD Controller : Quick Response

For Method1 current sensing : Under-Voltage Lock Out (UVLO)

VCS LS_FET RX2 It is very easy to achieve Active Voltage Positioning

0.75 x AI_VDDNB ISENP_NB C

COMP_NB R2 R1 VVDDNB = VDAC  ILOAD x RDROOP (27)

VDAC Figure 12 yields the desired error amplifier gain as

R X1  R X2 Figure 13. VDDNB Controller : Error Amplifier gain (AV)