bq2014 Controlador de Carga para Bateria
bq2014 Controlador de Carga para Bateria
bq2014 Controlador de Carga para Bateria
bq2014
Gas Gauge IC with External Charge Control
Features General Description Nominal Available Charge (NAC)
may be directly indicated using a
➤ Conservative and repeatable The bq2014 Gas Gauge IC is in- five-segment LED display.
measurement of available charge tended for battery-pack or in-system
in rechargeable batteries installation to maintain an accurate The bq2014 supports a simple single-
record of available battery charge. line bidirectional serial link to an ex-
➤ Charge control output operates an The IC monitors the voltage drop ternal processor (with a common
external charge controller such as across a sense resistor connected in ground). The bq2014 outputs battery
the bq2004 Fast Charge IC series between the negative battery information in response to external
terminal and ground to determine commands over the serial link.
➤ Designed for battery pack inte-
gration charge and discharge activity of the Internal registers include available
battery. charge, temperature, capacity, bat-
- 120µA typical standby current Self-discharge of NiMH and NiCd tery voltage, battery ID, battery
batteries is estimated based on an status, and programming pin set-
➤ Display capacity via single-wire tings. To support subassembly test-
serial communication port or di- internal timer and temperature sen-
sor. Compensations for battery tem- ing, the outputs may also be con-
rect drive of LEDs trolled. The external processor may
perature and rate of charge or dis-
➤ Measurements compensated for charge are applied to the charge, dis- also overwrite some of the bq2014
current and temperature charge, and self-discharge calcula- gas gauge data registers.
tions to provide available charge in- The bq2014 may operate directly
➤ Self-discharge compensation using formation across a wide range of op-
internal temperature sensor from three or four cells. With the
erating conditions. Battery capacity REF output and an external transis-
➤ User-selectable end-of-discharge is automatically recalibrated, or tor, a simple, inexpensive regulator
threshold “learned,” in the course of a dis- can be built to provide VCC across a
charge cycle from full to empty. greater number of cells.
➤ Battery voltage, nominal avail-
able charge, temperature, etc. The bq2014 includes a charge con-
available over serial port trol output that controls an external
Fast Charge IC such as the bq2004.
➤ 16-pin narrow SOIC
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bq2014
LCOM LED common output The voltage drop (VSR) across the sense re-
sistor RS is monitored and integrated over
Open-drain output switches VCC to source time to interpret charge and discharge activ-
current for the LEDs. The switch is off dur- ity. The SR input is tied to the high side of
ing initialization to allow reading of the soft the sense resistor. VSR < VSS indicates dis-
pull-up or pull-down programming resistors. charge, and VSR > VSS indicates charge. The
LCOM is also in a high impedance state effective voltage drop VSRO, as seen by the
when the display is off. bq2014, is VSR + VOS (see Table 5).
SEG1– LED display segment outputs (dual func- DISP Display control input
SEG5 tion with PROG1—PROG5)
DISP high disables the LED display. DISP
Each output may activate an LED to sink tied to VCC allows PROGX to connect di-
the current sourced from LCOM. rectly to VCC or VSS instead of through a
pull-up or pull-down reistor. DISP floating
PROG1– Programmed full count selection imputs allows the LED display to be active during
PROG5 (dual function with SEG1—SEG5) a valid charge or during discharge if the
NAC register is updated at a rate equiva-
These three-level input pins define the pro-
lent to V SRO ≤ -4mV. DISP low activates
grammed full count (PFC) thresholds de-
the display. See Table 1.
scribed in Table 2.
SB Secondary battery input
PROG3– Gas gauge rate selection inputs (dual
PROG4 function with SEG3—SEG4) This input monitors the single-cell voltage
potential through a high-impedance resis-
These three-level input pins define the pro-
tive divider network for the end-of-discharge
grammed full count (PFC) thresholds de-
voltage (EDV) thresholds,maximum charge
scribed in Table 2.
voltage (MCV), and battery removed.
PROG5 Self-discharge rate selection (dual func-
EMPTY Battery empty output
tion with SEG5)
This open-drain output becomes high-
This three-level input pin defines the self-
impedance on detection of a valid final end-
discharge compensation rate shown in Ta-
of-discharge voltage (VEDVF) and is low fol-
ble 1.
lowing the next application of a valid charge.
CHG Charge control output
DQ Serial I/O pin
This open-drain output becomes active high
This is an open-drain bidirectional pin.
when charging is allowed.
REF Voltage reference output for regulator
DONE Fast charge complete
REF provides a voltage reference output for
This input is used to communicate the
an optional micro-regulator.
status of an external charge controller such
as the bq2004 Fast Charge IC. Note: This VCC Supply voltage input
pin must be pulled down to VSS using a
200KΩ resistor. VSS Ground
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bq2014
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bq2014
Two EDV thresholds for the bq2014 are programmable 6x 20°C to 30°C
with the default values fixed at:
7x 30°C to 40°C
EDV1 (early warning) = 1.05V
EDVF (empty) = 0.95V 8x 40°C to 50°C
If VSB is below either of the two EDV thresholds, the as- 9x 50°C to 60°C
sociated flag is latched and remains latched, independ-
ent of VSB, until the next valid charge (as defined in the Ax 60°C to 70°C
section entitled “Gas Gauge Operation”). The VSB value
is also available over the serial port. Bx 70°C to 80°C
During discharge and charge, the bq2014 monitors VSR Cx > 80°C
for various thresholds. These thresholds are used to
compensate the charge and discharge rates. Refer to the
count compensation section for details. EDV monitoring
is disabled if VSR ≤ -250mV typical and resumes ½ sec-
Layout Considerations
ond after VSR > -250mV. The bq2014 measures the voltage differential between
the SR and VSS pins. VOS (the offset voltage at the SR
EMPTY Output pin) is greatly affected by PC board layout. For optimal
results, the PC board layout should follow the strict rule
The EMPTY output switches to high impedance when of a single-point ground return. Sharing high-current
VSB < VEDF and remains latched until a valid charge oc- ground with small signal ground causes undesirable
curs. noise on the small signal nodes. Additionally:
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bq2014
- - + +
Nominal Last Discharge
Main Counters
and Capacity
+
Available
Charge
< Measured
Discharged
Count
Qualified Register
Reference (LMD) (NAC) (LMD) Transfer (DCR)
Chip-Controlled Serial
Outputs Available Charge Port
LED Display
FG201002.eps
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bq2014
Programmed
PROGx Full PROG4 = L PROG4 = Z
Count
1 2 (PFC) PROG3 = H PROG3 = Z PROG3 = L PROG3 = H PROG3 = Z PROG3 = L Units
Scale = Scale = Scale = Scale = Scale = Scale = mVh/
- - -
1/80 1/160 1/320 1/640 1/1280 1/2560 count
H H 49152 614 307 154 76.8 38.4 19.2 mVh
H Z 45056 563 282 141 70.4 35.2 17.6 mVh
H L 40960 512 256 128 64.0 32.0 16.0 mVh
Z H 36864 461 230 115 57.6 28.8 14.4 mVh
Z Z 33792 422 211 106 53.0 26.4 13.2 mVh
Z L 30720 384 192 96.0 48.0 24.0 12.0 mVh
L H 27648 346 173 86.4 43.2 21.6 10.8 mVh
L Z 25600 320 160 80.0 40.0 20.0 10.0 mVh
L L 22528 282 141 70.4 35.2 17.6 8.8 mVh
VSR equivalent to 2
90 45 22.5 11.25 5.6 2.8 mV
counts/s (nom.)
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bq2014
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bq2014
30–40°C NAC
32
NAC
23 .5
50–60°C NAC
8
NAC
5 .88
Corrections for the rate of discharge are made by adjust-
ing an internal discharge compensation factor. The dis- 60–70°C NAC
4
NAC
2 .94
charge factor is based on the dynamically measured VSR. > 70°C NAC
2
NAC
1 .47
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bq2014
whenever LMD is updated from the DCR. The counter either polled or interrupt processing. Data input from the
does not wrap around but stops counting at 255. The ca- bq2014 may be sampled using the pulse-width capture
pacity inaccurate flag (CI) is set if LMD has not been up- timers available on some microcontrollers.
dated following 64 valid charges.
Communication is normally initiated by the host proces-
Current-Sensing Error sor sending a BREAK command to the bq2014. A
BREAK is detected when the DQ pin is driven to a
Table 5 illustrates the current-sensing error as a func- logic-low state for a time, tB or greater. The DQ pin
tion of V SR . A digital filter eliminates charge and should then be returned to its normal ready-high logic
discharge counts to the NAC register when VSRO (VSR + state for a time, tBR. The bq2014 is now ready to receive
VOS) is between VSRQ and VSRD. a command from the host processor.
The return-to-one data bit frame consists of three distinct
Communicating With the bq2014 sections. The first section is used to start the transmission
The bq2014 includes a simple single-pin (DQ plus re- by either the host or the bq2014 taking the DQ pin to a
turn) serial data interface. A host processor uses the in- logic-low state for a period, tSTRH,B. The next section is the
terface to access various bq2014 registers. Battery char- actual data transmission, where the data should be valid by
acteristics may be easily monitored by adding a single a period, tDSU, after the negative edge used to start commu-
contact to the battery pack. The open-drain DQ pin on nication. The data should be held for a period, tDV, to allow
the bq2014 should be pulled up by the host system, or may the host or bq2014 to sample the data bit.
be left floating if the serial interface is not used. The final section is used to stop the transmission by return-
The interface uses a command-based protocol, where the ing the DQ pin to a logic-high state by at least a period,
host processor sends a command byte to the bq2014. tSSU, after the negative edge used to start communication.
The command directs the bq2014 to either store the next The final logic-high state should be held until a period, tSV,
eight bits of data received to a register specified by the to allow time to ensure that the bit transmission was
command byte or output the eight bits of data specified stopped properly. The timings for data and break commu-
by the command byte. nication are given in the serial communication timing
specification and illustration sections.
The communication protocol is asynchronous return-to-
one. Command and data bytes consist of a stream of eight Communication with the bq2014 is always performed
bits that have a maximum transmission rate of 333 with the least-significant bit being transmitted first.
bits/sec. The least-significant bit of a command or data Figure 3 shows an example of a communication se-
byte is transmitted first. The protocol is simple enough quence to read the bq2014 NAC register.
that it can be implemented by most host processors using
Break 1 1 0 0 0 0 0 0 1 0 1 0 011 0
DQ
TD201401.eps
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bq2014
The bq2014 command and status registers are listed in 0 Either discharge activity detected or VSRO <
Table 6 and described below. VSRQ
1 VSRO > VSRQ
Command Register (CMDR)
The battery replaced flag (BRP) is asserted whenever
The write-only CMDR register is accessed when eight the potential on the SB pin (relative to VSS), VSB, falls
valid command bits have been received by the bq2014. from above the maximum cell voltage, MCV (2.25V), or
The CMDR register contains two fields: rises above 0.1V. The BRP flag is also set when the
n W/R bit bq2014 is reset (see the RST register description). BRP
is reset when either a valid charge action increments
n Command address NAC to be equal to LMD, or a valid charge action is de-
tected after the EDV1 flag is asserted. BRP = 1 signifies
The W/R bit of the command register is used to select that the device has been reset.
whether the received command is for a read or a write
function. The BRP values are:
The W/R values are: FLGS1 Bits
CMDR Bits 7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0 - BRP - - - - - -
W/R - - - - - - -
Where BRP is:
Where W/R is: 0 Battery is charged until NAC = LMD or dis-
charged until the EDV1 flag is asserted
0 The bq2014 outputs the requested register
contents specified by the address portion of 1 VSB dropping from above MCV, VSB rising
CMDR. from below 0.1V, or a serial port initiated
reset has occurred
1 The following eight bits should be written
to the register specified by the address por- The battery removed flag (BRM) is asserted whenever
tion of CMDR. the potential on the SB pin (relative to VSS) rises above
MCV or falls below 0.1V. The BRM flag is asserted until
The lower seven-bit field of CMDR contains the address
the condition causing BRM is removed. Because of sig-
portion of the register to be accessed. Attempts to write
nal filtering, 30 seconds may have to transpire for BRM
to invalid addresses are ignored.
to react to battery insertion or removal.
CMDR Bits The BRM values are:
7 6 5 4 3 2 1 0
FLGS1 Bits
AD0
- AD6 AD5 AD4 AD3 AD2 AD1
(LSB) 7 6 5 4 3 2 1 0
- - BRM - - - - -
Primary Status Flags Register (FLGS1)
The read-only FLGS1 register (address=01h) contains Where BRM is:
the primary bq2014 flags. 0 0.1V < VSB < 2.25V
The charge status flag (CHGS) is asserted when a 1 0.1V > VSB or VSB > 2.25V
valid charge rate is detected. Charge rate is deemed
valid when VSRO > VSRQ. A VSRO of less than VSRQ or The capacity inaccurate flag (CI) is used to warn the
discharge activity clears CHGS. user that the battery has been charged a substantial
number of times since LMD has been updated. The CI
The CHGS values are: flag is asserted on the 64th charge after the last LMD
FLGS1 Bits update or when the bq2014 is reset. The flag is cleared
after an LMD update.
7 6 5 4 3 2 1 0
CHGS - - - - - - -
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bq2014
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bq2014
The CI values are: Where EDV1 is:
0 Valid charge action detected,VSB ≥ VTS
FLGS1 Bits
7 6 5 4 3 2 1 0 1 VSB < VTS providing that OVLD=0 (see
FLGS2 register description)
- - - CI - - - -
The final end-of-discharge warning flag (EDVF) flag
Where CI is: is used to warn that battery power is at a failure condi-
tion. All segment drivers are turned off. The EDVF flag
0 When LMD is updated with a valid full dis- is latched until a valid charge has been detected. The
charge EMPTY pin is also forced to a high-impedance state on
1 After the 64th valid charge action with no assertion of EDVF. The host system may pull EMPTY
LMD updates or when the device is reset high, which may be used to disable circuitry to prevent
deep-discharge of the battery. The EDVF threshold is
The valid discharge flag (VDQ) is asserted when the set 100mV below the EDV1 threshold.
bq2014 is discharged from NAC = LMD or DONE is
valid. The flag remains set until either LMD is updated The EDVF values are:
or one of three actions that can clear VDQ occurs:
n The self-discharge count register (SDCR) has FLGS1 Bits
exceeded the maximum acceptable value (4096 7 6 5 4 3 2 1 0
counts) for an LMD update. - - - - - - - EDVF
n A valid charge action sustained at VSRO > VSRQ for at
least 256 NAC counts. Where EDVF is:
n The EDV flag was set at a temperature below 0°C 0 Valid charge action detected,
VSB ≥ VTS - 100mV
The VDQ values are:
1 VSB < VTS - 100mV providing that OVLD=0
FLGS1 Bits
(see FLGS2 register description)
7 6 5 4 3 2 1 0
- - - - VDQ - - - Voltage Threshold Register (VTS)
The end-of-discharge threshold voltages (EDV1 and
Where VDQ is: EDVF) can be set using the VTS register (address=0ch).
The read/write VTS register sets the EDV1 trip point.
0 SDCR ≥ 4096, subsequent valid charge ac- EDVF is set 100mV below EDV1. The default value in
tion detected, or EDV1 is asserted with the the VTS register is 70h, representing EDV1 = 1.05V and
temperature less than 0°C EDVF = 0.95V. EDV1 = 2.4V ∗ (VTS/256).
1 On first discharge after NAC = LMD or
DONE is valid VTS Register Bits
7 6 5 4 3 2 1 0
The first end-of-discharge warning flag (EDV1)
warns the user that the battery is almost empty. The VTS7 VTS6 VTS5 VTS4 VTS3 VTS2 VTS1 VTS0
first segment pin, SEG1, is modulated at a 4Hz rate if
the display is enabled once EDV1 is asserted, which
should warn the user that loss of battery power is immi-
Battery Voltage Register (VSB)
nent. The EDV1 flag is latched until a valid charge has The read-only battery voltage register is used to read
been detected. The EDV1 threshold is externally con- the single-cell battery voltage on the SB pin. The VSB
trolled via the VTS register (see Voltage Threshold Reg- register is updated approximately once per second with
ister on this page). the present value of the battery voltage.
VSB = 2.4V ∗ (VSB/256)
The EDV1 values are:
FLGS1 Bits VSB Register Bits
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
- - - - - - EDV1 - VSB7 VSB6 VSB5 VSB4 VSB3 VSB2 VSB1 VSB0
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bq2014
The gas gauge display and the gas gauge portion of the
Battery Identification Register (BATID)
TMPGG register are adjusted for cold temperature de- The read/write BATID register (address=04h) is avail-
pendencies. A piece-wise correction is performed as fol- able for use by the system to determine the type of bat-
lows: tery pack. The BATID contents are retained as long as
VCC is greater than 2V. The contents of BATID have no
Temperature Available Capacity Calculation effect on the operation of the bq2014. There is no de-
fault setting for this register.
> 0°C NAC / “Full Reference”
-20°C < T < 0°C 0.75 * NAC / “Full Reference” Last Measured Discharge Register (LMD)
< -20°C 0.5 * NAC / “Full Reference” LMD is a read/write register (address=05h) that the
bq2014 uses as a measured full reference. The bq2014
adjusts LMD based on the measured discharge capacity
The adjustment between > 0°C and -20°C < T < 0°C has a of the battery from full to empty. In this way the bq2014
10°C hysteresis. updates the capacity of the battery. LMD is set to PFC
during a bq2014 reset.
Nominal Available Charge Register
(NACH/NACL) Secondary Status Flags Register (FLGS2)
The read/write NACH register (address=03h) and the The read-only FLGS2 register (address=06h) contains
read-only NACL low-byte register (address=17h) are the the secondary bq2014 flags.
main gas gauging registers for the bq2014. The NAC
registers are incremented during charge actions and The charge rate flag (CR) is used to denote the fast
decremented during discharge and self-discharge ac- charge regime. Fast charge is assumed whenever a
tions. The correction factors for charge/discharge effi- charge action is initiated. The CR flag remains asserted
ciency are applied automatically to NAC. if the charge rate does not fall below 2 counts/sec.
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bq2014
The CR values are: pull-down resistors, the contents of PPD are xx101001.
(Note: DONE must be pulled down for proper operation.)
FLGS2 Bits
7 6 5 4 3 2 1 0 Program Pin Pull-Up Register (PPU)
CR - - - - - - - The read-only PPU register (address=08h) contains the
rest of the programming pin information for the bq2014.
Where CR is: The segment drivers, SEG1–5 and DONE, have corre-
sponding PPU register locations, PPU1–6. A given loca-
0 When charge rate falls below 2 counts/sec tion is set if a pull-up resistor has been detected on its
corresponding segment driver. For example, if SEG3 and
1 When charge rate is above 2 counts/sec DONE have pull-up resistors, the contents of PPU are
The fast charge regime efficiency factors are used when xx100100.
CR = 1. When CR = 0, the trickle charge efficiency fac-
tors are used. The time to change CR varies due to the PPD/PPU Bits
user-selectable count rates. 8 7 6 5 4 3 2 1
The discharge rate flags, DR2–0, are bits 6–4. - - PPU6 PPU5 PPU4 PPU3 PPU2 PPU1
- - PPD6 PPD5 PPD4 PPD3 PPD2 PPD1
FLGS2 Bits
7 6 5 4 3 2 1 0
- DR2 DR1 DR0 - - -
Capacity Inaccurate Count Register (CPI)
The read-only CPI register (address=09h) is used to in-
They are used to determine the current discharge re- dicate the number of times a battery has been charged
gime as follows: without an LMD update. Because the capacity of a re-
chargeable battery varies with age and operating condi-
DR2 DR1 DR0 VSR (V) tions, the bq2014 adapts to the changing capacity over
time. A complete discharge from full (NAC=LMD) to
0 0 0 VSR > -150mV empty (EDV1=1) is required to perform an LMD update
0 0 1 VSR < -150mV assuming there have been no intervening valid charges,
the temperature is greater than or equal to 0°C, and the
The overload flag (OVLD) is asserted when a discharge self-discharge counter is less than 4096 counts.
overload is detected, VSR < -250mV. OVLD remains as- The CPI register is incremented every time a valid
serted as long as the condition persists and is cleared af- charge is detected. When NAC > 0.94 ∗ LMD, however,
ter VSR > -150mV. The overload condition is used to stop the CPI register increments on the first valid charge;
sampling of the battery terminal characteristics for CPI does not increment again for a valid charge until
end-of-discharge determination when excessive dis- NAC < 0.94 ∗ LMD. This prevents continuous trickle
charges occur. charging from incrementing CPI if self-discharge decre-
ments NAC. The CPI register increments to 255 with-
FLGS2 Bits out rolling over. When the contents of CPI are incre-
7 6 5 4 3 2 1 0 mented to 64, the capacity inaccurate flag, CI, is as-
serted in the FLGS1 register. The CPI register is reset
- - - - - - - OVLD
whenever an update of the LMD register is performed,
and the CI flag is also cleared.
DR2–0 and OVLD are set based on the measurement of the
voltage at the SR pin relative to VSS. The rate at which Digital Magnitude Filter (DMF)
this measurement is made varies with device activity.
The read-write DMF register (address=0Ah) provides
the system with a means to change the default settings
Program Pin Pull-Down Register (PPD) of the digital magnitude filter. By writing different val-
The read-only PPD register (address=07h) contains some ues into this register, the limits of VSRD and VSRQ can be
of the programming pin information for the bq2014. The adjusted.
segment drivers, SEG1–5 and DONE, have corresponding Note: Care should be taken when writing to this regis-
PPD register locations, PPD1–6. A given location is set if a ter. A VSRD and VSRQ below the specified VOS may ad-
pull-down resistor has been detected on its corresponding versely affect the accuracy of the bq2014. Refer to Table
segment driver. For example, if SEG1 and SEG4 have 4 for recommended settings for the DMF register.
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bq2014
Reset Register (RST) When DISP is tied to VCC, the SEG1–5 outputs are inac-
tive. Note: DISP must be tied to VCC if the LEDs
The reset register (address=39h) provides the means to are not used. When DISP is left floating, the display
perform a software-controlled reset of the device. By becomes active whenever the NAC registers are count-
writing the RST register contents from 00h to 80h, a ing at a rate equivalent to VSRO < -4mV or charge cur-
bq2014 reset is performed. Setting any bit other than rent is detected, VSRO > VSRQ. When pulled low, the seg-
the most-significant bit of the RST register is not al- ment outputs become active immediately. A capacitor
lowed, and results in improper operation of the bq2014. tied to DISP allows the display to remain active for a
short period of time after activation by a push-button
Resetting the bq2014 sets the following: switch.
n LMD = PFC The segment outputs are modulated as two banks of
n CPI, VDQ, NAC, and NACL = 0 three, with segments 1, 3, and 5 alternating with seg-
ments 2 and 4. The segment outputs are modulated at
n CI and BRP = 1 approximately 100Hz, with each segment bank active
for 30% of the period.
Note: Self-discharge is disabled when PROG5 = H.
SEG1 blinks at a 4Hz rate whenever VSB has been de-
Display tected to be below VEDV1 (EDV1 = 1), indicating a low-
battery condition. VSB below VEDVF (EDVF = 1) disables
The bq2014 can directly display capacity information us- the display output.
ing low-power LEDs. If LEDs are used, the program
pins should be resistively tied to VCC or VSS for a pro-
gram high or program low, respectively..
Microregulator
The bq2014 can operate directly from 3 or 4 cells. To facili-
The bq2014 displays the battery charge state in relative tate the power supply requirements of the bq2014, an REF
mode. In relative mode, the battery charge is repre- output is provided to regulate an external low-threshold n-
sented as a percentage of the LMD. Each LED segment FET. A micropower source for the bq2014 can be inexpen-
represents 20% of the LMD. sively built using the FET and an external resistor; see
The capacity display is also adjusted for the present bat- Figure 1.
tery temperature. The temperature adjustment reflects
the available capacity at a given temperature but does
not affect the NAC register. The temperature adjust-
ments are detailed in the TMPGG register description.
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bq2014
Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera-
tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo-
sure to conditions beyond the operational limits for extended periods of time may affect device reliability.
Notes: 1. Default value; value set in DMF register. VOS is affected by PC board layout. Proper layout guide
lines should be followed for optimal performance.
2. To ensure correct threshold determination and proper operation, VCC > VSB + 1.5V
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bq2014
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bq2014
Note: The open-drain DQ pin should be pulled to at least VCC by the host system for proper DQ operation.
DQ may be left floating if the serial interface is not used.
DQ
(R/W "1")
tSTRH
DQ tSTRB
(R/W "0")
tDSU tDH
tDV
tSSU tSH
DQ tSV
(BREAK)
TD201002.eps
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bq2014
.004
L
Notes: Change 1 = Dec. 1994 B “Final” changes from Aug. 1994 A “Preliminary.”
Change 2 = Dec. 1995 C from Dec. 1994 B.
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bq2014
Ordering Information
bq2014
Temperature Range:
blank = Commercial (0 to +70°C)
Package Option:
SN = 16-pin narrow SOIC
Device:
bq2014 Gas Gauge IC
20
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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