NCP81220 D
NCP81220 D
NCP81220 D
Vin
VccCore
Driver
Vin
Driver
Vin
Driver
Vin
Driver
NCP81220 Intel
IMVP8 CPU
Vin
VccGT
Driver
Vin
Driver
SVID
Figure 1. Block Diagram
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26 CSN2A Inverting input to the current−balance amplifier for Phase 2 of the two−phase regulator
27 TSENSEA Temperature sense input for two−phase regulator
28 PWM1A / PWM1 output for two−phase regulator
ICCMAXA During startup, ICCMAX for two−phase regulator is programmed with a pull−down resistor
29 PWM2A / PWM2 output for two−phase regulator
VBOOTA Pin−program for two−phase Vboot.
30 DRON External FET driver enable for discrete driver or ONSemi DrMOS
31 PWM4 / PWM4 output for four−phase regulator /
ROSC Pulldown on this pin programs the operating frequency for both rails
32 PWM3 / PWM3 output for four−phase regulator /
ICCMAX Pulldown on this pin programs ICCMAX for four−phase rail during startup
33 PWM2 / PWM2 output for four−phase regulator /
VBOOT Pin−program for four−phase Vboot.
34 PWM1 / PWM1 output for four−phase regulator /
SV_ADDR Pulldown on this pin configures SVID address
35 TSENSE Temperature sense input for four−phase regulator
36 CSN1 Differential current sense negative for Phase 1 of four−phase rail
37 CSP1 Differential current sense positive for Phase 1 of four−phase rail
38 CSN2 Differential current sense negative for Phase 2 of four−phase rail
39 CSP2 Differential current sense positive for Phase 2 of four−phase rail
40 CSN3 Differential current sense negative for Phase 3 of four−phase rail
41 CSP3 Differential current sense positive for Phase 3 of four−phase rail
42 CSN4 Differential current sense negative for Phase 4 of four−phase rail
43 CSP4 Differential current sense positive for Phase 4 of four−phase rail
44 CSREF Total−current−sense amplifier reference voltage input for four−phase regulator
45 CSSUM Inverting input of total−current−sense amplifier for four−phase regulator
46 ILIM Over−current threshold setting – programmed with a resistor to CSCOMP for four−phase regulator
47 CSCOMP Output of total−current−sense amplifier for four−phase regulator
48 COMP Output of the error amplifier and the inverting inputs of the PWM comparators for four−phase regulator
49 FB Error amplifier voltage feedback for four−phase regulator
50 DIFF Output of the four−phase regulator s differential remote sense amplifier
51 VSP Differential output voltage sense positive for four−phase regulator
52 VSN Differential output voltage sense negative for four−phase regulator
53 Flag GND
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Current Sense Amplifier Gain 0 V < CSPx < 0.1 V 5.7 6.0 6.3 V/V
Multiphase Current Sense Gain CSREF = CSP = 10 mV to 30 mV ±3 %
Matching
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NCP81220
DRON
Output High Voltage Sourcing 500 mA 3.0 − − V
Output Low Voltage Sinking 500 mA − − 0.1 V
Pull Up Resistances 2.0 kW
Rise/Fall Time CL (PCB) = 20 pF, DVo = 10% to 90% − 160 ns
Internal Pull Down Resistance VCC = 0 V 70 kW
IOUT /IOUTA OUTPUT
Input Referred Offset Voltage Ilimit to CSREF −4 +4 mV
Output current max Ilimit sink current 30 mA 285 300 315 mA
Current Gain (Iout current)/(Ilimit Current) 9.5 10 10.5
Rlim = 20 K, Riout = 5 K
DAC = 0.8 V, 1.25 V, 1.52 V
OSCILLATOR
Switching Frequency Range 180 1170 kHz
Switching Frequency Accuracy 180 kHz < Fsw < 1170 kHz −10 − 10 %
PSYS
Input current max rsys = 25 K 100 mA
ADC resolution 8 bit 0.4 mA/Bit
Register update rate 145 ms
OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP)
Over Voltage Threshold During Soft− CSREF Rising 2.5 V
Start
Over Voltage Threshold Above DAC VSP rising 350 400 475 mV
Over Voltage Delay VSP rising to PWMx low 50 ns
Under Voltage Threshold Below VSP falling 350 400 475 mV
DAC−DROOP
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NCP81220
ILIM Threshold Current (OCP shut- Main Rail, RLIM = 20 K (N = number of 10/N mA
down after 50 ms delay) phases in PS0 mode)
ILIM Threshold Current (OCP shut- Auxiliary Rail, Rlim = 20 k 8.0 10 11.0 mA
down after 50 ms delay)
ILIM Threshold Current (immediate Auxiliary Rail, Rlim = 20 k 13 15 16.5 mA
OCP shutdown)
100% Duty Cycle COMP voltage when the PWM outputs re- − 2.5 − V
main HI VRMP = 12.0 V
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Startup Timing
VR_EN
(at the pin)
RESET
TD TF
VR_EN
(internal)
TE
VR_READY
(open drain)
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NCP81220
SCLK SCLK
CPU VR
VR latch CPU latch
send send
SDIO SDIO
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NCP81220
PWM1
o
0
PWM1A
o
45
PWM2
PWM4 4+2 o
o 90
270
PWM2A
o
225
PWM3
180 o
PWM1
PWM2
PWM3
PWM4
PWM1A
PWM2A
The table above shows how to configure the part as either required must have its CSP pin shorted to 5 V. If any more
a 4+2 or a 3+3, however, if an alternative configuration such than 2 phases are required on the GT rail then one of the 3+3
as 2+2 or 3+2 is desired then the phase that is no longer options in the table above must be selected.
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NCP81220
I.e. if a 2+2 configuration is required, you must select a ALERT. The SCLK is unidirectional and generated by the
4+2 configuration from the table above and then disable 2 master. The SDIO is bi−directional, used for transferring
phases from the Core rail by shorting CSP2 and CSP4 to 5 V. data from the CPU to the NCP81220 and from the
If a 2+3 configuration is required, you will select a 3+3 NCP81220 to the CPU. The ALERT is an open drain output
configuration from the table above and disable the third from the NCP81220 to signal to the master that the Status
phase of the Core rail by shorting CSP3 to 5 V. In this Register should be read.
instance PWM4 is used on the GT rail. SCLK, SDIO and ALERT should be pulled high to CPU
I/O voltage Vtt (which is typically 1.0 to 1.1 V) using 55 Ω
Serial VID Interface (SVID) Resistors.
The Serial VID Interface (SVID Interface) is a 3 wire The SVID bus will operate at a max frequency of 43 MHz.
digital interface used to transfer power management VID code change is supported by SVID interface with
information between the CPU (Master) and the NCP81220 three options as below:
(Slave). The 3 wires are clock (SCLK), data (SDIO) and
Serial VID
The NCP81220 supports the Intel serial VID interface. It communicates with the microprocessor through three wires (SCLK,
SDIO, ALERT). The table of supported registers is shown below.
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157.7 990 For the GT rail PWM1A & PWM2A can be disabled by
182.1 1080 connecting CSP1A & CSP2A to 5 V.
249 1170
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NCP81220
Remote Sense Amplifier the voltage drop across the inductor series resistance (DCR).
A high performance high input impedance true Rth is placed near an inductor to sense the temperature of the
differential amplifier is provided to accurately sense the inductor. This allows the filter time constant and gain to be
output voltage of the regulator. The VSP and VSN inputs a function of the Rth NTC resistor and compensate for the
should be connected to the regulator’s output voltage sense change in the DCR with temperature.
points. The remote sense amplifier takes the difference of
the output voltage with the DAC voltage and adds the droop
voltage to
V DIFOUT +
ǒVVSP * VVSNǓ ) ǒ1.3 V * VDACǓ ) ǒVDROOP * VCSREFǓ
This signal then goes through a standard error
compensation network and into the inverting input of the
error amplifier. The non−inverting input of the error
amplifier is connected to the same 1.3 V reference used for
the differential sense amplifier output bias.
RCSN CCSN inductor and should not need to be changed. The NTC
should be placed near the closest inductor. The output
voltage droop should be set with the droop filter divider.
SWNx VOUT
The pole frequency in the CSCOMP filter should be set
DCR LPHASE equal to the zero from the output inductor. This allows the
1 2
circuit to recover the inductor DCR voltage drop current
L PHASE signal. Ccs1 and Ccs2 are in parallel to allow for fine tuning
R CSN + of the time constant using commonly available values. It is
C CSN @ DCR
best to fine tune this filter during transient testing.
Total Current Sense Amplifier DCR@25C
FZ +
The NCP81220 uses a patented approach to sum the phase 2 @ PI @ L Phase
currents into a single temperature compensated total current
signal. This signal is then used to generate the output voltage Programming the Current Limit
droop, total current limit, and the output current monitoring The NCP81220 compares a programmable current−limit
functions. The total current signal is floating with respect to set point to the voltage from the output of the
CSREF. The current signal is the difference between current−summing amplifier. The level of current limit is set
CSCOMP and CSREF. The Ref(n) resistors sum the signals with the resistor from the ILIM pin to CSCOMP. The current
from the output side of the inductors to create a low through the external resistor connected between ILIM and
impedance virtual ground. The amplifier actively filters and CSCOMP is then compared to the internal current limit
gains up the voltage applied across the inductors to recover current ICL. If the current generated through this resistor into
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NCP81220
the ILIM pin (Ilim) exceeds the internal current−limit Programming IOUT
threshold current (ICL), an internal latch−off counter starts, The IOUT pin sources a current in proportion to the
and the controller shuts down if the fault is not removed after ILIMIT sink current. The voltage on the IOUT pin is
50 ms (shut down immediately for 150% load current) after monitored by the internal A/D converter and should be
which the outputs will remain disabled until the Vcc voltage scaled with an external resistor to ground such that a load
or EN is toggled. equal to ICCMAX generates a 2.5 V signal on IOUT. A
The voltage swing of CSCOMP cannot go below ground. pull−up resistor from 5 V VCC can be used to offset the
This limits the voltage drop across the DCR through the IOUT signal positive if needed.
current balance circuitry. An inherent per−phase current 2.5 V @ R LIMIT
limit protects individual phases if one or more phases stop R IOUT +
Rcs2) Rcs1@Rth
functioning because of a faulty component. The Rcs1)Rth @ ǒIout Ǔ
10 @ ICC_MAX @ DCR
over−current limit is programmed by a resistor on the ILIM Rph
pin. The resistor value can be calculated by the following
equations, Programming ICC_MAX
Equation related to the Rilim,: The SVID interface provides the platform ICC_MAX
value at register 21h for. A resistor to ground on the IMAX
I LIM @ DCR @ R CSńR PH
R ILIM + pin programs these registers at the time the part is enabled.
I CL
10 mA is sourced from these pins to generate a voltage on the
Where ICL = 10 mA program resistor. The value of the register is 1 A per LSB and
is set by the equation below. The resistor value should be no
Programming DAC Feed−Forward Filter less than 10 k.
The DAC feed−forward implementation is realized by R @ 10 mA @ 255 A
having a filter on the VSN pin. Programming Rvsn sets the ICC_MAX 21h +
2.5 V
gain of the DAC feed−forward and Cvsn provides the time
constant to cancel the time constant of the system per the Programming DAC Feed−Forward Filter
following equations. Cout is the total output capacitance and The DAC feed−forward implementation is realized by
Rout is the output impedance of the system. having a filter on the VSN pin. Programming Rvsn sets the
gain of the DAC feed−forward and Cvsn provides the time
constant to cancel the time constant of the system per the
following equations. Cout is the total output capacitance and
Rout is the output impedance of the system.
Programming DROOP
The signals CSCOMP and CSREF are differentially Rvsn + Cout @ Rout @ 453.6 10 6
summed with the output voltage feedback to add precision Cvsn + Rout @ Cout
voltage droop to the output voltage. Rvsn
Programming TSENSE
A temperature sense inputs are provided. A precision
current is sourced out the output of the TSENSE pin to
generate a voltage on the temperature sense network. The
voltage on the temperature sense input is sampled by the
internal A/D converter. A 10 k NTC similar to the
TSM0B103H3371RZ should be used. Rcomp1 is mainly
Droop = DCR * (RCS / Rph) used for noise. See the specification table for the thermal
sensing voltage thresholds and source current.
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NCP81220
Vin
Vramp _pp
Comp −IL
Duty
PWM Comparators
The non−inverting input of the comparator for each phase During steady state operation, the duty cycle is centered
is connected to the summed output of the error amplifier on the valley of the sawtooth ramp waveform. The steady
(COMP) and each phase current (I*DCR*Phase Balance state duty cycle is still calculated by approximately
Gain Factor). The inverting input is connected to the Vout/Vin. During a transient event, the controller will
oscillator ramp voltage with a 1.3 V offset. The operating operate in a hysteretic mode with the duty cycles pull in for
input voltage range of the comparators is from 0 V to 3.0 V all phases as the error amp signal increases with respect to
and the output of the comparator generates the PWM output. all the ramps.
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NCP81220
Protection Features
Soft Start
Soft start is implemented internally. A digital counter the PWMs will be set to 2.0 V MID state to indicate that the
steps the DAC up from zero to the target voltage based on the drivers should be in diode mode. DRON will then be
predetermined rate in the spec table. The PWM signals will asserted. As the DAC ramps the PWM outputs will begin to
start out open with a test current to collect data on phase fire. Each phase will move out of the MID state when the
count and for setting internal registers. After the first PWM pulse is produced. When the controller is
configuration data is collected, if the controller is enabled disabled the PWM signal will return to the MID state.
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NCP81220
PACKAGE DIMENSIONS
ÉÉÉ
TERMINAL AND IS MEASURED BETWEEN
PIN ONE L1 0.15 AND 0.30mm FROM TERMINAL TIP
ÉÉÉ
LOCATION 4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
ÉÉÉ
DETAIL A MILLIMETERS
E ALTERNATE TERMINAL DIM MIN MAX
CONSTRUCTIONS A 0.80 1.00
A1 0.00 0.05
ÉÉÉ
A3 0.20 REF
0.10 C EXPOSED Cu MOLD CMPD b 0.15 0.25
ÉÉÉ
D 6.00 BSC
D2 4.60 4.80
0.10 C TOP VIEW E 6.00 BSC
E2 4.60 4.80
A
DETAIL B (A3) DETAIL B
e 0.40 BSC
0.10 C K 0.30 REF
ALTERNATE L 0.25 0.45
CONSTRUCTION
L1 0.00 0.15
L2 0.15 REF
0.08 C A1
NOTE 4 SIDE VIEW SEATING
C PLANE
D2 K
DETAIL C L2
14 DETAIL A L2
27 DETAIL C
8 PLACES
SOLDERING FOOTPRINT*
E2
6.40 52X
52X L 4.80 0.63
1
52 40
52X b
e 0.07 C A B
BOTTOM VIEW 0.05 C NOTE 3
4.80 6.40
0.11
0.49
PKG DETAIL D
OUTLINE 8 PLACES
52X DETAIL D
0.40
PITCH 0.25
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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