HI-2579, HI-2581

3.3V MIL-STD-1553/1760 Dual Transceiver

February, 2019 with Low Profile Integrated Transformers
GENERAL DESCRIPTION
The HI-2579 / HI-2581 are low power CMOS dual
transceivers with integrated transformers designed
to meet the requirements of the MIL-STD-1553 /
MIL-STD-1760 specifications. The dual transceivers
with integrated transformers provide a low profile single
part solution for interfacing a protocol IC or FPGA to a
dual redundant MIL-STD-1553 bus.

The transmitter section of each bus takes complementary

CMOS / TTL Manchester II bi-phase data and converts it
to differential voltages suitable for driving the integrated
isolation transformer. Separate transmitter inhibit control
signals are provided for each transmitter.

The receiver section of the each bus converts the 1553

bus differential data to complementary CMOS / TTL data
PIN CONFIGURATIONS (TOP)
suitable for inputting to a Manchester decoder. Each
receiver has a separate enable input which can be used
BUSA - 1 24 - DNC
to force both receiver outputs to logic “0” (HI-2579) or BUSA - 2 23 - DNC
logic 1 (HI-2581). TXA - 3 22 - TXINHA
o TXA - 4 HI-2579CGIF 21 - RXA
The family of parts are available in Industrial -40 C to
o o o VDDA - 5 HI-2579CGTF 20 - RXA
+85 C, or Extended, -55 C to +125 C temperature RXENA - 6 19 - TXB
ranges. GNDA - 7 HI-2581CGIF 18 - TXB
VDDB - 8 HI-2581CGTF 17 - TXINHB
RXENB - 9 16 - RXB
FEATURES GNDB - 10 15 - RXB
DNC - 11 14 - BUSB
• Dual-redundant MIL-STD-1553 transceivers with DNC - 12 13 - BUSB
integrated transformers
• Small footprint and low profile package DNC = Do Not Connect

• Compliant to MIL-STD-1553A and B,

BUSA - 1 24 - DNC
MIL-STD-1760, ARINC 708A BUSA - 2 23 - DNC
• 3.3V single supply operation TXA - 3 22 - TXINHA
TXA - 4 HI-2579LCIF 21 - RXA
• Less than 1.0W maximum power dissipation VDDA - 5 HI-2579LCTF 20 - RXA
• Industrial and extended temperature ranges RXENA - 6 19 - TXB
GNDA - 7 HI-2581LCIF 18 - TXB
VDDB - 8 HI-2581LCTF 17 - TXINHB
RXENB - 9 16 - RXB
GNDB - 10 15 - RXB
DNC - 11 14 - BUSB
DNC - 12 13 - BUSB

DNC = Do Not Connect

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DS2579 Rev. G 1 02/19
 HI-2579, HI-2581

BLOCK DIAGRAM
VDD

Each Bus
Isolation
Transformer
TXA/B BUSA/B
Transmit Slope Not Used
Logic Control
TXA/B Not Used
BUSA/B
TXINHA/B

RXA/B
Receive Input
Logic Filter
RXA/B
Comparator
RXENA/B

GND

Figure 1.  Block Diagram

TXA/B

TXA/B

BUSA/B - BUSA/B

Vin
(Line to Line)

tDR tDR tDR tDR

RXA/B (HI-2579)
tRG tRG

RXA/B (HI-2579)

RXA/B (HI-2581)
tRG tRG

RXA/B (HI-2581)

Figure 2.  Example Waveforms

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PIN DESCRIPTIONS
Table 1.  Pin Descriptions

Pin Symbol Function Description

MIL-STD-1553 Bus A driver, negative signal (Transformer coupled or direct

1 BUSA Analog O/P
coupled bus connections)

MIL-STD-1553 Bus A driver, positive signal (Transformer coupled or direct

2 BUSA Analog O/P
coupled bus connections)

3 TXA Digital I/P Transmitter A digital data input, non-inverted

4 TXA Digital I/P Transmitter A digital data input, inverted

5 VDDA Power Transceiver A 3.3V supply

Receiver A enable. If low, forces both RXA and RXA low (HI-2579) or High
6 RXENA Digital I/P
(HI-2581)
7 GNDA Power Transceiver A ground connection

8 VDDB Power Transceiver B 3.3V supply

Receiver B enable. If low, forces both RXB and RXB low (HI-2579) or High
9 RXENB Digital I/P
(HI-2581)

10 GNDB Power Transceiver B ground connection

11 DNC − Not Used. Do Not Connect.

12 DNC − Not Used. Do Not Connect.

MIL-STD-1553 Bus B driver, positive signal (Transformer coupled or direct

13 BUSB Analog O/P
coupled bus connections)

MIL-STD-1553 Bus B driver, negative signal (Transformer coupled or direct

14 BUSB Analog O/P
coupled bus connections)

15 RXB Digital O/P Receiver B output, inverted

16 RXB Digital O/P Receiver B output, non-inverted

17 TXINHB Digital I/P Transmit inhibit, Bus B. If high BUSB, BUSB outputs are disabled

18 TXB Digital I/P Transmitter B digital data input, non-inverted

19 TXB Digital I/P Transmitter B digital data input, inverted

20 RXA Digital O/P Receiver A output, inverted

21 RXA Digital O/P Receiver A output, non-inverted

22 TXINHA Digital I/P Transmit inhibit, Bus A. If high BUSA, BUSA outputs are disabled

23 DNC − Not Used. Do Not Connect.

24 DNC − Not Used. Do Not Connect.

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FUNCTIONAL DESCRIPTION threshold comparator that produces CMOS data at the

RXA/B and RXA/B output pins. When the MIL-STD-1553
The HI-2579 family of data bus transceivers contains bus is idle and RXENA or RXENB are high, RXA/B will
differential voltage source drivers, differential receivers be logic “0” on HI-2579 and logic “1” on HI-2581.
and integrated transformers. They are intended for
applications using a MIL-STD-1553 A/B data bus. Each set of receiver outputs can also be independently
forced to the bus idle state (logic “0” on HI-2579 or logic
“1” on HI-2581) by setting RXENA or RXENB low.
Transmitter
Data is input to the device’s transmitter section from MIL-STD-1553 Bus Interface
the complementary CMOS inputs TXA/B and TXA/B.
The transmitter accepts Manchester II bi-phase data There are two ways of connecting to the MIL-STD-1553
and converts it to differential voltages which drive the bus, using a direct coupled interface or a transformer
internal transformers on BUSA/B and BUSA/B. The coupled interface (see Figure 3).
transformer outputs are either direct or transformer
coupled to the MIL-STD-1553 data bus. Both coupling A direct coupled interface uses the internal 1:2.5 ratio
methods produce a nominal voltage on the main bus of isolation transformer and two 55Ω isolation resistors
7.5 volts peak to peak. between the transformer and the bus.

The transmitter is automatically inhibited and placed in In a transformer coupled interface, the transceiver is
the high impedance state when both TXA/B and TXA/B connected to the internal 1:2.5 isolation transformer
are either at a logic “1” or logic “0” simultaneously. A logic which in turn is connected to a 1:1.4 coupling transformer.
“1” applied to the TXINHA/B input forces the transmitter The transformer coupled method also requires two
to the high impedance state, regardless of the state of coupling resistors equal to 75% of the bus characteristic
TXA/B and TXA/B. impedance (Zo) between the coupling transformer and
the bus. The coupling transformer and coupling resistors
are commonly integrated in a single device known as a
Receiver stub coupler.

The receiver accepts bi-phase differential data from Figure 4 and Figure 5 show test circuits for measuring
the MIL-STD-1553 bus through the same direct or electrical characteristics of both direct and transformer
transformer coupled interface as the transmitter. The coupled interfaces respectively (see “Electrical
receiver’s differential input stage includes a filter and Characteristics” on the following pages) .

ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING

Supply voltage (VDD)
CONDITIONS
-0.3 V to +5 V
Logic input voltage range -0.3 V DC to +3.6 V Supply Voltage VDD 3.3V ± 5%
Receiver differential voltage 50 Vp-p Temperature Range
Driver peak output current +1.0 A Industrial Screening
o
-40 C to +85 C
o

Power dissipation at 25°C 1.0 W Hi-Temp Screening

o
-55 C to +125 C
o
o
Solder Temperature 245 C max.
Junction Temperature 175 C
o NOTE: Stresses above absolute maximum ratings or outside
o o recommended operating conditions may cause permanent
Storage Temperature -65 C to +150 C damage to the device. These are stress ratings only. Operation
at the limits is not recommended.

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ELECTRICAL CHARACTERISTICS

Table 2.  DC Electrical Characteristics

VDD = +3.3V, GND = 0V, TA = Operating Temperature Range (unless otherwise stated)
Parameter Symbol Test Conditions Min Typ Max Units

Operating Voltage VDD 3.15 3.3 3.45 V

ICC1 Not Transmitting 4 17 mA

ICC2 Transmit one bus @ 50% duty cycle 225 320 mA

Total Supply Current
Transmit one bus @ 100% duty
ICC3 425 640 mA
cycle

PD1 Not Transmitting 0.06 W

Power Dissipation
Transmit one bus @ 100% duty
PD2 0.5 1.0 W
cycle

Min. Input Voltage (HI) VIH Digital Inputs 2.0 V

Max. Input Voltage (LO) VIL Digital Inputs 30% VDD

Min. Input Current (HI) IIH Digital Inputs 20 μA

Max. Input Current (LO) IIL Digital Inputs -20 μA

Min. Output Voltage (HI) VOH IOUT = -1.0mA, Digital Outputs 90% VDD

Max. Output Voltage (LO) VOL IOUT = +1.0mA, Digital Outputs 10% VDD

RECEIVER (Measured at Point “AD” in Figure 4 unless otherwise specified)

Input Resistance RIN Differential 2 kΩ

Input Capacitance CIN Differential 5 pF

Common Mode Rejection Ratio CMRR 45 dB

Input Common Mode Voltage VICM -10.0 +10.0 V-pk

1MHz Sine Wave (measured at

Detect VTHD point “AD” in Figure 4) 1.15 Vp-p
Threshold Voltage -
Direct Coupled RXA/B, RXA/B pulse width > 70 ns

No Detect VTHND No pulse at RXA/B, RXA/B 0.28 Vp-p

1MHz Sine Wave (measured at

Detect VTHD point “AT” in Figure 5) 0.86 Vp-p
Threshold Voltage -
Transformer Coupled RXA/B, RXA/B pulse width > 70 ns

No Detect VTHND No pulse at RXA/B, RXA/B 0.20 Vp-p

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Parameter Symbol Test Conditions Min Typ Max Units

TRANSMITTER (Measured at Point “AD” in Figure 4 unless otherwise specified)

Direct 35Ω Load (measured at

VOUT 6.1 9.0 Vp-p
Coupled point “AD” in Figure 4)
Output Voltage
Transformer 70Ω Load (measured at
VOUT 20.0 27.0 Vp-p
Coupled point “AT” in Figure 5)

Output Noise VON Differential, Inhibited 10 mVp-p

Direct 35Ω Load (measured at

VDYN -90 +90 mV
Coupled point “AD” in Figure 4)
Output Dynamic Offset Voltage
Transformer 70Ω Load (measured at
VDYN -250 +250 mV
Coupled point “AT” in Figure 5)

Output Capacitance COUT 1MHz Sine Wave 15 pF

Table 3.  AC Electrical Characteristics

VDD = +3.3V, GND = 0V, TA = Operating Temperature Range (unless otherwise stated)

Parameter Symbol Test Conditions Min Typ Max Units

RECEIVER (Measured at Point “AT” in Figure 5)

From input zero crossing to 450

Receiver Delay tDR ns
RXA/B or RXA/B Note 3

Spacing between RXA/B 90 365

Receiver Gap Time tRG ns
and RXA/B pulses Note 1 Note 2

From RXENA/B rising or

Receiver Enable Delay tREN falling edge to RXA/B or 40 ns
RXA/B

TRANSMITTER (Measured at Point “AD” in Figure 4)

TXA/B, TXA/B to BUSA/B,

Driver Delay tDT 150 ns
BUSA/B

Rise Time tr 35Ω Load 100 300 ns

Fall Time tf 35Ω Load 100 300 ns

tDI-H Inhibited Output 100 ns

Inhibit Delay
tDI-L Active Output 150 ns

Note 1. Measured using a 1 MHz sinusoid, 20 V peak to peak, line to line at point “AT” (Guaranteed but not tested).
Note 2. Measured using a 1 MHz sinusoid, 860 mV peak to peak, line to line at point “AT” (100% tested).
Note 3. Measured using a 1 MHz sinusoid, 860 mV peak to peak, line to line at point “AT”. Measured from input zero crossing point.

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MIL-STD-1553
BUS A
(Direct Coupled)

Isolation
Transformer 55Ω BUSA

Transceiver A
55Ω BUSA
1:2.5 MIL-STD-1553
BUS B
MIL-STD-1553 (Transformer Coupled)
Stub Coupler
Isolation
Transformer BUSB 52.5Ω

Transceiver B
BUSB
52.5Ω
1:2.5 1:1.4

HI-2579

Figure 3.  Bus Connections Example using HI-2579

VDD
Each Bus

Isolation
TXA/B Transformer 55Ω BUSA/B

TXA/B MIL-STD-1553
RXA/B
Transceiver 35Ω

RXA/B 55Ω BUSA/B

HI-2579 Point
“AD”

GND

Figure 4.  Direct Coupled Test Circuit

VDD
Each Bus

Isolation
TXA/B Transformer BUSA/B

TXA/B MIL-STD-1553
Transceiver 70Ω
RXA/B

RXA/B BUSA/B

HI-2579 Point
“AT”

GND

Figure 5.  Transformer Coupled Test Circuit

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ORDERING INFORMATION

HI - 25xx CG x F Ceramic Substrate

PART NUMBER LEAD FINISH

F Pb-free, RoHS compliant

LEAD
PART NUMBER TEMPERATURE RANGE FLOW
FINISH

I -40oC to +85oC I Gold

o o
T -55 C to +125 C T Gold

RXENA = 0 RXENB = 0
PART NUMBER
RXA RXA RXB RXB

2579 0 0 0 0

2581 1 1 1 1

HI - 25xx LC x F High TCE Substrate

PART NUMBER LEAD FINISH

F Pb-free, RoHS compliant

LEAD
PART NUMBER TEMPERATURE RANGE FLOW
FINISH

I -40oC to +85oC I Gold

T -55oC to +125oC T Gold

RXENA = 0 RXENB = 0
PART NUMBER
RXA RXA RXB RXB

2579 0 0 0 0

2581 1 1 1 1

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REVISION HISTORY
Revision Date Description of Change

DS2579, Rev. New 10/8/12 Initial Release

Correct Note 1 on package dimensions to state that the Heatsink pad is connected
Rev. A 5/23/13
internally to ground.

Add “CG” low profile package option.

Make minor clarifications and correct typographical errors in “DC Electrical
Rev. B 1/13/15 Characteristics” and “AC Electrical Characteristics”.
Corrected Receiver Threshold Voltage for Direct Coupled connection from 0.86V to
1.15V in “DC Electrical Characteristics”.

Clarify dimensions on package bottom-side test pads. No change in physical

Rev. C 3/5/15 dimensions.
Remove “CL” package option.

Correct typos in Pin Descriptions table. Correct bus connections in Figure 3 and
Rev. D 3/27/15
Figure 4.
Rev. E 07/29/16 “Table 2. DC Electrical Characteristics”: change VIH to 2.0V min.

Clarify labeling of “keep out” zones and heatsink on package drawing. Update
Rev. F 07/28/17
package photo.
Rev. G 02/22/19 Add “LC” high TCE substrate package variant.

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PACKAGE DIMENSIONS - “CG” CERAMIC SUBSTRATE

Top View Dimensions in inches (mm)

.845 ± .015
(21.46 ± .38)
.800 ± .015
(20.32 ± .38)
(12.32 ± .38)

(11.18 ± .38)
.485 ± .015

.440 ± .015

METAL COVER

PIN 1 INDEX
IN TOPMARK

Side View
Metal Cover .096 ± .008
(2.43 ± .20)

(4.22 ± .38)
.166 ± .015

OVERALL
.004

METALLIZATION
.070 ± .007
(1.78 ± .18)
CERAMIC

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PACKAGE DIMENSIONS - “CG” CERAMIC SUBSTRATE

Bottom View Dimensions in inches (mm)

.660 ± .007
(16.76 ± .18)
.218
.060 TYP.
(5.54)
(1.52)

.044 SQ.
6X (DNC)
.025 (1.12 SQ.)
24X R.017
(.64)
Corners
(R.43)
Heatsink
(4.65)
.183

(2.03)
.080
2X
24X
PIN 1 INDEX
R.008
(1.27)
23X .050

(2.03)
.080
(R.20) .510 ± .007
(12.95 ± .18)
.600 ± .007
(15.24 ± .18)

Notes:
1. Heatsink pad is internally connected to device GND pins. Connection to external GND for heat extraction is not necessary.
2. The “keep out” zones (shaded grey) enclose test pads for the transformer primary windings. DO NOT CONNECT (DNC).
3. Routing traces under the six test pads is not recommended.

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PACKAGE DIMENSIONS - “LC” HIGH TCE SUBSTRATE

Top View Dimensions in inches (mm)

.800 ± .015
(20.32 ± .38)
(11.18 ± .38)
.440 ± .015

Overmold

PIN 1 INDEX
IN TOPMARK

Side View
.100 ± .002
(2.54 ± .05)

(4.17 ± .38)
.164 ± .015
Overmold

OVERALL
High TCE Ceramic Substrate

.064 ± .007
(1.63 ± .18)
CERAMIC

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PACKAGE DIMENSIONS - “LC” HIGH TCE SUBSTRATE

Bottom View Dimensions in inches (mm)

.660 ± .007
(16.76 ± .18)
.218
.060 TYP. .006
(5.54)
(1.52) (0.15)

.044 SQ.
6X (DNC)
.025 (1.12 SQ.)
24X R.017
(.64)
Corners
(R.43)
Heatsink
(4.65)
.183

(2.03)
.080
2X
24X
.006 PIN 1 INDEX
R.008
(1.27)
23X .050

(2.03)
.080
(0.15) (R.20) .510 ± .007
(12.95 ± .18)
.600 ± .007
(15.24 ± .18)

Notes:
4. Heatsink pad is internally connected to device GND pins. Connection to external GND for heat extraction is not necessary.
5. The “keep out” zones (shaded grey) enclose test pads for the transformer primary windings. DO NOT CONNECT (DNC).
6. Routing traces under the six test pads is not recommended.

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