665 LNA-Design-2006
665 LNA-Design-2006
665 LNA-Design-2006
Edgar Sánchez-Sinencio
Part of the material here provided is based on Dr. Chunyu Xin’s dissertation
Ideal characteristics of LNA in Receivers
min F
Large voltage gain to reduce Ftot
Handling large signals without significant distortion
must present 50 ohms to the input source
For NB the impedance matching and power gain are usually optimized
at one frequency. The output load stage and the input matching usually
involve LC networks.
For wide band LNA the input matching stage and load are
optimized for a frequency band, thus the input matching and load
impedance behave as low-Q ( wide bandwidth) filters
1 − Γs 1 − ΓL
2 2
For unilateral device
GT =
2
s21 i.e. S12~0
1 − s11Γs 1 − s22 ΓL
2 2
BS = − Bc = Bopt
Gu
GS = + GC = Gopt
2
Gn
Fmin = 1 + 2 Rn [Gopt + GC ]
Detail NF expressions are given in the next pages.
i +Y v
2
N
F = o ,total = 1 + n 2 s n
N o ,source ins
in = ic + iu ; ic = Yc vc
vn = vc + vu
F =1+ 2
=1+
ins ins2
in2 2 vc
2
vu2
+ Yc + Ys +
2
Ys
F = 1 + 4kTB 4kTB 4kTB
ins2
4kTB
G + Yc + Ys Rc + Ru Ys G + Yc + Ys Rn
2 2 2
F =1+ u =1+ u
Gs Gs
where
iu2 vc2
Gu = , Rc =
4kTB 4kTB
vu2 ins2
Ru = , Gs =
4kTB 4kTB
and
vn2
Rn =
4kTB
F =1+
[ 2 2
]
Gu + (Gc + Gs ) + (Bc + Bs ) Rc + (Gs2 + BS2 )Ru
Gs
Optimal source admittance :
Now if
∂F ∂F
= 0 and =0
∂Gs ∂Bs
Bopt = − Bc = Bs
Gu
Gopt = Gs = + Gc2
Rn
then
⎡⎛ G ⎞
12
⎤
Fmin = 1 + 2 Rn [Gopt + Gc ] = 1 + 2 Rn ⎢⎜⎜ u
+ Gc ⎟⎟ + Gc ⎥
2
⎣⎢⎝ n ⎠ ⎥⎦
R
For the MOSFET noise model, we have to take into account two sources.
2 4kTγg do B
i 2
nd = 4kTγg do B ; v nd = ; γ = 2 3 for saturation and long channels
g m2
2 ω2C gs
i ng = 4kTγg g B ; g g =
5 g do
Correlation coefficient
*
ing ind
c=
[i 2
ng
2
⋅ i nd ]
12
vn2 γg
Rn = = 2do
4kTB g m
Gu =
(
δω2C gs2 1 − c
2
) ; ωT ≅
gm
5 g go cgs
Bopt = − Bc
Yopt = Gopt + jBopt = Gopt − jBc
Gopt =
Gu
Rn
+ Gc2 = αωC gs
δ
5γ
1− c
2
( )
Fmin = 1 + 2 Rn [G opt +Gc ] ≅ 1 +
2ω
5ωT
(
γδ 1 − c
2
)
Analog and Mixed-Signal Center, TAMU 15
LNA Metrics: Non-linearity model
f1 f 2
f1 f 2 f1+f2
f2-f1 2f1-f2 2f2-f1
2f1 2f2
In-band blocker
Output spectrum with two tone input -23dBm
Wanted Signal
-102dBm
Usually distortion term: 2f1-f2, 2f2-f1
fall in band. This is characterized by 3rd IM3
order non-linearity. f=2f1-f2
Large in-band blocker can desensitize
the circuit. It is measured by 1-dB f 1 f2
compression point.
l
ta
en
IIP3~ -10dBm~8dBm
am
nd
Fu
IM3 IM2
Pin(dBm)
IIP3 IIP2
VDD
ZL ZL
OUTPUT
OUTPUT
VBB VDD RL
M2
Rf
VBB
OUTPUT
VBB
INPUT RL
M1
M1 Lg
INPUT
Rs
M1 INPUT
INPUT OUTPUT C1
R1
Ls
1
Z in = Rs Z in =
g m1 Rf
Z in ≈
Z in = jω (Lg + Ls ) +
1 g
4γ R + m Ls
F ≥ 2+
1 γ 1+ L jωC gs C gs
α g m1 Rs F ≥ 1+ R1
α
NF: > 6dB 4.8dB Moderate < 2dB
Z in = jω (Lg + Ls ) +
1 g
+ m Ls ZL
jωC gs C gs OUTPUT
VBB
1 g
ωo = ωT = m
(Lg + Ls )Cgs C gs
Lg
Z o = ωT Ls
INPUT
Cgs
Io
Lg Vin Lg Io
1 1
(LG + LS )ωo = ; ωo2 =
ωoC gs (LG + LS )Cgs
and
g m LS
Rs =
C gs
which implies that :
1
LG = 2 − LS
ωoC gs
RL Rg γ χ ⎛ ωo ⎞
F = 1+ + + ⎜⎜ ⎟⎟ Lg RLg
Rs Rs α QL ⎝ ωT ⎠
ωo (Ls + Lg )
Cgs
1
QL = =
Rs ωo Rs C gs Ls
δα 2 δα 2
χ = 1 + 2 c QL
5γ
+
5γ
(
1 + QL2 )
ZIN RLs
Rn 2
F = Fmin + Ys − Yopt
Gs
IIP3 (dBm)
V 2
=
4 Veff
(2 + θVeff )(1 + θVeff ) > 8 Veff 20
3 θ 3 θ
IIP 3, strong , MOS
1 16
Veff = VGS − Vth θ=
Esat L 12
IIP3 independent of W 8
4
3
16 PD2 ⎛ 1⎞
( )
0
V 2
(V ) =
2
2 + ρ ⎜⎜1 + ⎟⎟
3 Po θ ⎝ ρ⎠
IIP 3, LNA 2 2
-4
-8
3 vsat Esat
ρ = θVeff Po = VDD 0.4 0.5 0.6 0.7 0.8 0.9 1
2 ωo Rs VGS
MOS transistor’s IIP3 v.s. gate drive voltage
Esat ~ 1V/um L~0.35um-0.18um
Single-ended
Differential
9 reject common mode noise 9 compact layout size
and interferer 9 less power for same NF
8 double area and current and linearity
Lg Lg Lg
M1 M1 M1
C1 C1 C1
Ls Ls Ls
Zin,com
C2
2C2
For passive termination, the real part of the source impedance will
always be positive. IF Rin,com happens to be negative and cancel the real
part of source impedance, oscillation MAY occur.
When design differential LNA, not only pay attention to differential
operation, but also check common-mode stability!
LSP LD
Vo
nMOS-pMOS shunt input
VBB Current reuse to save power
VIN
Larger area due to two degeneration
inductor if implemented on chip
NF: 2dB, Power gain: 17.5dB, IIP3: -
LSN
6dBm, Id: 8mA from 2.7V power supply
1.6
gm 1.2
0.8
g do 1.0
0.6
gm 0.8
Vgs − Vth
0.4 W 0.6
0.4
0.2
0.2
0.0 0.0
0 60 120 180 240 300 360 420 480 540 600
Current density (µA/µm)
Insights:
50 1.5
fT
40 1.3
C gs W 1.2
35
1.1
30
1.0
25
0.9
20 0.8
15 0.7
10 0.6
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Gate overdrive voltage (V)
Insights:
13 47µA/µm
⎛ ω0 ⎞
Noise factor scaling coefficient
12
F = 1 + κ nf ⎜⎜ ⎟⎟
⎝ ωT
11
10
88µA/µm ⎠
9 135µA/µm
1
8 Q=
7
184µA/µm 2 Rsω0C gs
6 300µA/µm
4
3
2-D plots for
1 2 3 4 5 6 7 8 design reference
Quality factor
Insights:
Design trade-offs
Iden↑- F↓
Q↑- F↑
For large Iden ( 300 µA/µm) there is an optimal value
of Q --- maybe too large for a practical design
10
8
6
4
2
0
-2
0 0.1 0.2 0.3 0.4 0.5
Gate overdrive voltage (V)
Insights:
MOS transistor IIP3 only, when embedded into actual circuit:
Input Q will degrade IIP3
Non-linear memory effect will degrade IIP3
Output non-linearity will degrade IIP3
IIP3 is a very weak function of device size
Generally, large overdrive means large IIP3
But the relationship between IIP3 and gate overdrive is not monotonic
There is a local maxima around 0.1V overdrive
40 1.3
= (F − 1) = 7.5
fo
κ nf
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Gate overdrive voltage (V)
fT
Small current budget ( < 10mA )
does not allow large gate over drive :
0.2 V ~ 0.4 V C gs W = 1.3 fF / µm
fT ~ 40 GHz
1.6 14
IIP3 (dBm)
0.8 gm 10
g do 1.0 8
0.6
gm 0.8 6
Vgs − Vth
W 0.6
0.4 4
0.4 2
0.2
0.2 0
0.0 0.0 -2
0 60 120 180 240 300 360 420 480 540 600
Current density (µA/µm)
0 0.1 0.2 0.3 0.4 0.5
Gate overdrive voltage (V)
13 47µA /µm
Now we can do calculations:
Noise factor scaling coefficient
12
11
88µA/µm
10
1
135µA/µm
C gs =
9
~ 166 fF
2QRsωo
8
184µA /µm
7
6 300µA /µm
4
3
166 fF
1 2 3 4 5 6 7 8
W= = 128µm
1.3 fF / µm
Quality factor
⎛ ωT ⎞ RL
Rs AV = j ⎜⎜ ⎟⎟
Ls = ≈ 0.2nH ⎝ ωo ⎠ Rs
ωT
1
Lg = 2 − Ls ≈ 26nH ωo
ωo C gs RL = AV Rs ≈ 30Ω
ωT
15.0 0.86
While pure CMOS process has higher level system integration and lower cost which in some
cost-sensitive designs will out run BiCMOS process.
1
IIP3 =
6 Re[Z1 (ω )]⋅ H (ω ) ⋅ A1 (ω ) ⋅ ε (∆ω ,2ω )
3
V. Aparin, P. Gazzerro, Z. Jianjun, S. Bo, S. Szabo, E. Zeisel, T. Segoria, S. Ciccarelli, C. Persico, C. Narathong, R. Sridhara, “A
highly-integrated tri-band/quadmode SiGe BiCMOS RF-to-baseband receiver for wireless CDMA/WCDMA/AMPS applications
with GPS capability,” 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, pp.234-5
ZL
OUTPUT
RL
VBB VDD
M2 Rf OUTPUT
VBB
INPUT RL
M1 M1
INPUT
Rs
INPUT M1 OUTPUT R1
0.25um CMOS
NF: 2.4dB
-3dB BW: 2M-1.6GHz
IIP3: 0dBm
Voltage Gain: 13.7dB
F. Bruccoleri, E.A.M. Klumperink, B. Nauta, “Noise Cancelling in Widband CMOS LNAs,” ISSCC 2002 Session 24.6
Z o (O h m s)
100
50
14µ
90
40
80 30
70 20
60
4 9 14 19 24 29
4 8 12 16 20 24 28 Width of signal line (M1)
Line spacing (µ m)
ld 2 ld 2
T
Z d Z dL
lg 2
Input
xg lg lg 2
Zs 0
Z gT
-20
7
S22
-25 5
-30
1 3 5 7 9 11 13 15 17 19 21 23 25 27 3
Frequency (GHz) 2 4 6 8 10 12 14 16 18 20 22 24 26
Frequency (GHz)
[1] A. Bevilacqua and A. M. Niknejad, “An Ultra-Wideband CMOS LNA for 3.1 to 10.6GHz Wireless Receivers”, ISSCC 2004.
[2] A. Ismail and A. Abidi, “A 3 to 10GHz LNA using a Wideband LC-ladder Matching Network”, ISSCC 2004
L1
Step 1: Series inductance makes the S11
C1 RB RB
Step2 VB
Rd C2
Ld
Cc RFOUT
Quarter wave
M2
L3
transmission line
L2
Cc
M1
RFIN
L1
C1 RB
Bondwire
VB
M5 M7
Cascoded BJT: better matching Bond wire
Cm M9
M1 M2
Noise figure: 1.6dB Vin- LNA_bypass
Rb Rb
LNA bypass switches and attenuator
Rb Ls Ls
Power/Voltage gain: 15dB Rb
Vbb
M3 M4
NMOS attenuator for low gain(-15dB)
Symmetrical layout
3nH
Deep trench lattice under spiral Gain S.W.
inductor
Inductors are placed far apart
580um
to avoid coupling (~200um) Q1, Q2
G S G S G
570um
S-parameter network
analyzer (HP 8719ES)
S11 better than -11dB
RF IN
IF OUT I&Q
IIP3=-13dBm
40
20
Output (dBm)
Testing board Spectrum 0
Analyzer -20
-40
-60
RF IN
-80
-50 -45 -40 -35 -30 -25 -20 -15 -10
60
IIP2=10dBm
40
Output (dBm)
20
IF OUT I&Q
-20
-40
-60