LNA
LNA
LNA
What is an LNA?
Amplifier S matrix:
s11 s21 S = [ ] s s 12 22
S
s12 s21 L 1 s22 L
in = s11 +
LNA Requirements
Gain(10-20dB)
to amplify the received signal; to reduce the input referred noise of the subsequent stages
Good linearity
Low noise
Input matching
Defines small signal amplification capability of LNA For IC implementation, LNA input is interfaced off-chip and usually matched to specific impedance (50 or 75). Its output is not necessary matched if directly drive the on-chip block such as mixer. This is characterized by voltage gain or transducer power gain by knowing the load impedance level. Transducer power gain: Power delivered to the load divided by power available from source. 2 2
GT = 1 S 1 s11 S
2
s21
1 L
1 s22 L
f 1- f 2
2 f 1- f 2
2 f 2- f 1 2f1
f 1+ f 2 2f2 f
f 1 f2
2f 2 f 1
in-band signal
Yt = a0 + a1 X t + a2 X t 2 + a3 X t 3
characterized by 3rd order non-linearity. Large in-band blocker can desensitize the circuit. It is measured by 1-dB compression point.
Analog and Mixed-Signal Center, TAMU 5
Noise factor is defined by the ratio of output SNR and input SNR. Noise figure is the dB form of noise factor. Noise figure shows the degradation of signals SNR due to the circuits that the signal passes.
LNAs noise factor directly appears in the total noise factor of the system.
gm
T 1 Gm ( ) = j Rs + Rg
F=
2 g
2 io ,T
2 o
2 io ,T
G v
2 s
2 2 m s
= 1+
2 vg
v
2 d
2 s
2 id
G v
2 2 m s
2 gm Rg 2 + F = 1+ ( Rs + Rg ) Rs Rs T 1+ + g m Rs Rs T Rg
2
This expression contains both the channel noise and the gate induced noise 1 is a good approximation Rg = R poly +
5gm
Analog and Mixed-Signal Center, TAMU 10
Rs ,opt
T = Rs =
Rg gm
Fmin
= 1 + 2 g m Rg T
Analog and Mixed-Signal Center, TAMU 11
F vs. Rs
For an LNA operating at 5.2GHz in 0.18 m CMOS process, according to experience and published literatures, we can choose Rg = 2, = 3, = 0.75, T = 2*56GHz, gm = 50mA/V and plot F vs. Rs:
Rg
2
+ F = 1+ g m Rs Rs T
12
Find Rs ,opt for a typical amplifier. Assume fT = 75GHz f = 5GHz , ( ) = 2 , R poly is minimized by proper layout, thus intrinsic gate resistance is given by: 1 1 Rg = R poly + 5gm 5gm
Rg 10 = 0.1 g m = = 40mS Rs ,opt 119, Fmin = 1.08 5Rs Rs
In practice, itll be difficult to get such a low Noise figure and get useful gain with the simple common source due to the bad power match Conflict of minimum noise vs. optimum matching Thats why we need input matching schemes for LNA!
Analog and Mixed-Signal Center, TAMU 13
Vs 2 P = = in 2 Re( Z s ) 2
Narrowband LNA:
Inductive degenerated Resistive terminated
15
Since the input of a CS MOS devices is primarily capacitive then we can terminate the input with a resistor Rm=Rs to match the input (at low frequencies)
Vb
RD
Zout M2 I dc M1 Rm Z in
Vout
It can be used in both narrowband and the wideband application. But its high NF(usually NF>6dB) characteristic limits its application.
V in
Rs
16
Noise Analysis
Output noise due to source resistor Rs:
Vout
2 * Vn,D
Z out
RD
ro2
2 in,M2
- gm2Vx
+
Vgs2
-
C gs2
Vn2,m = KTRs ( g m1 RD ) 2
Output noise due to thermal noise of M1:
2 n , m1
Rs
V *
2 n,s
+
2 2 * V n,m i g1
C gs1 V1
-
Z in
Rm
gm1V1
ro1
i n,M1
Noise Analysis
The noise factor of the LNA is:
V + Vn , m + Vn ,m1 + Vn , D + Vn ,m 2 total output noise F= n,s noise due to the source resistor Vn2,s
2 2 2 2 2
( Rs + Rin )
2 ens
gm 2 = ens 1 + g m Rs
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Noise Analysis
io = ind + g m vgs ind Rs vgs = ( ind + g m vgs + jCgs vgs ) Rs vgs = 1 + g m vgs + jCgs vgs
1 + jCgs Rs
Notice that if gm=1/Rs (power match) then only half of drain current noise goes to the output
20
Noise Analysis
Noise Factor:
1 i + g R 1 gd 0 m s = 1+ 2 F = 1+ 2 g m Rs gm 2 ens + g R 1 m s
2 nd
F = 1+
gd 0
gm
Av =
RL (1 g m1 R f R f + RL
)
Rf
RL Vout
Z out
Input impedance: Z in =
R f + RL 1 + g m1 RL
//
1 sC gs1
RS
V in
Z in
Cf M1 Cgs1
Rs + R f 1 + g m1 Rs
22
Noise Analysis
Noise Factor:
2 2 2 2 2 4 iR 4 i Z Z R 4 id RL out f 1 Z out out s F = 1+ + + 2 2 2 2 Vn , Rs Av Vn , Rs Av Vn2, Rs Av2 2
R f 1 + g m1 Rs = 1+ Rs 1 g m1 R f
1 R f + Rs + RR s L 1 g m1 R f
g m1 R f + Rs + R s 1 g m1 R f
23
Z in = s ( Lg + Ls ) +
g L 1 + m s sC gs C gs
Z in ( j0 ) = Rs
o2 =
g L 1 , and Rs = m s = T Ls C gs ( Lg + Ls ) Cgs
if this value is too small to be practical, a capacitor can be inserted in shunt with Cgs to artificially reduce T
Analog and Mixed-Signal Center, TAMU 24
Input impedance-non-idealities
Z in = s ( Lg + Ls ) +
o =
1 ( Lg + Ls ) Cgs / / 1 T RLs
Rg = R poly , shW 12n 2 L
Rg , NQS = 1 5gm
Q Boosting
At resonance we get Q boosting effect: 1 1 Q= = ( Rs + LsT ) Cgs0 2 Rs Cgs0
1 T id = g m vgs = Qg m vs = vs { 2 Rs 0 Gm 1 4 24 3
Gm
vgs = Q vs
Need to watch out for linearity as vgs is Q times larger than the input signal Short channel devices operating in velocity saturation regime (i.e., large overdrive voltage) are more forgiving as their gm is relatively constant.
Analog and Mixed-Signal Center, TAMU 26
27
Noise Analysis
The output noise current due to Rs and Rg is simply calculated by multiplying the voltage noise sources by Gm The calculation of output noise current due to drain noise is more 2 involved: id flows partly into the source of the device, it activates the 2 gm of the transistor which produces a correlated noise in shunt with id
T o
28
j Ls 1 1 j Ls + + j Lg + Rs jC gs jC gs g m vgs = id 2
j Ls 1 (at resonance) Rs jC gs
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i =G
2 no
2 m
(v
2 Rs
+v
2 Rg
1 2 + id 4
1 Gm = 2 Rs
T o
2
F=
2 no
2 2 Gm vRs
o = 1+ + g m Rs Rs T Rg
Note that the Noise figure at resonance is the same as CS amplifier w/o inductive degeneration. Inductive degeneration did not raise Fmin but matched the input !
30
= 1 + 2 c QL
QL = QCgs
o ( Lg + Ls ) 1 = = o Rs Cgs Rs
2 2 2 + 1 + QL ( ) 5 5
Optimal Noise figure happens for a particular QL. Possible to obtain a noise and power match
* D.K. Shaeffer, T.H. Lee, A 1.5V 1.5GHz CMOS Low Noise Amplifier, JSSC, Vol. 32, No. 5. May 1997
Analog and Mixed-Signal Center, TAMU 31
Optimal QL
If we try to optimize the noise figure while power dissipation is kept constant then: QL,opt will be independent from the frequency and around 4.5 Fmin is not too sensitive to QL and only changes by less than 0.1dB for QL between 3.5 and 5.5 Smaller QL results in larger bandwidth and smaller inductors, while a larger QL results in narrower bandwidth and larger inductors
32
Linearity
Linearity of a MOS transistor in saturation region:
Veff
IIP3 is independent of W
2 2 VIIP 3, LNA (V ) =
16 P 3 P
2 D 2 2 o
( 2 + ) 1 +
= Veff
(Q
= 1 o Rs Cgs )
Step 2: Determine the current(Id) from power budget Step 3: From W & Id gm and Veff Step 4: From gm and Veff T and Fmin Step 5: Select Ls and Lg for the input network
Ls = Rs T
2 Lg = (1/ o C gs ) Ls
34
Increase T by increasing Id (with fixed device size) For fixed current density, increasing Q will reduce device size thus reduce total power - NF will increase
Reduce Q (in short channel devices the improvement is limited) Burn more current (not gaining much due to velocity saturation) Apply proper linearization techniques
Design Example:
Specs:
Frequency S11 S21 NF IIP3 Current Supply Process 2.4GHz <-10dB >15dB <2dB >-10dBm <10mA 1.8V 0.18m CMOS
C gs = 1 2QLo Rs = 147 fF
Choose minimum length L = 0.18m W = 110m Step 2: Choose the current Id = 9mA Step 3: From W & Id gm = 52mA/V Step 4: From gm and Cgs fT = 56GHz Step 5: Select Ls and Lg for the input network:
Ls = Rs T = 0.14nH
2 Lg = 1 o Cgs Ls = 31nH
37
38
Summary:
Parameters:
Calculated Simulated 110m/0.18 m 110 m/0.18 m 20nH 0.28nH 8.6mA 26
Performance:
Specs Frequency S11 S21 NF IIP3 Current Supply 2.4GHz <-10dB >15dB <2dB <10mA 1.8V Simulation 2.4GHz -32dB 15.7dB ~0.62dB 8.6mA 1.8V
>-10dBm -6.85dBm
39
We ignored the effect of load impedance on input impedance in previous derivations. Lets revisit it: It can be shown that:
RL can be large and it can drop the real part of the input impedance when we use resonators at output Notice that the output impedance influenced the input impedance even in the absence of Cgd!
Analog and Mixed-Signal Center, TAMU 40
41
C1 + C2 jC1C2
For passive termination, the real part of the source impedance will always be positive. IF Rin,com happens to be negative and cancel the real part of source impedance, oscillation MAY occur.
Analog and Mixed-Signal Center, TAMU 42
F. Gatta, E. Sacchi, et al, A 2-dB Noise Figure 900MHz Differential CMOS LNA, IJSSC, Vol. 36, No. 10, Oct. 2001 pp. 1444-1452
43
Chunyu Xin, and Edgar Snchez-Sinencio, A GSM LNA Using Mutual-Coupled Degeneration, IEEE Microwave and Wireless Components Letters, VOL. 15, NO. 2, Feb 2005
44
Drawback
Large NF
Substrate Noise
A MOS device is in fact a 4 terminal device. The 4th terminal is the substrate. The bulk-source potential modulates the drain current with a transconductance of gmb which has the same polarity as gm (i.e., increasing the bulk potential increases the drain current) The substrate has a finite (nonzero) resistance and therefore has thermal noise To reduce Rsub we should put many substrate contacts close to the device 4kTRsub 2 2
ino , sub = 1 + ( RsubCb )
2
f g mb
Substrate Noise(cont.)
Reduces possibility of latch up issues Lowers Rsub and its associated noise(Impacts LNA through backgate effect (gmb) Absorbs stray electrons from other circuits that will otherwise inject noise into the LNA
Package Parasitics
As interface to the external world, the LNA must transit from the silicon chip to the package and board environment, which involves bondwires, package leads, and PCB trace.
Analog and Mixed-Signal Center, TAMU 48
Package Parasitics(cont.)
Package Parasitics(cont.)
Some or all of the degeneration inductor Ls can be absorbed into the bondwire inductance These parasitics must be absorbed into the LNA design. This requires a good model for the package and bondwires. It should be noted that the inductance of the input loop depends on the arrangement of the bondwires, and hence die size and pad locations. Many designs also require ESD protection, which manifests as increased capacitance on the pads.
For more details, please read:
1. B. Razavi, Design of Analog CMOS Integrated Circuits (chapter 18) McGraw-Hill, New York 2001. 2. Andrzej Szymaski et.al: Effects of package and process variation on 2.4 GHz analog integrated circuits, Microelectronics and Reliability, Jan. 2006
Analog and Mixed-Signal Center, TAMU 50
Before doing the measurement: Calibrate two lines. Adjust the power level
52
Output Signal
Analog and Mixed-Signal Center, TAMU 53
Noise Source
54