150ma, Low-Dropout Regulator, Ultralow-Power, I 1 A With Pin-Selectable, Dual-Level Output Voltage

TPS781 Series
www.ti.com ........................................................................................................................................................... SBVS102B – MARCH 2008 – REVISED MAY 2008
150mA, Low-Dropout Regulator, Ultralow-Power, IQ 1µA

with Pin-Selectable, Dual-Level Output Voltage
1FEATURES The VSET pin allows the end user to switch between
• Low IQ: 1µA
2
two voltage levels on-the-fly through a
microprocessor-compatible input. This LDO is
• 150mA, Low-Dropout Regulator with designed specifically for battery-powered applications
Pin-Selectable Dual Voltage Level Output where dual-level voltages are needed. With ultralow
• Low Dropout: 200mV at 150mA IQ (1µA), microprocessors, memory cards, and smoke
• 3% Accuracy Over Load/Line/Temperature detectors are ideal applications for this device.
• Available in Dual-Level, Fixed Output Voltages The ultralow-power and selectable dual-level output
from 1.5V to 4.2V Using Innovative Factory voltages allow designers to customize power
EPROM Programming consumption for specific applications. Designers can
now shift to a lower voltage level in a battery-powered
• Available in an Adjustable Version from 1.22V design when the microprocessor is in sleep mode,
to 5.25V or a Dual-Level Output Version further reducing overall system power consumption.
• VSET Pin Toggles Output Voltage Between Two The two voltage levels are preset at the factory
Factory-Programmed Voltage Levels through a unique architecture using an EPROM. The
EPROM technique allows for numerous output
• Stable with a 1.0µF Ceramic Capacitor
voltage options between VSET low (1.5V to 4.2V) and
• Thermal Shutdown and Overcurrent Protection VSET high (2.0V to 3.0V) in the fixed output version
• CMOS Logic Level-Compatible Enable Pin only. Consult with your local factory representative for
• Available in DDC (TSOT23-5) or DRV (2mm × exact voltage options and ordering information;
minimum order quantities may apply.
2mm SON-6) Package Options
The TPS781 series are designed to be compatible
APPLICATIONS with the TI MSP430 and other similar products. The
• TI MSP430 Attach Applications enable pin is compatible with standard CMOS logic.
This LDO is stable with any output capacitor greater
• Power Rails with Programming Mode than 1.0µF. Therefore, implementations of this device
• Dual Voltage Levels for Power-Saving Mode require minimal board space because of miniaturized
• Wireless Handsets, Smartphones, PDAs, MP3 packaging and a potentially small output capacitor.
Players, and Other Battery-Operated Handheld The TPS781 series IQ (1µA) also come with thermal
Products shutdown and current limit to protect the device
during fault conditions. All packages have an
DESCRIPTION operating temperature range of TJ = –40°C to
+125°C. For high-performance applications requiring
The TPS781 family of low-dropout (LDO) regulators a dual-level voltage option, consider the TPS780
offer the benefits of ultralow power (IQ = 1µA), series, with an IQ of 500nA and dynamic voltage
miniaturized packaging (2×2 SON-6), and selectable scaling.
dual-level output voltage levels. An adjustable version
is also available, but does not have the capability to
shift voltage levels.
TPS781DDC TPS781DRV
TSOT23-5 2mm x 2mm SON-6
(TOP VIEW) (TOP VIEW)
IN 1 5 OUT OUT 1 6 IN
Thermal
GND 2 N/C 2 Pad 5 GND
EN 3 4 VSET/FB VSET/FB 3 4 EN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS781 Series
SBVS102B – MARCH 2008 – REVISED MAY 2008 ........................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1) (2)

PRODUCT VOUT
TPS781vvvxxxyyyz VVV is the nominal output voltage for VOUT(HIGH) and corresponds to VSET pin low.
XXX is the nominal output voltage for VOUT(LOW) and corresponds to VSET pin high.
YYY is the package designator.
Z is the tape and reel quantity (R = 3000, T = 250).
Adjustable version (3) (4)
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Additional output voltage combinations are available on a quick-turn basis using innovative, factory EPROM programming.
Minimum-order quantities apply; contact your sales representative for details and availability.
(3) To order the adjustable version, use TPS78101YYYZ.
(4) The device is either fixed voltage, dual-level VOUT, or adjustable voltage only. Device design does not permit a fixed and adjustable
output simultaneously.
ABSOLUTE MAXIMUM RATINGS (1)

At TJ = –40°C to +125°C, unless otherwise noted. All voltages are with respect to GND.
PARAMETER TPS781 Series UNIT
Input voltage range, VIN –0.3 to +6.0 V
Enable and VSET voltage range, VEN and VVSET –0.3 to VIN + 0.3 (2) V
Output voltage range, VOUT –0.3 to VIN + 0.3V V
Maximum output current, IOUT Internally limited
Output short-circuit duration Indefinite
Total continuous power dissipation, PDISS See the Dissipation Ratings table
Human body model (HBM) 2 kV
ESD rating
Charged device model (CDM) 500 V
Operating junction temperature range, TJ –40 to +125 °C
Storage temperature range, TSTG –55 to +150 °C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) VEN and VVSET absolute maximum rating are VIN + 0.3V or +6.0V, whichever is less.
DISSIPATION RATINGS
DERATING FACTOR
BOARD PACKAGE RθJC RθJA ABOVE TA = +25°C TA < +25°C TA = +70°C TA = +85°C
(1)
High-K DRV 20°C/W 65°C/W 15.4mW/°C 1540mW 845mW 615mW
High-K (1) DDC 90°C/W 200°C/W 5.0mW/°C 500mW 275mW 200mW
(1) The JEDEC high-K (2s2p) board used to derive this data was a 3-inch × 3-inch, multilayer board with 1-ounce internal power and ground
planes and 2-ounce copper traces on top and bottom of the board.
2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated

TPS781 Series
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(NOM) + 0.5V or 2.2V, whichever is greater; IOUT =
100µA, VVSET = VEN = VIN, COUT = 1.0µF, fixed or adjustable, unless otherwise noted. Typical values at TJ = +25°C.
TPS781 Series
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range 2.2 5.5 V
Nominal TJ = +25°C, VSET = high/low –2 ±1 +2 %
VOUT (1) DC output accuracy Over VIN, IOUT, VOUT + 0.5V ≤ VIN ≤ 5.5V,
–3.0 ±2.0 +3.0 %
temperature 0mA ≤ IOUT ≤ 150mA, VSET = high/low
Internal reference (2)
VFB TJ = +25°C, VIN = 4.0V, IOUT = 75mA 1.216 V
(adjustable version only)
Output voltage range (3) (4)
VOUT_RANGE VIN = 5.5V, IOUT = 100µA (2) VFB 5.25 V
ΔVOUT/ΔVIN Line regulation VOUT(NOM) + 0.5V ≤ VIN ≤ 5.5V, IOUT = 5mA –1 +1 %
ΔVOUT/ΔIOUT Load regulation 0mA ≤ IOUT ≤ 150mA –2 +2 %
VDO Dropout voltage (5) VIN = 95% VOUT(NOM), IOUT = 150mA 250 mV
BW = 100Hz to 100kHz, VIN = 2.2V,
VN Output noise voltage 86 µVRMS
VOUT = 1.2V, IOUT = 1mA
VSET high (output VOUT(LOW)
VHI 1.2 VIN V
selected), or EN high (enabled)
VSET low (output VOUT(HIGH)
VLO 0 0.4 V
selected), or EN low (disabled)
ICL Output current limit VOUT = 0.90 × VOUT(NOM) 150 230 400 mA
IOUT = 0mA 1.0 1.3 µA
IGND Ground pin current
IOUT = 150mA 8 µA
VEN ≤ 0.4V, 2.2V ≤ VIN < 5.5V,
ISHDN Shutdown current (IGND) 18 130 nA
TJ = –40°C to +100°C
IVSET VSET pin current VEN = VVSET = 5.5V 70 nA
IEN EN pin current VEN = VVSET = 5.5V 40 nA
FB pin current (6)
IFB VIN = 5.5V, VOUT = 1.2V, IOUT = 100µA 10 nA
f = 10Hz 40 dB
VIN = 4.3V,
PSRR Power-supply rejection ratio VOUT = 3.3V, f = 100Hz 20 dB
IOUT = 150mA
f = 1kHz 15 dB
VOUT transition time (high-to-low) VOUT_LOW = 2.2V, VOUT(HIGH) = 3.3V,
tTR(H→L) 800 µs
VOUT = 97% × VOUT(HIGH) IOUT = 10mA
VOUT transition time (low-to-high) VOUT_HIGH = 3.3V, VOUT(LOW) = 2.2V,
tTR(L→H) 800 µs
VOUT = 97% × VOUT(LOW) IOUT = 10mA
COUT = 1.0µF, VOUT = 10% VOUT(NOM) to
tSTR Startup time (7) 500 µs
VOUT = 90% VOUT(NOM)
IOUT = 150mA, COUT = 1.0µF, VOUT = 2.8V,
tSHDN Shutdown time (8) VOUT = 90% VOUT(NOM) to VOUT = 10% 500 (9) µs
VOUT(NOM)
Shutdown, temperature increasing +160 °C
TSD Thermal shutdown temperature
Reset, temperature decreasing +140 °C
TJ Operating junction temperature –40 +125 °C
(1) The output voltage for VSET = low/high is programmed at the factory.
(2) Adjustable version only.
(3) No VSET pin on the adjustable version.
(4) No dynamic voltage scaling on the adjustable version.
(5) VDO is not measured for devices with VOUT(NOM) < 2.3V because minimum VIN = 2.2V.
(6) The TPS78101 FB pin is tied to VOUT. Adjustable version only.
(7) Time from VEN = 1.2V to VOUT = 90% (VOUT(NOM)).
(8) Time from VEN = 0.4V to VOUT = 10% (VOUT(NOM)).
(9) See Shutdown in the Application Information section for more details.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 3

TPS781 Series
FUNCTIONAL BLOCK DIAGRAM
IN OUT
Current
Limit
Thermal
Shutdown
MUX
EPROM
EN Bandgap
Active
Pull- 10kW
(1) Down
VSET/FB
LOGIC
GND
(1) Feedback pin (FB) for adjustable versions; VSET for fixed voltage versions.
PIN CONFIGURATIONS
TPS781DRV TPS781DDC
2mm x 2mm SON-6 TSOT23-5
(TOP VIEW) (TOP VIEW)
OUT 1 6 IN IN 1 5 OUT
Thermal
N/C 2 (1) 5 GND GND 2
Pad
VSET/FB 3 4 EN EN 3 4 VSET/FB
(1) It is recommended that the SON package thermal pad be connected to ground.
Table 1. TERMINAL FUNCTIONS

TERMINAL
NAME DRV DDC DESCRIPTION
Regulated output voltage pin. A small (1µF) ceramic capacitor is needed from this pin to
OUT 1 5 ground to assure stability. See the Input and Output Capacitor Requirements in the
Application Information section for more details.
N/C 2 — Not connected.
Feedback pin (FB) for adjustable versions; VSET for fixed voltage versions. Driving the select
VSET/FB 3 4 pin (VSET) below 0.4V selects preset output voltage high. Driving the VSET pin over 1.2V
selects preset output voltage low.
Driving the enable pin (EN) over 1.2V turns on the regulator. Driving this pin below 0.4V puts
EN 4 3
the regulator into shutdown mode, reducing operating current to 18nA typical.
GND 5 2 Ground pin.
Input pin. A small capacitor is needed from this pin to ground to assure stability. Typical input
IN 6 1 capacitor = 1.0µF. Both input and output capacitor grounds should be tied back to the IC
ground with no significant impedance between them.
Thermal pad Thermal pad — It is recommended that the SON package thermal pad be connected to ground.

TPS781 Series
TYPICAL CHARACTERISTICS
Over the operating temperature range of TJ = –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater;
IOUT = 100µA, VEN = VVSET = VIN, COUT = 1µF, and CIN = 1µF, unless otherwise noted.
LINE REGULATION LINE REGULATION

IOUT = 5mA, VOUT = 1.22V (typ) IOUT = 5mA, VVSET = 1.2V, VOUT = 2.2V (typ)
TPS78101 TPS781330220
0.3 1.0
0.8
0.2
0.6
TJ = +85°C TJ = +25°C TJ = -40°C
0.4
0.1
TJ = +25°C 0.2
VOUT (%)
VOUT (%)
TJ = +125°C
0 0
-0.2
-0.1 TJ = +125°C
-0.4
-0.6
-0.2
TJ = -40°C TJ = +85°C -0.8
-0.3 -1.0
2.2 2.7 3.2 3.7 4.2 4.7 5.2 5.7 2.7 3.2 3.7 4.2 4.7 5.2 5.7
VIN (V) VIN (V)
Figure 1. Figure 2.
LINE REGULATION LINE REGULATION

IOUT = 150mA, VVSET = 1.2V, VOUT = 2.2V (typ) IOUT = 5mA, VVSET = 0.4V, VOUT = 3.3V (typ)
TPS781330220 TPS781330220
3 1.0
0.8
2 TJ = -40°C
0.6
TJ = +25°C
0.4
1
0.2
VOUT (%)
VOUT (%)
TJ = +25°C TJ = -40°C
0 0
-0.2
TJ = +85°C
-1
-0.4
TJ = +85°C -0.6
-2
-0.8
-3 -1.0
2.7 3.2 3.7 4.2 4.7 5.2 5.7 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
VIN (V) VIN (V)
Figure 3. Figure 4.
LINE REGULATION LOAD REGULATION

IOUT = 150mA, VVSET = 0.4V, VOUT = 3.3V (typ) VOUT = 3.3V
TPS781330220 TPS78101
3 1.5
2
1.0
1 TJ = +125°C
TJ = -40°C 0.5
VOUT (%)
VOUT (%)
0 TJ = +25°C
0
-1
-0.5
-2
TJ = +85°C TJ = +25°C TJ = +85°C
TJ = -40°C
-3 -1.0
3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 0 25 50 75 100 125 150
VIN (V) IOUT (mA)
Figure 5. Figure 6.

TPS781 Series
TYPICAL CHARACTERISTICS (continued)

LOAD REGULATION LOAD REGULATION

VVSET = 1.2V, VIN = 2.7V, VOUT = 2.2V VVSET = 0.4V, VIN = 3.8V, VOUT = 3.3V
TPS781330220 TPS781330220
3.0 3
2.5
2
2.0
TJ = -40°C
1.5
1
1.0
VOUT (%)
VOUT (%)
0.5 0
TJ = -40°C
0
-1
-0.5
TJ = +25°C TJ = +85°C
-1.0
TJ = +25°C -2
-1.5
TJ = +85°C
-2.0 -3
0 25 50 75 100 125 150 0 25 50 75 100 125 150
IOUT (mA) IOUT (mA)
Figure 7. Figure 8.
DROPOUT VOLTAGE vs OUTPUT CURRENT DROPOUT VOLTAGE vs OUTPUT CURRENT

VOUT = 3.3V (typ), VIN = 0.95 × VOUT (typ) VVSET = 0.4V, VOUT = 3.3V (typ), VIN = 0.95 × VOUT (typ)
TPS78101 TPS781330220
200 250
180 TJ = +125°C
TJ = +85°C
160 200
VDO (VIN - VOUT) (mV)
140 TJ = +85°C
TJ = +125°C
120 150
100
80 100
60
40 50
TJ = +25°C TJ = -40°C TJ = -40°C
20 TJ = +25°C
0 0
0 25 50 75 100 125 150 0 25 50 75 100 125 150
IOUT (mA) IOUT (mA)
Figure 9. Figure 10.
DROPOUT VOLTAGE vs TEMPERATURE DROPOUT VOLTAGE vs TEMPERATURE

VOUT = 3.3V (typ), VIN = 0.95 × VOUT (typ) VVSET = 0.4V, VOUT = 3.3V (typ), VIN = 0.95 × VOUT (typ)
TPS78101 TPS781330220
250 250
200 200
150mA 150mA
150 150
100mA 100mA
100 100
50mA 50mA
50 50
10mA 10mA
0 0
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C) Temperature (°C)

TPS781 Series

GROUND PIN CURRENT vs INPUT VOLTAGE GROUND PIN CURRENT vs INPUT VOLTAGE
IOUT = 50mA, VOUT = 1.22V IOUT = 150mA, VOUT = 1.22V
TPS78101 TPS78101
6 8
TJ = +85°C TJ = +125°C
7
5
TJ = +125°C
TJ = +85°C 6
4
5
IGND (mA)
IGND (mA)
3 4
3
2 TJ = +25°C TJ = -40°C
TJ = +25°C 2
1
TJ = -40°C 1
0 0
2.2 2.7 3.2 3.7 4.2 4.7 5.2 5.7 2.2 2.7 3.2 3.7 4.2 4.7 5.2 5.7
VIN (V) VIN (V)
IOUT = 50mA, VVSET = 1.2V, VOUT = 2.2V IOUT = 150mA, VVSET = 1.2V, VOUT = 2.2V
TPS781330220 TPS781330220
6 12
11
5 10
TJ = +85°C TJ = +125°C 9
TJ = +125°C
4 8
TJ = +85°C
IGND (mA)
IGND (mA)
7
3 6
5
2 4
TJ = +25°C TJ = -40°C 3
TJ = +25°C
1 2
TJ = -40°C
1
0 0
2.7 3.2 3.7 4.2 4.7 5.2 5.7 2.7 3.2 3.7 4.2 4.7 5.2 5.7
VIN (V) VIN (V)
IOUT = 50mA, VVSET = 0.4V, VOUT = 3.3V IOUT = 150mA, VVSET = 0.4V, VOUT = 3.3V
TPS781330220 TPS781330220
6 9
8
5 TJ = +85°C TJ = +125°C
TJ = +85°C TJ = +125°C 7
4 6
IGND (mA)
IGND (mA)
5
3
4
2 3
TJ = +25°C TJ = +25°C TJ = -40°C
TJ = -40°C 2
1
1
0 0
3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
VIN (V) VIN (V)

TPS781 Series

SHUTDOWN CURRENT vs INPUT VOLTAGE CURRENT LIMIT vs INPUT VOLTAGE

IOUT = 0mA, VVSET = 0.4V VOUT = 90% VOUT (typ), VOUT = 1.22V (typ)
TPS78101 TPS78101
60 280
270
50 TJ = -40°C
TJ = +85°C 260
Current Limit (mA)

40
250
IGND (nA)
TJ = +25°C
30 240
TJ = +25°C 230
20
220
TJ = +85°C
10
TJ = -40°C 210
0 200
2.2 2.7 3.2 3.7 4.2 4.7 5.2 5.7 2.2 2.7 3.2 3.7 4.2 4.7 5.2 5.7
VIN (V) VIN (V)
CURRENT LIMIT vs INPUT VOLTAGE CURRENT LIMIT vs INPUT VOLTAGE

VVSET = 1.2V, VOUT = 95% VOUT (typ), VOUT = 2.2V (typ) VVSET = 0.4V, VOUT = 95% VOUT (typ), VOUT = 3.3V (typ)
TPS781330220 TPS781330220
300 300
290 290
280 280
Current Limit (mA)
Current Limit (mA)
270 TJ = -40°C 270 TJ = -40°C

260 260
250 250
TJ = +25°C TJ = +25°C
240 240
230 TJ = +85°C 230 TJ = +85°C
220 220
TJ = +125°C TJ = +125°C
210 210
200 200
2.7 3.2 3.7 4.2 4.7 5.2 5.7 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
VIN (V) VIN (V)
FEEDBACK PIN CURRENT vs TEMPERATURE VSET PIN CURRENT vs INPUT VOLTAGE

IOUT = 0mA, VOUT = 1.22V IOUT = 100µA, VVSET = 1.2V, VOUT = 2.2V
TPS78101 TPS781330220
5 1.0
4 0.8
0.6
IVSET (nA)
3
IFB (nA)
TJ = +85°C TJ = -40°C TJ = +25°C

2 0.4
VIN max
1 0.2
VIN min
0 0
-40 -25 -10 5 20 35 50 65 80 95 110 125 2.7 3.2 3.7 4.2 4.7 5.2 5.7
Temperature (°C) VIN (V)

TPS781 Series

VSET PIN CURRENT vs INPUT VOLTAGE ENABLE PIN CURRENT vs INPUT VOLTAGE
IOUT = 100µA, VVSET = 0.4V, VOUT = 3.3V IOUT = 1mA, VOUT = 1.22V
TPS781330220 TPS78101
2.5 2.0
TJ = +125°C 1.8
2.0
1.6
1.4
1.5
1.2
IVSET (nA)
IEN (nA)
TJ = +85°C TJ = +25°C TJ = -40°C
1.0 1.0
TJ = +85°C TJ = -40°C 0.8
0.5
0.6
0.4
0
TJ = +25°C 0.2
-0.5 0
3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 2.2 2.7 3.2 3.7 4.2 4.7 5.2 5.7
VIN (V) VIN (V)
ENABLE PIN CURRENT vs INPUT VOLTAGE ENABLE PIN CURRENT vs INPUT VOLTAGE
IOUT = 100µA, VSET = 1.2V, VOUT = 2.2V IOUT = 100µA, VVSET = 0.4V, VOUT = 3.3V
TPS781330220 TPS781330220
2.0 2.0
1.8 1.8
1.6 1.6
1.4 1.4
IEN (nA)
1.2 1.2
IEN (nA)
1.0 1.0
TJ = +85°C TJ = +25°C TJ = -40°C TJ = +85°C TJ = +25°C TJ = -40°C
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0 0
2.7 3.2 3.7 4.2 4.7 5.2 5.7 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
VIN (V) VIN (V)
ENABLE PIN HYSTERESIS vs TEMPERATURE ENABLE PIN HYSTERESIS vs TEMPERATURE

IOUT = 1mA, TPS78101 IOUT = 1mA, TPS781330220
1.2 1.2
1.1 1.1
1.0 1.0
VEN On VEN On
0.9 0.9
VEN (V)
VEN (V)
0.8 0.8
0.7 0.7
VEN Off VEN Off
0.6 0.6
0.5 0.5
0.4 0.4
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125

TPS781 Series

%ΔVOUT vs TEMPERATURE %ΔVOUT vs TEMPERATURE

IOUT = 1mA, VIN = 3.8V, VOUT = 3.3V VVSET = 1.2V, VIN = 2.7V, VOUT = 2.2V (typ)
TPS78101 TPS781330220
0.4 1
0.3
0.1mA
0.2
0
%DVOUT (V)
0.1
%VOUT (V)
5mA
0
-0.1
-1
-0.2 150mA
-0.3
-0.4 -2
-40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125
%ΔVOUT vs TEMPERATURE OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY

VVSET = 0.4V, VIN = 3.8V, VOUT = 3.3V (typ) CIN = 1µF, COUT = 2.2µF, VVSET = 1.2V, VIN = 2.7V
TPS781330220 TPS781330220
3 100
Output Spectral Noise Density (mV/ÖHz)
2
10
150mA
1 109mVRMS
%DVOUT (V)
1
0.1mA
0
5mA 0.1
-1 50mA
150mA 109mVRMS
0.01
-2
1mA
108mVRMS
-3 0.001
-40 -25 -10 5 20 35 50 65 80 95 110 125 10 100 1k 10k 100k
Temperature (°C) Frequency (Hz)
RIPPLE REJECTION vs FREQUENCY

VIN = 2.7V, VOUT = 1.2V, COUT = 2.2µF INPUT VOLTAGE RAMP vs OUTPUT VOLTAGE
TPS78101 TPS781330220
80
VIN VIN = 0.0V to 5.0V
1mA
70 VOUT = 3.3V
VOUT
Enable IOUT = 150mA
Voltage (1V/div)
60 COUT = 10mF
Current (50mA/div)
50
PSRR (dB)
40
50mA Load Current
30
20 0V
150mA
10
0
10 100 1k 10k 100k 1M 10M Time (20ms/div)
Frequency (Hz)

TPS781 Series

OUTPUT VOLTAGE vs ENABLE (SLOW RAMP) INPUT VOLTAGE vs DELAY TO OUTPUT

TPS781330220 TPS781330220
VIN Enable VSET
Voltage (1V/div)
Voltage (1V/div)
Current (50mA/div)
Current (50mA/div)
VOUT
Load Current VIN
Load Current
VIN = 5.5V
VOUT = 3.3V
IOUT = 150mA VIN = 0.0V to 5.5V
COUT = 10mF VOUT VOUT = 2.2V
0A IOUT = 100mA
0V
0V COUT = 10mF
Time (20ms/div) Time (1ms/div)

LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE

TPS781330220 TPS781330220
VIN VIN
1V/div 1V/div
VOUT VOUT
VIN = 4.0V to 4.5V VIN = 4.0V to 4.5V
VOUT = 2.2V VOUT = 3.3V
IOUT = 150mA IOUT = 150mA
Slew Rate = 1V/ms Slew Rate = 1V/ms

LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE

TPS781330220 TPS781330220
VIN Enable Enable

(100mV/div)
(100mV/div)
Voltage
Voltage
VOUT
VIN
VOUT
VIN = 5.5V
VOUT = 3.3V
(20mA/div)
(10mA/div)
Current
Current
IOUT = 0mA to 10mA Load Load

COUT = 10mF Current VIN = 5.5V Current
VOUT = 3.3V
IOUT = 0mA to 60mA
0A 0A
COUT = 10mF


TPS781 Series

ENABLE PIN vs OUTPUT VOLTAGE RESPONSE

AND OUTPUT CURRENT ENABLE PIN vs OUTPUT VOLTAGE DELAY
TPS781330220 TPS781330220
Enable
VIN = 5.5V
VIN VOUT = 3.3V
Enable
Voltage (1V/div)
Voltage (1V/div)
VOUT IOUT = 150mA

VOUT
Current (50mA/div)
Current (50mA/div)
VIN COUT = 10mF
Load Current Load

Current
VIN = 5.50V
0V 0V
VOUT = 3.3V
IOUT = 150mA
COUT = 10mF

VSET PIN TOGGLE VSET PIN TOGGLE

TPS781330220 TPS781330220
VOUT VOUT
1V/div
VSET VSET
1V/div
VIN = 5.0V
Enable = VIN VIN = 5.0V
IOUT = 150mA IOUT = 150mA
VOUT Transitioning from 2.2V to 3.3V VOUT Transitioning from 3.3V to 2.2V

VSET PIN TOGGLE (SLOW RAMP)

TPS781330220
Current (50mA/div)
VIN
VOUT VSET
Voltage (1V/div)
100mA
VIN = 5.5V
VOUT = 3.3V 50mA
Load Current IOUT = 150mA
to 100mA 0A
COUT = 10mF
Time (50ms/div)
Figure 47.

TPS781 Series
APPLICATION INFORMATION
APPLICATION EXAMPLES Programming the TPS78101 Adjustable LDO

Regulator
The TPS781 series of LDOs typically take less than
The output voltage of the TPS78101 adjustable
800µs to transition from a lower voltage of 2.2V to a
regulator is programmed using an external resistor
higher voltage of 3.3V under an output load of
divider as shown in Figure 49. The output voltage
150mA; see Figure 45. Additionally, the TPS781
operating range is 1.2V to 5.1V, and is calculated
series contain active pull-down circuitry that
using Equation 1:
automatically pulls charge out of the voltage capacitor
to transition the output voltage from the higher
voltage to the lower voltage, even with no load
VOUT = VFB ´ 1 + 1
R
R2 ( ) (1)
connected. Output voltage overshoots and
undershoots are minimal under this load condition. Where:
The TPS781 series typically take less than 800µs to VFB = 1.216V typ (the internal reference voltage)
transition from VSET low (3.3V to 2.2V), or VSET high
Resistors R1 and R2 should be chosen for
(2.2V to 3.3V); see Figure 45 and Figure 46. Both
approximately 1.2µA divider current. Lower value
output states of the TPS781 series are
resistors can be used for improved noise
factory-programmable between 1.5V to 4.2V. Note
performance, but the solution consumes more power.
that during startup or steady-state conditions, it is
Higher resistor values should be avoided as leakage
important that the EN pin and VSET pin voltages never
current into/out of FB across R1/R2 creates an offset
exceed VIN + 0.3V.
voltage that artificially increases/decreases the
feedback voltage and thus erroneously
4.2V to 5.5V 2.2V to 3.3V
VIN IN OUT VOUT decreases/increases VOUT. Table 2 lists several
1m F 1mF
common output voltages and resistor values. The
TPS781
recommended design procedure is to choose R2 =
1MΩ to set the divider current at 1.2µA, and then
On
EN
calculate R1 using Equation 2:
Off
VSET High = VOUT(LOW)

V
(
R1 = OUT - 1 ´ R2
VFB ) (2)
VSET Low = VOUT(HIGH) VSET
GND
VIN IN OUT VOUT

1m F 1mF
Figure 48. Typical Application Circuit R1
TPS78101
EN FB
The TPS781 series is also used effectively in
dynamic voltage scaling (DVS) applications. DVS R2
GND
applications are required to dynamically switch
between a high operational voltage to a low standby
voltage in order to reduce power consumption.
Modern multimillion gate microprocessors fabricated R1
with the latest sub-micron processes save power by VOUT = VFB ´ (1 + )
transitioning to a lower voltage to reduce leakage R2
currents while maintaining content. This architecture
enables the microprocessor to transition quickly into Figure 49. TPS78101 Adjustable LDO Regulator
an operational state (wake up) without requiring a Programming
reload of the states from external memory, or a
reboot.
Table 2. Output Voltage Programming Guide
OUTPUT VOLTAGE R1 R2
1.8V 0.499MΩ 1MΩ
2.8V 1.33MΩ 1MΩ
5.0V 3.16MΩ 1MΩ

TPS781 Series
Powering the MSP430 Microcontroller 3.0V

VIN VOUT VCC
Several versions of the TPS781 are ideal for
1m F 1m F
powering the MSP430 microcontroller. Table 3 shows LDO MSP430
potential applications of some voltage versions.
I/O
GND VSS
Table 3. Typical MSP430 Applications
VOUT(HIGH) VOUT(LOW)
DEVICE (TYP) (TYP) APPLICATION
VOUT, MIN > 1.800V
required by many VCC = 3.0V
MSP430s. Allows
TPS781360200 3.6V 2.0V
lowest power 5mA
consumption
Active
operation.
Mode
VOUT, MIN > 2.200V
required by some 1.6mA IQ
TPS781360220 3.6V 2.2V
MSP430s FLASH LPM3/Sleep Mode
operation.
VOUT, MIN > 2.700V
required by some
TPS781360300 3.6V 3.0V
MSP430s FLASH
operation. Figure 50. Typical LDO without DVS
VOUT, MIN < 3.600V
required by some
TPS781360220 3.6V 2.2V MSP430s. Allows
2.2V to 3.6V
highest speed
VIN VOUT VCC
operation.
1m F 1m F
TPS781 MSP430
The TPS781 family offers many output voltage
VSET I/O
versions to allow designers to optimize the supply
GND VSS
voltage for the processing speed required of the
MSP430. This flexible architecture minimizes the
supply current consumed by the particular MSP430
application. The MSP430 total system power can be
reduced by substituting the 1µA IQ TPS781 series VCC = 3.6V
LDO in place of an existing, older-technology LDO.
Additionally, DVS allows for increasing the clock VCC = 2.2V 5mA
speed in active mode (MSP430 VCC = 3.6V). The Active
3.6V VCC reduces the MSP430 time in active mode. Mode
In low-power mode, MSP430 system power can be
further reduced by lowering the MSP430 VCC to 2.2V 700nA IQ
Current LPM3/Sleep Mode
in sleep mode.
Key features of the TPS781 series are an ultralow
quiescent current (1µA), DVS, and miniaturized
packaging. The TPS781 family are available in
SON-6 and TSOT-23 packages. Figure 50 shows a Figure 51. TPS781 with Integrated DVS
typical MSP430 circuit powered by an LDO without
DVS. Figure 51 is an MSP430 circuit using a TPS781 The other benefit of DVS is that it allows a higher VCC
LDO that incorporates an integrated DVS, thus voltage on the MSP430, increasing the clock speed
simplifying the circuit design. In a circuit without DVS, and reducing the active mode dwell time.
as Figure 50 illustrates, VCC is always at 3.0V. When
the MSP430 goes into sleep mode, VCC remains at
3.0V; if DVS is applied, VCC could be reduced in
sleep mode. In Figure 51, the TPS781 LDO with
integrated DVS maintains 3.6V VCC until a logic high
signal from the MSP430 forces VOUT to level shift
VOUT from 3.6V down to 2.2V; thus reducing power in
sleep mode.

TPS781 Series
INPUT AND OUTPUT CAPACITOR SHUTDOWN

REQUIREMENTS
The enable pin (EN) is active high and is compatible
Although an input capacitor is not required for with standard and low-voltage CMOS levels. When
stability, it is good analog design practice to connect shutdown capability is not required, EN should be
a 0.1µF to 1.0µF low equivalent series resistance connected to the IN pin, as shown in Figure 52.
(ESR) capacitor across the input supply near the Figure 53 shows both EN and VSET connected to IN.
regulator. This capacitor counteracts reactive input The TPS781 series, with internal active output
sources and improves transient response, noise pull-down circuitry, discharges the output to within 5%
rejection, and ripple rejection. A higher-value VOUT with a time (t) shown in Equation 3:
capacitor may be necessary if large, fast rise-time
load transients are anticipated, or if the device is not 10kW ´ RL
t=3 ´ COUT
located near the power source. If source impedance 10kW + RL
is not sufficiently low, a 0.1µF input capacitor may be (3)
necessary to ensure stability. Where:
The TPS781 series are designed to be stable with RL= output load resistance
standard ceramic capacitors with values of 1.0µF or COUT = output capacitance
larger at the output. X5R- and X7R-type capacitors
are best because they have minimal variation in value 4.2V to 5.5V 2.2V to 3.3V
and ESR over temperature. Maximum ESR should be VIN IN OUT VOUT
less than 1.0Ω. With tolerance and dc bias effects, 1m F 1mF
the minimum capacitance to ensure stability is 1µF. TPS781
BOARD LAYOUT RECOMMENDATIONS TO EN

IMPROVE PSRR AND NOISE PERFORMANCE
VSET High = VOUT(LOW)
To improve ac performance (such as PSRR, output
VSET Low = VOUT(HIGH) VSET
noise, and transient response), it is recommended GND
that the printed circuit board (PCB) be designed with
separate ground planes for VIN and VOUT, with each
ground plane connected only at the GND pin of the
device. In addition, the ground connection for the Figure 52. Circuit Showing EN Tied High when
output capacitor should connect directly to the GND Shutdown Capability is Not Required
pin of the device. High ESR capacitors may degrade
PSRR.
4.2V to 5.5V 2.2V
VIN IN OUT VOUT
INTERNAL CURRENT LIMIT
1m F 1mF
The TPS781 is internally current-limited to protect the TPS781
regulator during fault conditions. During current limit,
the output sources a fixed amount of current that is EN
largely independent of output voltage. For reliable
operation, the device should not be operated in a
current limit state for extended periods of time.
VSET
The PMOS pass element in the TPS781 series has a GND
built-in body diode that conducts current when the
voltage at OUT exceeds the voltage at IN. This
current is not limited, so if extended reverse voltage
operation is anticipated, external limiting to 5% of Figure 53. Circuit to Tie Both EN and VSET High
rated output current may be appropriate.

TPS781 Series
DROPOUT VOLTAGE ACTIVE VOUT PULL-DOWN

The TPS781 series use a PMOS pass transistor to In the TPS781 series, the active pull-down discharges
achieve low dropout. When (VIN – VOUT) is less than VOUT when the device is off. However, the input
the dropout voltage (VDO), the PMOS pass device is voltage must be greater than 2.2V for the active
the linear region of operation and the input-to-output pull-down to work.
resistance is the RDS(ON) of the PMOS pass element.
VDO approximately scales with output current MINIMUM LOAD
because the PMOS device behaves like a resistor in
dropout. As with any linear regulator, PSRR and The TPS781 series are stable with no output load.
transient response are degraded as (VIN – VOUT) Traditional PMOS LDO regulators suffer from lower
approaches dropout. This effect is shown in the loop gain at very light output loads. The TPS781
Typical Characteristics section. Refer to application employs an innovative, low-current circuit under very
report SLVA207, Understanding LDO Dropout, light or no-load conditions, resulting in improved
available for download from www.ti.com. output voltage regulation performance down to zero
output current. See Figure 41 for the load transient
response.
TRANSIENT RESPONSE
As with any regulator, increasing the size of the
output capacitor reduces over/undershoot magnitude
but increases duration of the transient response. For
more information, see Figure 42.

TPS781 Series
THERMAL INFORMATION
THERMAL PROTECTION POWER DISSIPATION

Thermal protection disables the output when the The ability to remove heat from the die is different for
junction temperature rises to approximately +160°C, each package type, presenting different
allowing the device to cool. Once the junction considerations in the PCB layout. The PCB area
temperature cools to approximately +140°C, the around the device that is free of other components
output circuitry is enabled. Depending on power moves the heat from the device to the ambient air.
dissipation, thermal resistance, and ambient Performance data for JEDEC low- and high-K boards
temperature, the thermal protection circuit may cycle are given in the Dissipation Ratings table. Using
on and off again. This cycling limits the dissipation of heavier copper increases the effectiveness in
the regulator, protecting it from damage as a result of removing heat from the device. The addition of plated
overheating. through-holes to heat-dissipating layers also
improves the heatsink effectiveness. Power
Any tendency to activate the thermal protection circuit dissipation depends on input voltage and load
indicates excessive power dissipation or an conditions. Power dissipation (PD) is equal to the
inadequate heatsink. For reliable operation, junction product of the output current times the voltage drop
temperature should be limited to +125°C maximum. across the output pass element (VIN to VOUT), as
To estimate the margin of safety in a complete design shown in Equation 4:
(including heatsink), increase the ambient
temperature until the thermal protection is triggered; PD = (VIN - VOUT) ´ IOUT (4)
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least PACKAGE MOUNTING
+35°C above the maximum expected ambient
condition of your particular application. This Solder pad footprint recommendations for the
configuration produces a worst-case junction TPS781 series are available from the Texas
temperature of +125°C at the highest expected Instruments web site at www.ti.com through the
ambient temperature and worst-case load. TPS781 series product folders.
The internal protection circuitry of the TPS781 series

has been designed to protect against overload
conditions. However, it is not intended to replace
proper heatsinking. Continuously running the TPS781
series into thermal shutdown degrades device
reliability.

PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TPS78101DDCR ACTIVE SOT-23-THIN DDC 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 CEB
TPS78101DDCT ACTIVE SOT-23-THIN DDC 5 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 CEB
TPS78101DRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 CEB
TPS78101DRVT ACTIVE WSON DRV 6 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 CEB
TPS781250200DDCR ACTIVE SOT-23-THIN DDC 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 SAN
TPS781250200DDCT ACTIVE SOT-23-THIN DDC 5 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 SAN
TPS781330220DDCR ACTIVE SOT-23-THIN DDC 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 CED
TPS781330220DDCRG4 ACTIVE SOT-23-THIN DDC 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 CED
TPS781330220DDCT ACTIVE SOT-23-THIN DDC 5 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 CED
TPS781330220DRVR ACTIVE WSON DRV 6 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 CED
TPS781330220DRVT ACTIVE WSON DRV 6 250 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 CED
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS78101DDCR SOT- DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
23-THIN
TPS78101DDCT SOT- DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
23-THIN
TPS78101DRVR WSON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS78101DRVT WSON DRV 6 250 178.0 8.4 2.25 2.25 1.0 4.0 8.0 Q2
TPS781250200DDCR SOT- DDC 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
23-THIN
TPS781250200DDCT SOT- DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
23-THIN
TPS781330220DDCR SOT- DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
23-THIN
TPS781330220DDCT SOT- DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
23-THIN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 5-Jan-2021
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS78101DDCR SOT-23-THIN DDC 5 3000 213.0 191.0 35.0
TPS78101DDCT SOT-23-THIN DDC 5 250 213.0 191.0 35.0
TPS78101DRVR WSON DRV 6 3000 200.0 183.0 25.0
TPS78101DRVR WSON DRV 6 3000 205.0 200.0 33.0
TPS78101DRVT WSON DRV 6 250 205.0 200.0 33.0
TPS78101DRVT WSON DRV 6 250 203.0 203.0 35.0
TPS781330220DRVR WSON DRV 6 3000 205.0 200.0 33.0
TPS781330220DRVR WSON DRV 6 3000 203.0 203.0 35.0
TPS781330220DRVT WSON DRV 6 250 200.0 183.0 25.0
TPS781330220DRVT WSON DRV 6 250 205.0 200.0 33.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRV 6 WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006A SCALE 5.500
WSON - 0.8 mm max height
2.1 A
B
1.9
PIN 1 INDEX AREA

2.1
1.9
0.8
0.7 C
SEATING PLANE
0.08 C
(0.2) TYP
1 0.1 0.05
EXPOSED 0.00
THERMAL PAD
3
4
2X
7
1.3 1.6 0.1
6
1
4X 0.65
0.35
6X
PIN 1 ID 0.3 0.25
6X
(OPTIONAL) 0.2 0.1 C A B
0.05 C
4222173/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006A WSON - 0.8 mm max height
6X (0.45)
(1)
1 7
6X (0.3) 6
SYMM (1.6)
(1.1)
4X (0.65)
4
3
(R0.05) TYP SYMM
( 0.2) VIA
TYP (1.95)
LAND PATTERN EXAMPLE

SCALE:25X
0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND
SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
DEFINED SOLDER MASK
(PREFERRED) DEFINED
SOLDER MASK DETAILS
4222173/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006A WSON - 0.8 mm max height
SYMM
6X (0.45)
METAL
1 7
6X (0.3) 6
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4222173/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DRV0006D SCALE 5.500
WSON - 0.8 mm max height
2.1 A
B
1.9
PIN 1 INDEX AREA

2.1
1.9
0.8
0.7 C
SEATING PLANE
0.08 C
(0.2) TYP
1 0.1 0.05
EXPOSED 0.00
THERMAL PAD
3
4
2X
7
1.3 1.6 0.1
6
1
4X 0.65
0.35
6X
PIN 1 ID 0.3 0.25
6X
(OPTIONAL) 0.2 0.1 C A B
0.05 C
4225563/A 12/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006D WSON - 0.8 mm max height
6X (0.45)
(1)
1 7
6X (0.3) 6
SYMM (1.6)
(1.1)
4X (0.65)
4
3
(R0.05) TYP SYMM
( 0.2) VIA
TYP (1.95)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:25X
0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND
EXPOSED EXPOSED
METAL METAL
SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
DEFINED SOLDER MASK
(PREFERRED) DEFINED
SOLDER MASK DETAILS
4225563/A 12/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006D WSON - 0.8 mm max height
SYMM
6X (0.45)
METAL
1 7
6X (0.3) 6
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4225563/A 12/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
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applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated

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TPS781 Series

www.ti.com ........................................................................................................................................................... SBVS102B – MARCH 2008 – REVISED MAY 2008

150mA, Low-Dropout Regulator, Ultralow-Power, IQ 1µA

SBVS102B – MARCH 2008 – REVISED MAY 2008 ........................................................................................................................................................... www.ti.com

ORDERING INFORMATION (1) (2)

ABSOLUTE MAXIMUM RATINGS (1)

2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated

www.ti.com ........................................................................................................................................................... SBVS102B – MARCH 2008 – REVISED MAY 2008

Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 3

SBVS102B – MARCH 2008 – REVISED MAY 2008 ........................................................................................................................................................... www.ti.com

FUNCTIONAL BLOCK DIAGRAM

Table 1. TERMINAL FUNCTIONS

4 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated

www.ti.com ........................................................................................................................................................... SBVS102B – MARCH 2008 – REVISED MAY 2008

LINE REGULATION LINE REGULATION

LINE REGULATION LINE REGULATION

LINE REGULATION LOAD REGULATION

Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 5

SBVS102B – MARCH 2008 – REVISED MAY 2008 ........................................................................................................................................................... www.ti.com

TYPICAL CHARACTERISTICS (continued)

LOAD REGULATION LOAD REGULATION

DROPOUT VOLTAGE vs OUTPUT CURRENT DROPOUT VOLTAGE vs OUTPUT CURRENT

VDO (VIN - VOUT) (mV)

DROPOUT VOLTAGE vs TEMPERATURE DROPOUT VOLTAGE vs TEMPERATURE

VDO (VIN - VOUT) (mV)

6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated

www.ti.com ........................................................................................................................................................... SBVS102B – MARCH 2008 – REVISED MAY 2008

TYPICAL CHARACTERISTICS (continued)

Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 7

SBVS102B – MARCH 2008 – REVISED MAY 2008 ........................................................................................................................................................... www.ti.com

TYPICAL CHARACTERISTICS (continued)

SHUTDOWN CURRENT vs INPUT VOLTAGE CURRENT LIMIT vs INPUT VOLTAGE

Current Limit (mA)

CURRENT LIMIT vs INPUT VOLTAGE CURRENT LIMIT vs INPUT VOLTAGE

Current Limit (mA)

270 TJ = -40°C 270 TJ = -40°C

FEEDBACK PIN CURRENT vs TEMPERATURE VSET PIN CURRENT vs INPUT VOLTAGE

TJ = +85°C TJ = -40°C TJ = +25°C

8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated

www.ti.com ........................................................................................................................................................... SBVS102B – MARCH 2008 – REVISED MAY 2008

TYPICAL CHARACTERISTICS (continued)

ENABLE PIN HYSTERESIS vs TEMPERATURE ENABLE PIN HYSTERESIS vs TEMPERATURE

Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 9

SBVS102B – MARCH 2008 – REVISED MAY 2008 ........................................................................................................................................................... www.ti.com

TYPICAL CHARACTERISTICS (continued)

%ΔVOUT vs TEMPERATURE %ΔVOUT vs TEMPERATURE

%ΔVOUT vs TEMPERATURE OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY

RIPPLE REJECTION vs FREQUENCY

10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated

www.ti.com ........................................................................................................................................................... SBVS102B – MARCH 2008 – REVISED MAY 2008

TYPICAL CHARACTERISTICS (continued)

OUTPUT VOLTAGE vs ENABLE (SLOW RAMP) INPUT VOLTAGE vs DELAY TO OUTPUT

Time (20ms/div) Time (1ms/div)

LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE

Time (200ms/div) Time (200ms/div)

LOAD TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE

VIN Enable Enable

IOUT = 0mA to 10mA Load Load

Time (5ms/div) Time (2ms/div)