K.L.E.

Society’s
K.L.E. INSTITUTE OF TECHNOLOGY, HUBBALLI
Dept of Electronics and Communication Engineering

Course Plan
FMTC0302 /Rev 2.1
Semester: III Year: 2020-21

Course Title: ELECTRONIC DEVICES Course Code: 18EC33

Total Contact Hours: 40 Duration of USE: 03 Hrs.
SEE Marks: 60 CIE Marks: 40
Lesson Plan Author: Dr. R. L. Itagi Date: 28-08-2020
Checked By: Dr. Manu T. M. Date: 08-08-2020

Prerequisites

Atomic structure of materials.

Course Outcomes-(CO)
At the end of this course student will be able to:

18EC33.1 Interpret the principles of semiconductor Physics.

18EC33.2 Describe the principles and characteristics of different types of semiconductor
devices.
18EC33.3 Explain the fabrication process of semiconductor devices.
18EC33.4 Apply the mathematical models of semiconductor junctions and MOS transistors for
circuits and systems.

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 K.L.E. Society’s
K.L.E. INSTITUTE OF TECHNOLOGY, HUBBALLI
Dept of Electronics and Communication Engineering

Mapping of Course Outcomes (CO) with Program outcomes (PO) and Program Specific
Outcomes (PSO)

Course Title: Electronic Devices Course code: 18EC33

Semester: III Year: 2020-21

Course PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1
Outcomes (CO)
18EC33.1
Understand the
principles of 2 3 - - - - - - 1 1 - - 3
semiconductor
Physics.
18EC33.2
Understand the
principles and
characteristics of 2 3 1 - - - - - 1 1 - - 3
different types of
semiconductor
devices.
18EC33.3
Understand the
fabrication
1 2 - - - - - - 1 1 - - 2
process of
semiconductor
devices.
18EC33.4
Utilize the
mathematical
models of
semiconductor 1 2 1 - - - - - 1 1 - - 3
junctions and
MOS transistors
for circuits and
systems.
Average 2 3 1 - - - - - 1 1 - - 3
Degree of compliance 1: Slight 2: Moderate 3: Substantial

PSO1: Analyze, design, build and test analog, digital, communication and embedded systems
for a given specifications.

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 K.L.E. Society’s
K.L.E. INSTITUTE OF TECHNOLOGY, HUBBALLI
Dept of Electronics and Communication Engineering

Course Content
Course Code: 18EC33 Course Title: Electronic Devices

L-T-P: 4-0-0 Teaching Hrs: 40 SEE Duration:03

CIE Marks: 40 SEE Marks: 60 Total Marks: 100

Module
Contents Hrs.
No.
Semiconductors: Bonding forces in solids, Energy bands, Metals, Semiconductors
and Insulators, Direct and Indirect semiconductors, Electrons and Holes, Intrinsic
1 and Extrinsic materials, Conductivity and Mobility, Drift and Resistance, Effects of 8
temperature and doping on mobility, Hall Effect.
(Text 1: 3.1.1, 3.1.2, 3.1.3, 3.1.4, 3.2.1, 3.2.3, 3.2.4, 3.4.1, 3.4.2, 3.4.3, 3.4.5)

P-N Junctions: Forward and Reverse biased junctions- Qualitative description of

Current flow at a junction, reverse bias, Reverse bias breakdown- Zener breakdown,
avalanche breakdown, Rectifiers. (Text 1: 5.3.1, 5.3.3, 5.4, 5.4.1, 5.4.2, 5.4.3)
2 Optoelectronic Devices Photodiodes: Current and Voltage in an Illuminated 8
Junction, Solar Cells, Photodetectors. Light Emitting Diode: Light Emitting
materials. (Text 1: 8.1.1, 8.1.2, 8.1.3, 8.2, 8.2.1)

Bipolar Junction Transistor: Fundamentals of BJT operation, Amplification with

BJTS, BJT Fabrication, The coupled Diode model (Ebers-Moll Model), Switching
operation of a transistor, Cut-off, saturation, switching cycle, specifications, Drift in
3 8
the base region, Base narrowing, Avalanche breakdown, Base Resistance and
Emitter crowding.
(Text 1: 7.1, 7.2, 7.3, 7.5.1, 7.6, 7.7.1, 7.7.2, 7.7.3, 7.7.5)

Field Effect Transistors: Basic p-n JFET Operation, Equivalent Circuit and
Frequency Limitations, MOSFET- Two terminal MOS structure- Energy band
4 diagram, Ideal Capacitance – Voltage Characteristics and Frequency Effects, Basic 8
MOSFET Operation- MOSFET structure, Current-Voltage Characteristics.
(Text 2: 9.1.1, 9.4, 9.6.1, 9.6.2, 9.7.1, 9.7.2, 9.8.1, 9.8.2)

Fabrication of p-n junctions: Thermal Oxidation, Diffusion, Rapid Thermal

Processing, Ion implantation, chemical vapour deposition, photolithography,
5 Etching, metallization. (Text 1: 5.1) 8
Integrated Circuits: Background, Evolution of ICs, CMOS Process Integration,
Integration of Other Circuit Elements. (Text 1: 9.1, 9.2, 9.3.1, 9.3.2).
Text Books:
1. Ben G. Streetman, Sanjay Kumar Banergee, “Solid State Electronic Devices”, 7th
Edition, Pearson Education, 2016, ISBN 978-93-325-5508-2.
2. Donald A Neamen, Dhrubes Biswas, “Semiconductor Physics and Devices”,
4thEdition, MCGraw Hill Education, 2012, ISBN 978-0-07-107010-2.
Reference Books:
1. S. M. Sze, Kwok K. Ng, “Physics of Semiconductor Devices”, 3rd Edition, Wiley, 2018.
2. A. Bar-Lev, “Semiconductor and Electronic Devices”, 3rd Edition, PHI, 1993.

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 K.L.E. Society’s
K.L.E. INSTITUTE OF TECHNOLOGY, HUBBALLI
Dept of Electronics and Communication Engineering

Evaluation Scheme

IA Exam Scheme:
Assessment Weightage in Marks

Internal Assessment 1 10

Internal Assessment 2 10
Internal Assessment 3 10
Average of all the three IAs 30
Avg. Unit Test Marks (2-unit tests) 02
Avg. Quiz Marks (4-Quizzes) 04
Assignment (Module 1, 2, 3, 4) 04

Final Internal Assessment 40

Course Unitization for Internal Assessment Exams and University Semester Examination
No. of Questions in No. of
Teaching
Module Chapter Questions
Hours IA1 IA2 IA3
in SEE
1 Semiconductors 8 1+1/2 2

2 P-N Junctions 8 1+1/2 2

Bipolar Junction 8
3 1+1/2 2
Transistor
8
4 Field Effect Transistors 1+1/2 1+1/2 2

Fabrication of p-n 8
5 junctions, Integrated 1+1/2 2
Circuits

Note*
For I.A.:
• Each IA is conducted for 40 marks and reduced to 10 marks.
• 2 unit tests are conducted (Any 2 modules)
• 3 Questions carrying 20 marks each and up to 4 sub questions are allowed.
• Student has to answer any 2 full questions of 20 marks each (Two full questions from Q1,Q2 and Q3)

For S.E.E.:
• The question paper will have ten questions.
• Each full question is for 20 marks.
• There will be 2 full questions (with a maximum of four sub questions in one full question) from each
module.
• Each full question with sub questions will cover the contents under a module.
• Students will have to answer 5 full questions, selecting one full question from each module.

Date: Head of Department

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 K.L.E. Society’s
K.L.E. INSTITUTE OF TECHNOLOGY, HUBBALLI
Dept of Electronics and Communication Engineering

Module wise Plan

Course Code and Title: 18EC33- Electronic Devices
Module 1: Semiconductors Planned Hours: 8

Learning Outcomes:

At the end of the topic student should be able to:

Sr. No. TLOs COs BL
1 Define bonding forces and energy bands to categorize materials into 1 L1
conductors, semiconductors and insulators.
2 Interpret the drift current in extrinsic material in terms of conductivity 1 L2
and mobility. Discuss Hall effect.

Lesson Schedule
Class No. Portion covered per hour
1. Overview of the course
2. Bonding forces in solids, Energy bands
3. Metals, Semiconductors and Insulators, Direct and Indirect semiconductors
4. Electrons and Holes, Intrinsic and Extrinsic materials
5. Conductivity and Mobility
6. Drift and Resistance
7. Effects of temperature and doping on mobility
8. Hall Effect

Review Questions
Sr. No. Questions TLO BL

1 Explain how materials are categorized as conductors, semiconductors and insulators using 1 L1
(i) bonding forces (ii) using energy band diagram.

2 Describe intrinsic and extrinsic materials. Explain majority and minority carriers in 1 L1
extrinsic materials.

3 Obtain expressions for current density, conductivity and mobility in a solid. 2 L2

4 Describe Hall effect and give the applications of Hall effect. 2 L2

5 A new semiconductor has Nc=1019cm-3, Nv=5x1018cm-3 and Eg=2eV. It is doped with 2 L3

1017 donors (fully ionized), calculate the electron. Hole and intrinsic carrier
concentrations at 627o C. Sketch the simplified band diagram showing the position of
EF.

6 A Si bar 1µm long and 100 µm2 in cross-sectional are is doped with 1017 cm-3 2 L3
phosphorus. Find the current at 300 K with 10V applied. How long does it take an
electron to drift 1 µm in pure Si at an electric field of 100V/cm?

7 Consider a bar with w=0.1 mm, t=10 µm, and L=5mm. For B=10KG in the direction 2 L3
from center of slab upwards, and a current of 1mA, we have V AB=-2mV and
VCD=100mV. Find the type, concentration, and mobility of the majority carrier.

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 K.L.E. Society’s
K.L.E. INSTITUTE OF TECHNOLOGY, HUBBALLI
Dept of Electronics and Communication Engineering

Course Code and Title: 18EC33 - Electronic Devices

Module 2: P-N Junctions Planned Hours: 8

Learning Outcomes:
At the end of the topic student should be able to:
Sr. No. TLOs COs BL
1 Describe the current flow in a p-n junction and diode application as rectifier. 1, 4 L2

2 Discuss breakdown mechanisms in p-n junction: Zener and avalanche. 1 L1

4 Discuss the operating principle of special p-n junctions. 2 L1

Lesson Schedule
Class No. Portion covered per hour
1. Forward and Reverse biased junctions- Qualitative description of Current flow at a junction
2. Reverse bias, Reverse bias breakdown- Zener breakdown, avalanche breakdown
3. Rectifiers
4. Rectifiers
5. Optoelectronic Devices Photodiodes: Current and Voltage in an Illuminated Junction
6. Photodetectors
7. Solar Cells
8. Light Emitting Diode: Light Emitting materials

Review Questions
Sr. No. Questions TLO BL
1 Give the qualitative description of current in a p-n junction. 1 L2

2 An abrupt Si p-n junction has the following properties at 300 K: 1 L3

p side: Na= 1017cm-3, τn = 0.1 µs, µp=200cm2/V-s, µn=700

and n side: Nd= 1017cm-3, τp = 0.1 µs, µn=1300cm2/V-s, µp=450
The junction is forward biased by 0.5 V. What is the forward current? What
is the current at a reverse bias of -0.5 V?

3 A Si solar cell has a short circuit current of 100 mA and an open-circuit 3 L3

voltage of 0.8 V under full solar illumination. The fill factor is 0.7. What is
the maximum power delivered to a load by this cell?

4 Sketch the voltage across a 1 kΩ resistor in series with a diode (offset 0.4 V, 1 L3
resistance 400 Ω) and a voltage source of 2 sin wt.

5 In a p+-n junction with n-doping changed from Nd to 2Nd, describe the changes 1, 2 L3

in junction capacitance, built-in potential, breakdown voltage, and ohmic

losses.

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 K.L.E. Society’s
K.L.E. INSTITUTE OF TECHNOLOGY, HUBBALLI
Dept of Electronics and Communication Engineering

Course Code and Title: 18EC33- Electronic Devices

Module 3: Bipolar Junction Transistor Planned Hours: 8

Learning Outcomes:

At the end of the topic student should be able to:

Sr. No. TLOs Cos BL
1 Describe the working principle of BJT and its amplification and switching 2, 4 L2
operation.
2 Explain the fabrication process of BJT. 3 L1

Lesson Schedule
Class No. Portion covered per hour
1. Fundamentals of BJT operation
2. Amplification with BJTS
3. BJT Fabrication
4. The coupled Diode model (Ebers-Moll Model)
5. Switching operation of a transistor, cutoff, saturation
6. Switching cycle, specifications
7. Drift in the base region, Base narrowing
8. Avalanche breakdown, Base Resistance and Emitter crowding

Review Questions
Sr. No. Questions TLO BL
1 Sketch the ideal collector characteristics for the transistor in circuit with V CC=10 V 1 L3
and RC=50 kΩ. Let iB vary from zero to 0.2 mA. Draw a load line on the resulting
characteristics and find the steady state value of VCE.

2 Explain BJT operation with different current components present in transistor. 1 L1

3 Explain how amplification takes place in a BJT circuit. 1 L2

4 Describe active region, saturation region and cut-off region in a transistor. 1 L1

5 Discuss base narrowing. 1 L1

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 K.L.E. Society’s
K.L.E. INSTITUTE OF TECHNOLOGY, HUBBALLI
Dept of Electronics and Communication Engineering

Course Code and Title: 18EC33- Electronic Devices

Module 4: Field Effect Transistors Planned Hours: 8

Learning Outcomes:

At the end of the topic student should be able to:

Sr. No. TLOs Cos BL
1 Describe the working principle of JFET and MOSFET. 2 L2
2 Explain the structure of MOSFET. 3 L1

Lesson Schedule
Class No. Portion covered per hour
1. Basic JFET Operation
2. Equivalent Circuit and Frequency Limitations
3. MOSFET- Two terminal MOS structure
4. Energy band diagram
5. Voltage Characteristics
6. Ideal Capacitance –and Frequency Effects
7. Basic MOSFET Operation- MOSFET structure
8. Current-Voltage Characteristics

Review Questions

Sr. No. Questions TLO BL

1 Explain JFET operation. 1 L2
2 Give the equivalent circuit of JFET and mention frequency limitations. 1 L1

Explain MOSFET operation. 2 L2

3
Discuss energy band diagram and ideal capacitance in MOSFET. 2 L2
4
Explain current-voltage characteristics of MOSFET. 2 L2
5

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 K.L.E. Society’s
K.L.E. INSTITUTE OF TECHNOLOGY, HUBBALLI
Dept of Electronics and Communication Engineering

Course Code and Title: 18EC33- Electronic Devices

Module 5: Fabrication of p-n junctions, Integrated Circuits Planned Hours: 8

Learning Outcomes:

At the end of the topic student should be able to:

Sr. No. TLOs COs BL
1 Describe the fabrication process of p-n junction. 3 L1

2 Discuss IC fabrication and CMOS ICs. 3 L2

Lesson Schedule
Class No. Portion covered per hour
1. Fabrication of p-n junctions: Thermal Oxidation, Diffusion
2. Rapid Thermal Processing, Ion implantation
3. Chemical vapour deposition, photolithography
4. Etching, metallization
5. Integrated Circuits: Background, Evolution of ICs
6. CMOS Process Integration
7. Integration of Other Circuit Elements
8. Contd.

Review Questions
Sr. No. Questions TLO BL

1. Explain fabrication of p-n junction using thermal oxidation. 1 L2

2. Explain fabrication of p-n junction using diffusion process. 1 L2

3. Explain rapid thermal processing in fabrication of p-n junction. 1 L2

4. Explain ion implantation and chemical vapour deposition in fabrication of p-n 1 L2
junction.
5. Explain photolithography and its applications. 1 L2
6. What is etching in p-n junction fabrication? What materials are used for this 1 L2
process?
7. Describe steps used for CMOS process integration in brief. 2 L2
8. Explain how integration of circuit elements is done in IC. 2 L2

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 K.L.E. Society’s
K.L.E. INSTITUTE OF TECHNOLOGY, HUBBALLI
Dept of Electronics and Communication Engineering

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 K.L.E. Society’s
K.L.E. INSTITUTE OF TECHNOLOGY, HUBBALLI
Dept of Electronics and Communication Engineering

First IA Test
Sem/Div: III A and B
Sub: Electronic Devices Date: 09/09/2019
Sub Code: 18EC33 Time: 11.30 am-12.45 pm
Faculty Incharge: R. L. Itagi Max Marks: 40
Note: 1) Answer any two questions.
2) All questions carry equal marks.
Q. Sub Question Marks BL CO
No. Qtn.
a. State the differences between direct bandgap and indirect bandgap
semiconductor materials. In optical communication system, it is
06 L1 1
desired to have p-n junctions with radiative recombination. Mention
1 which one of the above you suggest to use.
b. Discuss the properties of p and n type semiconductor with energy
06 L2 1
band diagram at absolute zero temperature and at room temperature.
c. Explain the three types of bonding forces in solids. 08 L2 1

a. Write and explain the diode current equation with the help of I-V
characteristic. 04 L2 2
b. Draw the circuit of a Zener voltage regulator circuit. Mark the
currents IS, IZ and IL, and using the relation between these currents,
06 L1 2
explain how line and load regulation are done in a Zener voltage
regulator circuit.
2
c. Derive expressions for total current and open circuit voltage in a
08 L2 2
photodiode. Define photovoltaic effect and state its application.
d. A solar cell has dark saturation current of 5 nA and short circuit
current when illuminated is 200 mA. The fill factor is 0.5 and the
02 L3 2
maximum power delivered is 60 mW. Calculate the open circuit
voltage.

a. What is meant by carrier injection in transistor operation? Explain 06

using a n-p-n or a p-n-p transistor. State the bias conditions for L1 2
transistor operation in forward active region.
b. Using suitable values for base and collector current calculations,
04 L2 2
explain how a transistor is used as an amplifier.
c. Draw the dc load line for the transistor circuit with VCC=40 V and
02 L2 2
3 RC=5 kΩ for a n-p-n transistor.
d. Compare the I-V characteristics of (i) a rectifier diode (ii) zener
diode (iii) photodiode.
What is the bias given to p-n junction in each case? Discuss the
operating mode in each case, with a mention of their application. 08 L2 2

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 K.L.E. Society’s
K.L.E. INSTITUTE OF TECHNOLOGY, HUBBALLI
Dept of Electronics and Communication Engineering

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 K.L.E. Society’s
K.L.E. INSTITUTE OF TECHNOLOGY, HUBBALLI
Dept of Electronics and Communication Engineering

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