Obe Curriculum For The Course: RGPV (Diploma Wing) Bhopal
Obe Curriculum For The Course: RGPV (Diploma Wing) Bhopal
Obe Curriculum For The Course: RGPV (Diploma Wing) Bhopal
Method of External
Assessment
Learning Outcome Solve equation using Boolean algebra and K- 08 10
4 map.(Cognitive)
Boolean Algebra-Rules and Laws of Boolean Algebra, De-Morgan’s
Theorem. Duality Theorem
Introduction to logic design with Karnaugh map
Contents Simplification of Boolean Function up-to 4 variables(2,3,4 variable), Don’t
Care Condition
Boolean Representation-Sum of Product and product of Sum, Min Term and
Max term
Method of External
Assessment
Learning Outcome Implement and verify truth table of given logic gates 06 15
5 and Boolean equation. (Psychomotor)
Verify truth table of NOT and, OR, EX-OR, EXNOR, NOR, NANDgates.
Implement AND, OR and NOT gate using NOR and NAND gate and
Contents verifytruth table.
Implement and verify truth table of De-Morgan’s theorem.
Implement simple Boolean equation using gates and verifyoutput.
Method of Internal
Assessment
RGPV (DIPLOMA OBE CURRICULUM Sheet
WING) BHOPAL FOR THE COURSE FORMAT- 3 No. 3/5
Method of Internal
Assessment
Learning Outcome Compare the characteristics of different logic 08 10
10 families.(Cognitive)
Characteristics of Logic Families –Power Dissipation, Speed, Fan in Fan Out,
Propagation delay Time
Contents
logic Families –RTL, DTL, IIL, ECL, MOS
Analysis of open collector and tri –state Logic
External
Method of
Assessment
FORMAT-
RGPV (DIPLOMA OBE CURRICULUM Sheet
WING) BHOPAL FOR THE COURSE 3 No. 5/5
Method of External
Assessment
Learning Outcome Explaindifferent types ofshift register and counter. 06 10
12 (Cognitive)
Registers, Shift Register, types of Shift Register-SISO, SIPO, PISO, PIPO
Contents
Counters-Basics of counter and its applications
Method of External
Assessment
Learning Outcome Design and Implement given SequentialLogic Circuits and 08 15
13 verify it.(Psychomotor)
Verify truth table of RS, JK, D and T flip-flop.
Design and Implement Shift registers using D flip-flop
Contents
Design and Implement ripple counter using J-K flip-flop
Design and Implement synchronous counter using J-K flip-flops.
Method of Internal
Assessment
SuggestedListofExperiments:
1. Study and Verify the truth table of logic gates (74xx series).
2. Realization of AND, OR, NOT and Ex-OR logic gates using NAND and NOR gate
13. Verification of truth table of RS, JK, D and Tflip flop using IC’s.
1.
2.
3.
4.
5.
6.
7.
CO LO
SCHEME FOR LEARNING Branch Code Course Code
Code Code
RGPV (Diploma Wing ) Bhopal
OUTCOME C 0 2 0 1 1
Format No. 4
COURSE NAME Digital Technique
CO Description Perform conversion among different number systems, and became familiar with basic codes used in digital computer.
RGPV (Diploma Wing ) Bhopal SCHEME FOR LEARNING Branch Code Course Code CO LO
Code Code
OUTCOME
C 0 2 0 2 3
COURSE NAME Digital Technique
CO Description Design simple Logic Circuit with logic gates by applying Boolean laws and rules on expression.
LO Description Draw symbol andwrite truth table & logical expression for allthe gates.
SCHEME OF STUDY
Teaching –
Teach Pract.
S. No. Learning Content Learning Description of T-L Process LRs Required Remarks
Hrs. /Tut Hrs.
Method
LO-03 Logic Gates: Basic concepts of Interactive Teacher will explain the 07 -- Text Books, PPT,
Diode/transistor switch circuit, Logic classroom contents and provide Handouts, chalk
Gates Symbols, Truth Table and lecture, PPT, handouts to students. Teacher board, charts, Video
Logical expression of Basic logic demonstration, will conduct assignments/ lecture- NPTEL and
gates-AND, OR, NOT Universal others.
quiz,assignment quiz/tutorial to make students
Gates-NAND and NOR Special s, tutorial practice their knowledge.
Purpose Gates-EX-OR, EX-NOR
Realization of All Other Gates Using
Universal Gates
SCHEME OF ASSESSMENT
Maximu External /
S. No. Method of Assessment Description of Assessment Resources Required
m Marks Internal
LO Description Implement and verify truth table of given logic gates and Boolean equation.
SCHEME OF STUDY
Teaching –
Teach Pract. /
S. No. Learning Content Learning Description of T-L Process LRs Required Remarks
Hrs. Tut Hrs.
Method
LO-05 Verify truth table of NOT and, Lab Teacher with support from lab 06 Lab manual, charts,
OR, EX-OR, EXNOR, NOR, demonstration, staff will demonstrate the Handouts, experimental
NANDgates. PPT , hands on trainer instruments/kit
procedure of lab experiments.
Implement AND, OR and NOT practice, lab
assignments. Student will conduct lab with measuring
gate using NOR and NAND instruments, computer
assignment based on these
gate and verifytruth table.
experiments. with relevant simulation
Implement and verify truth
software and high speed
table of De-Morgan’s
theorem.
internet.
Implement simple Boolean
equation using gates and
verifyoutput
SCHEME OF ASSESSMENT
Maximum External /
S. No. Method of Assessment Description of Assessment Resources Required
Marks Internal
Student will be asked to
1. Verify the truth table of given logic gate
LO-05 Practical test in laboratory 15 Rubrics, Rating scale Internal
2. Implement logic gate using universal gate.
3. Verify De-Morgan’s theorem.
ADDITIONAL INSTRUCTIONS FOR THE HOD/ FACULTY (IF ANY)
CO LO
SCHEME FOR LEARNING Branch Code Course Code
Code Code
RGPV (Diploma Wing ) Bhopal
OUTCOME C 0 2 0 3 6
Format No. 4
COURSE NAME Digital Technique
Learn the minimization techniques to simplify the hardware requirements of digital circuit and understand the design of Combinational
CO Description
circuit.
LO Description Design Adder, Subtractor. Encoder and Decoder circuits
SCHEME OF STUDY
Teaching – Tea Pract.
S. No. Learning Content Learning Description of T-L Process ch / Tut LRs Required Remarks
Method Hrs. Hrs.
LO-06 Half adder, Full adder Interactive Teacher will explain the 07 -- Text Books, PPT,
Half Subtractor and Full Subtractor classroom lecture, contents and provide handouts Handouts, chalk
Basics of Encoder, Decimal to BCD Encoder PPT, Video, to students. Teacher will board, charts,
Basics of Decoder, BCD -to -Seven Segments demonstration, conduct assignments/ Video lecture-
Decoder. quiz, assignments. quiz/tutorial to make students NPTEL and others.
practice their knowledge.
SCHEME OF ASSESSMENT
Method of Maximum External /
S. No. Description of Assessment Resources Required
Assessment Marks Internal
CO LO
SCHEME FOR LEARNING Branch Code Course Code
Code Code
RGPV (Diploma Wing ) Bhopal
OUTCOME C 0 2 0 3 7
Format No. 4
COURSE NAME Digital Technique
CO Description Learn the minimization techniques to simplify the hardware requirements of digital circuit and understand the design of Combinational circuit.
CO LO
SCHEME FOR LEARNING Branch Code Course Code
Code Code
RGPV (Diploma Wing ) Bhopal
OUTCOME C 0 2 0 3 8
Format No. 4
COURSE NAME Digital Technique
CO Description Learn the minimization techniques to simplify the hardware requirements of digital circuit and understand the design of Combinational circuit.
Implement and verify given combinational logic circuits.
LO Description
SCHEME OF STUDY
Teaching – Description of T-L Teach Pract. /
S. No. Learning Content LRs Required Remarks
Learning Method Process Hrs. Tut Hrs.
LO-08 Implement and verify truth table of Lab demonstration, Teacher with support 06 Lab manual, charts,
Half & Full adder, Half & Full PPT , hands on from lab staff will Handouts, experimental
Subtractor. practice, lab trainer instruments /kit
demonstrate the
Verify truth table of 4:1 Multiplexer, assignments.
procedure of lab with measuring
1:4 De-multiplexer
experiments. instruments, computer
Design and implement Decoder(2:4)
and Encoder(4:2) Student will conduct with relevant simulation
Study of Code converter and BCD lab assignment based software and high speed
adder. on these experiments. internet.
SCHEME OF ASSESSMENT
Maximu External /
S. No. Method of Assessment Description of Assessment Resources Required
m Marks Internal
Student will be asked to
1. Verify the given Adder/Subtractor circuit.
LO-09 Practical test in laboratory 2. Verify the given Multiplexer/De-multiplexer. 20 Rubrics, Rating scale External
& encoder.
CO LO
SCHEME FOR LEARNING Branch Code Course Code
Code Code
RGPV (Diploma Wing ) Bhopal
OUTCOME C 0 2 0 4 9
Format No. 4
COURSE NAME Digital Technique
CO Description Obtain basic knowledge of logic families for implement logics within integrated circuit.
SCHEME OF STUDY
Teaching –
Description of T-L Teach Pract.
S. No. Learning Content Learning LRs Required Remarks
Process Hrs. /Tut Hrs.
Method
LO-9 Introduction to Digital Integrated Interactive Teacher will explain the 07 -- Text Books, PPT,
Circuits classroom contents and provide Handouts, chalk
Characteristics of Digital IC’s lecture, PPT, handouts to students. board, charts, Video
Video, Teacher will conduct lecture- NPTEL and
demonstration, assignments/ quiz / tutorial others.
quiz, to make students practice
assignments. their knowledge.
SCHEME OF ASSESSMENT
External /
S. No. Method of Assessment Description of Assessment Maximum Marks Resources Required
Internal
Student will be asked to (and/or): Question paper,
Mid Semester Theory
LO-9 1. Explain the digital integrated circuits. 10 Internal
Exam Rating scale.
2. Draw the Characteristics of Digital IC’s.
CO LO
SCHEME FOR LEARNING Branch Code Course Code
Code Code
RGPV (Diploma Wing ) Bhopal
OUTCOME C 0 2 0 4 10
Format No. 4
COURSE NAME Digital Technique
CO Description Obtain basic knowledge of logic families for implement logics within integrated circuit.
CO LO
SCHEME FOR LEARNING Branch Code Course Code
Code Code
RGPV (Diploma Wing ) Bhopal
OUTCOME C 0 2 0 5 11
Format No. 4
COURSE NAME Digital Technique
CO Description Understand the design of Sequential Circuits such as Flip Flop, Registers and Counters.
CO LO
SCHEME FOR LEARNING Branch Code Course Code
Code Code
RGPV (Diploma Wing ) Bhopal
OUTCOME C 0 2 0 5 12
Format No. 4
COURSE NAME Digital Technique
CO Description Understand the design of Sequential Circuits such as Flip Flop, Registers and Counters.
CO LO
SCHEME FOR LEARNING Branch Code Course Code
Code Code
RGPV (Diploma Wing ) Bhopal
OUTCOME C 0 2 0 5 13
Format No. 4
COURSE NAME Digital Technique
CO Description Understand the design of Sequential Circuits such as Flip Flop, Registers and Counters.
SCHEME OF STUDY
Teaching –
Description of T-L Teach Pract.
S. No. Learning Content Learning LRs Required Remarks
Process Hrs. /Tut Hrs.
Method
LO-13 Verify truth table of RS, JK, D and T Lab Teacher with support -- 08 Lab manual, charts,
flip-flop. demonstration, from lab staff will Handouts,
Design and Implement Shift PPT , hands on demonstrate the experimental trainer
registers using D flip-flop practice, procedure of lab instruments/kit with
Design and Implement ripple labassignments. experiments. measuring
counter using J-K flip-flop
Design and Implement synchronous Student will conduct lab instruments,
counter using J-K flip-flops. assignment based on computer with
these experiments. relevant simulation
software and high
speed internet.
SCHEME OF ASSESSMENT
Maximu External /
S. No. Method of Assessment Description of Assessment Resources Required
m Marks Internal
2
NOTE: Max. Marks for Internal Assessment Practical Component is 30. Marks obtained by the students will be
proportionately reduced to 20 , while processing the result.
NOTE: End Sem Practical Examination should be conducted for a Max Marks of 30