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    Assignments Week09 Solution

    Uploaded by

    Samuel Adamu
    This document provides the solutions to 10 assignments testing concepts in digital circuit fault testing. The assignments cover topics like the differences between verification and testing, sources of transient faults, calculating the number of stuck-at faults in different logic gates, detecting transistor stuck-open faults, equivalent faults, fault dominance, parallel fault simulation, and determining the output fault list given input fault lists.

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    Assignments Week09 Solution

    Uploaded by

    Samuel Adamu
    42 views3 pages
    This document provides the solutions to 10 assignments testing concepts in digital circuit fault testing. The assignments cover topics like the differences between verification and testing, sources of transient faults, calculating the number of stuck-at faults in different logic gates, detecting transistor stuck-open faults, equivalent faults, fault dominance, parallel fault simulation, and determining the output fault list given input fault lists.

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    This document provides the solutions to 10 assignments testing concepts in digital circuit fault testing. The assignments cover topics like the differences between verification and testing, sources of transient faults, calculating the number of stuck-at faults in different logic gates, detecting transistor stuck-open faults, equivalent faults, fault dominance, parallel fault simulation, and determining the output fault list given input fault lists.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    42 views3 pages

    Assignments Week09 Solution

    Uploaded by

    Samuel Adamu
    This document provides the solutions to 10 assignments testing concepts in digital circuit fault testing. The assignments cover topics like the differences between verification and testing, sources of transient faults, calculating the number of stuck-at faults in different logic gates, detecting transistor stuck-open faults, equivalent faults, fault dominance, parallel fault simulation, and determining the output fault list given input fault lists.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 3

    Solutions to Assignments for Week 9

    1. Which of the following statements is false?


    a. We carry out testing on all the manufactured devices.
    b. Verification guarantees the quality of the manufactured
    device.
    c. Verification has to be done prior to testing.
    d. None of the above.
    Correct answer is (b).
    Testing guarantees the quality of the manufactured
    devices, while verification guarantees the quality of the
    design.
    2. Which of the following are sources of transient fault in circuits?
    a. Loose connection in an interconnection.
    b. A MOS transistor is permanently non-conducting.
    c. Exposure of circuits (containing memories) to charged
    particles.
    d. All of the above.
    Correct answer is (c).
    (a) is an instance of intermittent fault, and (b) is an
    instance of permanent fault. When a circuit containing
    dynamic storage elements is exposed to charged particles,
    the particles penetrate the chip package and can discharge
    the capacitors that constitute the storage elements. This is
    an instance of transient fault; the circuit starts functioning
    properly again when the burst of charged particles stop.
    3. For a gate level netlist with 5 lines, the number of single and
    multiple stuck-at faults are:
    a. 10 and 242.
    b. 10 and 243.
    c. 32 and 242.
    d. 32 and 243.
    Correct answer is (a).
    Number of single stuck-at faults = 2 x 5 =10
    Number of multiple stuck-at faults = 3 5 – 1 = 242
    4. The number of test vectors to detect all single stuck-at faults
    in a 3-input NAND gate is:
    a. 4 **
    b. 5
    c. 6
    d. 8
    Correct answer is (a).
    The required test set is {011, 101, 110, 111}, i.e. 4 test
    vectors.
    5. The number of test vectors to detect all single stuck-at faults
    in a 10-input XOR gate is:
    a. 22
    b. 11
    c. 2
    d. 3
    Correct answer is (d).
    A possible test set can be {0000000000, 1111111111,
    0000000001}. The first test detects all stuck-at-1 faults in
    the inputs and also the output. The second test detects all
    stuck-at-0 faults in the inputs and stuck-at-1 fault in the
    output. The third test is necessary to detect stuck-at-0 fault
    in the output.
    6. Which of the following statements is true for transistor stuck-
    open faults in CMOS circuits?
    a. We have to measure the current flowing from VDD to
    GND.
    b. A pair of test patterns needs to be applied in sequence.
    c. A test set that detects all single stuck-at faults will also
    detect stuck-open faults.
    d. None of the above.
    Correct answer is (b).
    For detecting stuck-open faults, two-pattern test is
    required. The first vector initializes the output (load
    capacitance) to a known value, while the second vector
    activates the fault.
    A single vector cannot detect the fault, as the output value
    in presence of the fault may depend on the previous
    output.
    7. In a 3-input NOR gate, which set of faults are equivalent?
    a. Input lines stuck-at-1 and output stuck-at-1.
    b. Input lines stuck-at-0 and output stuck-at-1.
    c. Input lines stuck-at-0 and output line stuck-at-0.
    d. None of the above.
    Correct answer is (d).
    The equivalent faults are: {A/1, B/1, C/1, F/0}, where A, B,
    C are the inputs and F is the output.
    8. For a 3-input NAND gate with inputs A, B, C and output F,
    which of the following is true?
    a. F/0 dominates B/1.
    b. F/1 dominates A/1.
    c. F/0 dominates C/0.
    d. F/1 dominates B/1.
    Correct answer is (a).
    Tests that can detect B/1 are: {101}
    Tests that can detect F/0 are: {000, 001, 010, 011, 100,
    101, 110}
    Clearly, F/0 dominates B/1.
    9. Suppose we are carrying out parallel fault simulation with 50
    test vectors on a circuit with 100 faults. How many passes of
    simulation will be required (without fault dropping) on a
    machine with word size of 32 bits?
    a. 5000
    b. 200
    c. 157
    d. None of the above.
    In every pass of simulation, we can simulate with 31 faults,
    as one bit in the word has to be reserved for the fault-free
    response. So for 100 faults, we need 4 passes for every
    vector. For 50 test vectors, the number of passes will be 50
    x 4 = 200.
    10. Consider a NAND gate with three inputs A, B, C and output Z.
    The logic values at the inputs are A=1, B=0, and C=1. The
    input fault lists are LA = {x/0, y/1, A/0}, LB = {x/0, B/1), LC =
    {y/1, w/0. C/0}. What will be the fault list at the output Z?
    a. {B/1, Z/0}
    b. {x/0, B/1, Z/0}
    c. {B/1, y/1, Z/0}
    d. None of the above.
    Correct answer is (a).
    Inputs are A=1, B=0, C=1. So a single fault will propagate
    to the output if B changes, and both A and C do not
    change.
    L Z = (LB – (LA U LC)) U {Z/0} = {B/1, Z/0}

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