IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO.

4, APRIL 2013 975

A CMOS Operational Schmitt

Trigger R-to-F Converter for Nanogap-Based
Nanosensors Read-Out
Alberto Bonanno, Marco Crepaldi, Member, IEEE, Ismael Rattalino, Paolo Motto, Danilo Demarchi, Member, IEEE,
and Pierluigi Civera

Abstract—We report design and measurements on a

CMOS Schmitt Trigger-based quasi-digital resistance-to-fre-
quency converter prototype that can be effectively used as a
read-out circuit for nanodevice-based sensors. The readout circuit
comprises an operational amplifier and an inverting Schmitt
Trigger, achieving an hysteresis scaled to 1 mV-order, hence,
increasing frequency compared to a standard Schmitt Trigger RC
oscillator. Experimental results obtained through an opto-isolated
PCB set-up show maximum 0.8% measurement accuracy
and a dynamic range between and . The flexible
R-to-F converter occupies silicon area and has a
simulated power consumption of at 1.2 V supply.
Index Terms—CMOS nanosensor interface, parasitic estima-
tion, R-to-F converter, Schmitt trigger RC oscillator.

I. INTRODUCTION Fig. 1. Integration of nanodevices onto a standard CMOS IC after both Front-
end-Of-Line (FEOL) and BEOL have completed. The nanodevices, based on
state-of-the-art nanostructured materials, are interfaced as oscillator loads to

N ANOSTRUCTURED materials integration with mi-

crotechnology has been recently proposed for new
generation sensors, towards the interaction of well-established
the CMOS read-out environment through nanogap electrodes (

bonded molecule) has been kept off-chip.

and ). In
this read-out array element validation paper, the nanodevice (e.g., nanogap and

microelectronic designs with biosystems and the molecular

world [1]. Basically, these new generation sensors will rely the integration of nanomaterials directly on the top of commer-
on physical stimulus read-out from nanomaterials, converting cial CMOS silicon chips [7], [8], after the Back-End-Of-Line
physical quantities into electrical signals with a flexible in- (BEOL) process has been completed (Fig. 1). A low power and
terfacing circuit fabricated in a standard low-cost technology. small area read-out circuit, operating as a quasi-digital Resis-
The CMOS process satisfies these requirements because it tance-to-Frequency (R-to-F) converter, can be a flexible and ef-
enables custom circuit design for high accuracy measurements, fective solution, especially towards replication in complex array
low-cost mass production and scaling down at the same time. configurations.
In perspective, a large number of sensing devices will be The very first measurements on nanogap-based nanodevices
integrated in a single silicon chip. are dc characterizations needed for acquiring information on
An approach could be the design of a single read-out cir- resistive properties of the synthesized nanomaterial or binding
cuit able to switch and manage an array of sensing elements molecules. In that case, voltage control for such nanodevices
[2]–[4]. Alternatively, the IC could include many circuit replicas should not exceed 2 V. A higher voltage could force the elec-
with very small size and low-power consumption each [5], al- tromigration process and can fatally damage a nanogap structure
lowing parallel acquisition of nanosensors’ data. In our research [9]. Moreover, focusing on the bonded molecules, some current
center, we choose the last approach and we are working to- induced mechanical forces arise as a result of charge redistribu-
wards the implementation of real-time data acquisition from tion around the atoms and they are roughly proportional to the
nanosensor arrays exploiting nanogap gold electrodes [6] or magnitude of the current [10]. These current induced forces can
physically break the molecular junction. An increase of temper-
ature intensifies thermal fluctuations and vibrations of the struc-
Manuscript received December 22, 2011; July 7, 2012. Date of publication
March 07, 2013; date of current version March 23, 2013. This paper was rec- ture, thus reducing the breakdown force.
ommended by Associate Editor A. Demosthenous. Some other applications, such as biosensors for DNA detec-
A. Bonanno, M. Crepaldi (corresponding author), and I. Rattalino are with the
tion [11], [12] also require ac characterization since, in that case,
IIT, the Istituto Italiano di Tecnologia, IIT@Polito Department, Center for Space
Human Robotics (CSHR), 10129 Torino, Italy (e-mail: marco.crepaldi@iit.it). the variation of the capacitance corresponds to different concen-
D. Demarchi, P. Motto, and P. Civera are with the Dipartimento di Elettronica tration of DNA molecules within the solution used as dielectric
e delle Telecomunicazioni (DET), Politecnico di Torino, 10129, Torino, Italy.
of the nanogap capacitor.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. For dc characterization, the aim is the evaluation of the sensi-
Digital Object Identifier 10.1109/TCSI.2012.2220455 tivity to the desired phenomena in term of resistance variation.

1549-8328/$31.00 © 2013 IEEE

976 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 4, APRIL 2013

In that sense, the nanodevices we are interested in can be mod- that can be connected to each nanodevice through a multiplexer
eled as a resistor. Overall resistance can be written as tree to implement sequential data acquisition. This approach
. The equation comprises three terms: the has been used in [2] where several nanowires are connected to
baseline resistance which could vary from a few to a a single-ended OpAmp used as integrator. A triangular output
few depending on the fabrication technology and process, is converted to a square wave signal which is the output of
the deviation , usually due to temperature variations, and the oscillator. This is then used as the feedback control signal
finally , the true sensing activity contribution. This is the for generating positive and negative current in the nanowires
widely-used model that represents nanosensors conceived for during measurements. A similar technique has been used in
gas, chemical and biological species detection or even for stan- [3] where the circuit assures high linearity in a wide resistive
dard pressure sensors. In fact, a large number of nanosensors in
range but it occupies large silicon area (i.e., high aspect ratio
the literature is based on the read-out of the dynamic variation
of transistors at the input of the system) and the total current
of nanomaterials’ resistive properties [13], [14]. With nanogap-
consumption exceeds 2 mA.
based molecular nanosensors, the I/V characteristic of a Metal-
Molecular-Metal junction shows that a plausible resis- The circuit described in [4] is used as an interface for resistive
tance is in the range but it strongly depends on gas sensor arrays. The current flowing through the resistance
the type, the number and the length of bonded molecules on the is mirrored and used for charging and discharging a capacitor
nanogap [15]. array at the input of an inverting ST. The resulting digital output
In this paper, we focus on the design of an IC interface signal is used by a Switch Phase generation unit for charge and
for nanogap-based nanosensors characterized by a variable discharge process control of a capacitor array. The flexibility
resistance and an approximated constant capacitance of the measurement range is given by the selection of proper
within the sensing range. Due to the variability of the capacitance in the array. On the other hand, it would consume
fabrication process of nanogap-based molecular nanosensor, too much power (i.e., 3 mW) if instanced several times in an
influencing and values, we propose an adjustable array paradigm to allow real-time parallel acquisition data.
wide dynamic range CMOS R-to-F converter, com- An accurate oscillator, able to sense capacitive and resistive
prising an Operational Amplifier (OpAmp) and a bi-stable variation, has been reported in [5]. The oscillator is based on
Schmitt Trigger (ST). A nanogap-based nanodevice under test the measurement of the time required for N cycles of the output
can now be used as feedback load. In this circuit topology, the frequency of the VCO and the comparison with a time base de-
ST combined with the OpAmp achieves a mV-order adjustable pending on the time constant RC. Even if its low power con-
hysteresis gap, both providing the necessary conditions for sumption and its small silicon area makes this circuit compat-
oscillation and increasing the achievable output signal fre- ible with our array paradigm, the full measurement range does
quency. In fact, standard relaxation oscillators, based on a
not include high resistance, which is a characteristic of nanogap-
ST only, do not achieve high oscillation frequency when the
based nanodevices.
feedback resistance is in the -range. We report measure-
Other circuits are conceived for applications that involve
ments on a fabricated prototype that has been validated using
an opto-isolated Printed Circuit Board (PCB). The nano-device nanogaps as reported in [16]. A sample and integrate circuit
is emulated using well-known commercial resistors (surface has been designed for detecting currents from 100 pA to
mount and Ohmite) to compare measurements with simulation depending on the sensor’s resistance. If nanogaps are used for
results. Experimental results show a dynamic range for be- bio-applications, e.g., measurements of DNA concentration
tween and . The circuit, suited to array integration, (see [12]), both resistance and capacitance have to be con-
occupies silicon area and consumes when sidered for an electrical model of the nanosensor. In fact, the
the bias current control is set at . DNA chain is linked to a conductive polymer deposited into the
The paper is organized as follows. Section II discusses R-to-F nanogap. Such polymer contributes to the sensor capacitance
related work, while Section III introduces and defines the cir- (ranging from pF to nF) in parallel with the sensor resistance
cuit. Section IV presents design, modeling and discusses cali- across the nanogap sensor. Thus, a difference in nucleic acid
bration. Herein, we focus on the demonstration of circuit’s fea- concentration causes not only a change in resistance but also a
tures and we propose simple models to explain its operation capacitance variation. The circuit design is based on an OpAmp
and stability. Post-layout simulations are reported in Section V used as a comparator for converting the nanosensor impedance
while measurements are given and compared to simulations in to a time-domain signal. The nanodevice is connected to an
Section VI. The circuit is additionally validated with a 2–10 nm input of the comparator while a reference voltage is connected
nanogap-based device for molecule detection. These measure- to the other. In the case of nanogap arrays used for implemen-
ments allowed both validation with a realistic nanodevice and tation of molecular-based memory [17], the circuit shall be
a first verification of the effectiveness of our oscillator-based
even less complex because it has to only detect the difference
read-out approach. Section VII concludes the paper.
between and of molecules corresponding to the
logic values of a bit within the selected memory cell.
II. R-TO-F CIRCUITS FOR NANODEVICES INTERFACING Within the following section we introduce our R-to-F con-
The main approach for the electrical properties measure- verter and the advantages of its use as an interface for nanogap-
ments of a nanodevice array comprises a single read-out circuit based resistive nanodevices.
BONANNO et al.: A CMOS OPERATIONAL SCHMITT TRIGGER R-TO-F CONVERTER 977

Fig. 2. Standard Schmitt-Trigger based oscillator (a), Operational Schmitt Trigger (b), and equivalent hysteresis graph (c). Depending on previous history, there-
fore on the output, the hybrid circuit corresponds to two different copies of the same operational amplifier. Each OpAmp operates for small-signal inputs, i.e.,
along the vertical hysteresis paths.

III. OPERATIONAL SCHMITT TRIGGER (OST) techniques have been also proposed as an extension of IEEE
standard sensor interface [19]: these enable significant advan-
Definition and Motivation tages especially when the sensors need to be placed in a harsh
Considering that the implementation of an array of environment or when the measured signal needs to be trans-
nanosensing elements (i.e., the nanodevice combined with mitted over a long distance [20]. An analog output in fact could
the R-to-F interface) operating in parallel for a real-time data be perturbed by noise coupling effects due to interference or
acquisition is our final purpose, we evaluate different solutions coupling effects. Moreover, a 1-bit quasi-digital signal can be
for detecting resistance variation of nanomaterials. In addition easily managed in an array architecture.
to the requirements on the measurement accuracy (i.e., the An external unit (e.g., programmable DSP or microcon-
relative measurement error), that are dependent on the specific troller), where strict constraints for power and area are not
nanodevice and application, the final circuit has to meet strict imposed, will be in charge of converting the quasi-digital signal
constraints in terms of silicon area occupation and power to an N-bit representation for digital signal processing [21].
consumption for being integrated in an array architecture. Such Moreover, a quasi-digital signal can be directly interfaced to
parameters will limit the number of nanosensing elements in an asynchronous IR-UWB transmitter [22] for wireless data
the future array architecture. transmission.
A direct resistance measurement can be possible, converting The ST-based architecture (Fig. 2(a)). has low power con-
resistance variation into analog voltage signal. Such output sumption and low complexity, but standard circuits do not
value usually needs to be converted into digital signal of N-bits, achieve high oscillation frequency for the resistive range of our
for being used by digital units for signal processing (DSP). interest. With molecular nanodevices, with typical resistivity in
Even in an array structure of several sensing elements, it is the range [23], a simple ST oscillator would operate
suitable to manage digital values. Thus, the A/D conversion at low frequency, and this could be problematic. When used in
circuit has to be included into each nanosensing element for real-time applications, a quasi digital sensor would require high
allowing parallel data acquisition in the array. In that sense, the reactivity: the back-end computation time required for the de-
complexity of the array architecture dramatically increases. tection of an event shall be small compared to the time-constant
Our purpose is to limit the complexity of the whole system of the physical quantity under measurement. Hence, frequency
in order to reduce power consumption and silicon area. A con- shall be kept as high as possible to allow a fast reaction to
ventional solution to directly convert a resistance value into a dynamic resistance variations, both for characterization and
digital signal regards the use of a relaxation oscillator whose raw on/off digital decisions.
frequency is determined by the resistance under measurement To increase oscillation frequency compared to standard
and a known capacitor [18]. The R-to-F converter has a 1-bit ST-based RC oscillators, here we propose a circuit with very
quasi-digital output with an oscillation period that is an analog narrow equivalent hysteresis gap (Fig. 2(b)). The circuit com-
conversion of the feedback resistance variations. Quasi-digital prises a standard ST and an OpAmp connected to the same
978 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 4, APRIL 2013

Fig. 3. (a) Schmitt Trigger. (b) Two stages OpAmp with DC Output Controller.

output terminal. Oscillation frequency is defined by the equiv- input signal has then to exceed for allowing tran-
alent resistance of the nanosample, the capacitor and sistor to drive the output node to a logic “0.” In this new
the amplifier ac characteristics. The oscillator output is bias condition, transistor is cut-off and the whole current
converted to the square-wave signal by the chain of three is available to the load. A similar process occurs if the input
identical inverters (X3). The voltage across the nanosample can signal changes from to 0, as the output switches only when
be carefully controlled during oscillation. In fact, the voltage the input voltage is reduced to . By oper-
at the input common node “F” is almost constant, limited by ating on the size of and and thus on their equivalent
two thresholds and around the voltage , , we can control of the Schmitt-Trigger. Once the
while the node “A” switches from logic value “1” to logic size of the other PMOS and NMOS devices is fixed, the higher
value “0,” limited by the supply voltage of the circuit and their aspect ratio, the wider the hysteresis gap. In the literature,
the global ground. Thus, the voltage across the nanosample is many works focus on the control and the minimization of the
alternatively positive and negative, defined by or, hysteresis gap [27], [28]. Here, the hysteresis gap of our ST is
with , approximated to . Under such con- still large, i.e., 320 mV. To obtain a digital signal at the output,
ditions, the nanogap-based nanosensor is preserved from the the ST has to provide the maximum current required by the feed-
damages described in Section I. We define this hybrid circuit back loop and defined by (2).
as “Operational Schmitt Trigger” (OST), since it integrates the
bistable properties of a ST and the ac response of an OpAmp. (2)

A. Schematic
where and correspond to logic level “0” and “1”
For a qualitative analysis, we start considering the standard respectively. Such concept is important to understand the be-
relaxation oscillator based on the ST circuit [see Fig. 2(a)]. The haviour of the OST reported in Fig. 2(b), where ST and OpAmp
formulas that describe the charging and discharging process of share the same output node “A.”
the input capacitor are well-known and we can link the oscil- Fig. 3(b) shows the schematic of the OpAmp. The differen-
lation frequency to the and values using (1), where tial input stage ( and ) and their bias point are set using
is the feedback resistance, is the capacitor at the ST input, transistor of the current mirror. and are the ac-
and are the edges of the hysteresis gap of the ST. tive load of the differential stage, while , , , and
are used for the second cascode stage. The current
(1) flowing through and is also mirrored to the output
stage since the transistor has been designed with the same
where . Fig. 3(b) shows the schematic circuit of the im- size of . and stabilize the OpAmp with unitary feed-
plemented inverting ST. The hysteresis gap back. The diode connected transistors and polarize
is defined by and [24]–[26]. The ST oper- that feedbacks the output signal to the input of the second
ates as follows. When input signal is “0,” transistor and stage. In fact, the drain of transistor is connected to the gate
are cut-off while and drive the output voltage of that modulates the cascode stage of OpAmp in a neg-
to . Transistor is also cut-off since its is the of ative feedback configuration. Such DC-Output Controller has
the saturated transistor and thus the maximum current is been mainly conceived for using the OpAmp within other on-
available for the output load. When the input voltage increases going studying applications where the output dc level has to be
and reaches , transistors and are activated but forced at midrange of the supply voltage. For those applications,
is not reduced enough to be considered negligible. In fact, the OpAmp is used in linear region. On the contrary, here the
the supply voltage is split on the two channel resistances cascode stage does not work as usual since node is forced to
of transistors and in saturation region. The logic state “1” or “0” by the ST. The differential amplifier has
BONANNO et al.: A CMOS OPERATIONAL SCHMITT TRIGGER R-TO-F CONVERTER 979

a nominal 67 dB dc gain and a 10 MHz 0 dB bandwidth. When

is , the OpAmp has an output series resistance of
.

B. Conceptual Operation

From a digital perspective, the circuit can be described as fol-

lows, referring to Fig. 2(b). When the oscillator is powered on,
the circuit is forced to an unstable equilibrium since the bistable
block’s input is initially imposed at a half voltage supply .
In such condition, the ST drives the load to a rail-to-rail logic
value “1” or “0.” Let us assume that the ST sets a high logic
level at the output . When it switches, the current flows
through resistance and the capacitor starts to be charged.
The slope of the rising voltage at the input of the active cir- Fig. 4. Full oscillation range obtained through transient
cuit is a function of the time-constant. The OpAmp is simulations for different . Region A and B correspond to two different os-
cillation regimes. At the operation ends oscillation is a square wave, side B, and
forced to operate out of linearity since its output is set by a sine wave, side A.
the ST and it is not directly dependent on the voltage difference
. In the schematic of Fig. 3(b), the output stage ab-
can be modeled as two different Thévenin equivalent output net-
sorbs current through the NMOS transistors of the cas-
works, same negative series resistance [ , Fig. 2(c)] but dif-
code stage. Initially, such current can be provided by the ST as
ferent voltage sources that combine to the output resistance of
long as it does not reach the saturation limit. Under this condi-
the OpAmp . The common mode of is then infinitesimally
tion, the output level is high and the input voltage continues to
perturbed, depending on the working hysteresis path of the ST,
rise. When the current absorbed by the amplifier is reaching the
resulting in a very low gap. The output stage of the OpAmp is
maximum current that can be provided by the ST, rapidly de-
modeled using a voltage source (that linearly depends on
creases. Since no current can be provided to the feedback loop,
input voltage ), with a series resistance . For simplicity we
immediately decreases. At the same time, the OpAmp can
model the two bias conditions of the ST, assuming a constant
easily drive the output voltage to the logic “0.” The voltage
and two voltage sources , . The ST’s equivalent
changes slope and the capacitor starts to be discharged, thus
voltage source in the two conditions , depends on the
we can identify the threshold of the hybrid system. The
previous operation history, i.e., , and once set by
next output switching occurs when voltage is lower than
’s previous history, it remains unvaried. This ensures that os-
the reference voltage and exceeds the threshold . This
cillation can hold by maintaining the input differential voltage
periodic commutation generates an oscillation having a higher
small, similarly to linear negative feedback circuits.
frequency compared to a standard ST-based RC oscillator, as-
suming the same load. The two threshold and de-
fines a mV-order dynamic hysteresis that is very small IV. DESIGN AND ANALYSIS
compared to mentioned above (i.e., 320 mV). The effect is
an increase of oscillation frequency of two orders of magnitude
A. Oscillation
compared to standard ST-based RC oscillators. Hence, voltage
is quite stable because it has small oscillations around , Generally, this circuit operates with a full swing
usually set at a half voltage supply. Since the output voltage and oscillation is a square wave for high . However, as will
is quasi-digital, the nano-sample maximum voltage is . be shown in Section VI, the circuit can also operate under sinu-
The hysteresis gap can be finely controlled with the OpAmp soidal regime provided that is close to the equivalent output
bias current ( in Fig. 3(b)). In fact, an increase of cor- resistance. Fig. 4 shows the oscillation period for dif-
responds to an increase of the output current flowing ferent loads in the range . Within this wide
into the cascode stage. This narrows the hysteresis gap, since range, the monotonic curve can be divided in two wide operation
the easily overcomes . could be very useful ranges, A and B, for low and high resistance (
to tackle interference coupling and noise for R-to-F conversion. and ). The two intervals correspond, qualita-
In fact, since the hysteresis gap is very small, disturbances can tively, to two different oscillation trends of , towards a sine
easily couple across the high impedance input node and the cir- wave and a full digital signal, respectively. Within zone A, the
cuit can generate spurious output commutations. Noise impact period changes as whereas the trend is linear in zone B.
can be lowered reducing , hence widening the hysteresis Typically the whole sensing range is not needed for a single nan-
gap. odevice, and the knee point (i.e., the boundary limit between re-
From the analog viewpoint, the operation of this hybrid cir- gions A and B) can be adjusted operating on capacitor (see
cuit can be explained referring to both OpAmp and ST output Fig. 5). Running specific analyses on the conversion curve of
resistance at (see Fig. 2(c)). For the ST two different bias Fig. 4, we conclude that can be assumed a linear function of
points can be possible, depending on the previous history, corre- in zone B, i.e., and a non-linear function
sponding to two possible hysteresis paths. Around , these in zone A, i.e., . Within these two ranges,
980 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 4, APRIL 2013

Fig. 6. Small-signal equivalent circuit of the oscillator. Using this simple

equivalent small signal model, the necessary conditions for oscillation start can
be calculated.

by the control compared with (see Section VI) so that

the analog control input could be used for fine adjustments.
Fig. 5. A detailed view on simulation results for different . Oscillation pe- B. Stability Modelling
riod is larger if increases and, consequently, the knee point of the curve
moves left. Linear zone B is larger for high off-chip capacitors. This subsection analyzes the stability of OST circuit basing
on equivalent small signal model at , assuming the same
, the maximum linearity error is 4% and 3% for low ST equivalent output resistance - for the two possible bias
and large resistor loads, respectively. points. The sample resistance , its parallel parasitic capac-
The circuit permits an oscillation range tuning by setting itance and the off-chip capacitor model the full circuit
. Particularly, the impact of on period can be modeled as load. The OpAmp can be modeled with a controlled voltage
in zone B, and source, an equivalent output resistance and capacitance and
in zone A, where and . Fig. 5 .
reports period for different . As increases, frequency Fig. 6 shows the small signal equivalent circuit assuming it
decreases. For instance, considering , the holds for the two possible bias points. The open loop gain can
oscillation frequency varies from 153 kHz to 2.2 kHz if we be calculated using Kirchhoff’s current law across node A [(3)
change off-chip capacitor from 10 pF to 10 nF respectively. and (4)] which is obtained by calculating the current through the
Assuming , and with pF, and units respectively, impedance , i.e., and capacitor . In our analysis
the coefficient can vary from to 1.85 whereas we assume that . We obtain
ranges , for between 10 pF and 10 nF.
(3)
Within the whole input range, the fitting polynomials include
both 1-st and 1/2-th power terms, and . Assuming
and , the fitting curve is (4)
then with full-range error
lower than 4%. Besides evident effects on , also influences where is the small signal OpAmp differential input voltage
the knee point and the linearity of the conversion curve. With and is the differential voltage gain of the OpAmp. Substi-
and , the knee point is tuting and rearranging the two equations, we obtain the formula
whereas it shifts to for . For higher reported in (5) for . , and depend on the
, the linear region B is expanded and the maximum linearity transistor sizing, while and depend on the load.
error is even reduced from 3% to 1.8%. The circuit can be Assuming that is fixed and is negligible, simulation re-
then easily designed to work within region A or B, given a sults show that oscillation starts when is larger than a critical
constrained resistance range. value (in our prototyped circuit, ). Otherwise,
Finally, since oscillation is induced by the unbalanced action the system is stable with a positive phase margin. Fig. 7 shows
of the ST and the OpAmp, by modifying the dimension of two possible magnitude and phase open loop gain responses for
and so that the maximum current is reduced, the hys- two loads, and . For , the circuit
teresis gap is narrowed and oscillation frequency increases. has a negative phase margin and for each of the two possible op-
On the other hand, the same effect is obtained with an increase erational amplifiers initially biased, the system is unstable. For
of . is narrowed because of a higher . How- , the operational amplifiers reaches a weak stability
ever, the R-to-F conversion curve is not significantly modified and oscillation is stopped since the phase of is above 180 .

(5)
BONANNO et al.: A CMOS OPERATIONAL SCHMITT TRIGGER R-TO-F CONVERTER 981

TABLE I
IMPACT OF ON PERIOD

Fig. 7. Magnitude and Phase open loop gain plots for (con-
tinuous line) and (dotted line). , ,
, . For , due to the negative phase
margin, oscillation is started.

Fig. 8. Simple RC model of the nanodevice under test. The nanosample gen-
erally comprises two to-ground parasitic capacitors and and a parallel
capacitor .

Fig. 9. Transient simulation of the oscillator for . The oscillation

regime corresponds to approaching the transition zone, depicted in Fig. 4.
amplitude of , applied at the negative input of the OpAmp
The studying approach for a second order system, affirming (with about 1 mV amplitude variation) is very close to the hys-
that the oscillation condition is reached if the dumping factor teresis gap of the enhanced ST. , the oscillator output, is con-
is 0, could not be applied here. In fact, the numerator of verted to a square wave by the chain of three identical inverters
includes (s), the differential transfer function of the OpAmp to obtain
which includes at least a pole, in our case at 21.87 kHz. The the quasi-digital signal . is the current flowing through
resulting system is a third order system and we should refer to the nanodevice that charges and discharges the off-chip capac-
[29], where the definition of the “effective” dumping factor itor . The circuit maintains a controlled voltage across the
is introduced for the analysis of a similar third order system. nanosample as the OpAmp input voltage remains , i.e.,
keeping the circuit unstable but within a negative feedback con-
V. POST-LAYOUT SIMULATIONS dition. The simulated power consumption is at 1.2 V
The circuit has been simulated including bondwires and I/O power supply with and it is to a first approxima-
PAD RLC models. We also included a simple RC nanodevice tion frequency independent.
model to analyze the impact of parasitics on the circuit opera- 2) Parasitic Impact: The R-to-F converter is basically an
tion. The load has been modeled as shown in Fig. 8. and RC oscillator, and parasitic components may impact on perfor-
model pF-order parasitic components due to physical connec- mance and operation [30], particularly for large measurements
tions on the testing board, while still models the parasitic set-ups with off-chip components, as in our specific case. Ad-
parallel capacitance of the sample. ditionally, at nanoscale, nanodevices’ parasitics are also par-
1) Transient Simulations: Fig. 9 shows a transient simula- ticularly important for CMOS integration [31]. These depend
tion for , , , . The on both the fabrication process and the metal interconnections
982 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 4, APRIL 2013

length of the BEOL. In this section we analyze and comment

the impact of parasitic on performance and circuit operation.
Assuming linear small-signal approximation, even when op-
erating near the knee point shown in Fig. 4, variations can
be mapped to resistance variations, i.e., assuming ,
. The impact of , and has been evalu-
ated at simulation level. Assuming constant , each parasitic
impacts on , therefore we define sensitivity , and
as the per pF period variation to , , , respectively. More-
over, we can calculate the relative effect given by , and
variations on the measurement . From simula-
tions, we conclude that the impact of and can be negli-
gible as it is below 0.1% and 1.2% respectively.
Fig. 10. Monte Carlo simulations with both process variations and mismatches.
Table I shows that is higher compared to and .
but it remains constant for high in terms of relative variation
. ranges spanning three
orders of magnitude . We conclude that this ST-based oscil-
lator is sensitive to . This characteristic can be both an ad-
vantage and a disadvantage. A high can be a disadvantage,
i.e., impacting on the measurement of , since each sample
of the nanogap-based nanodevice has different capacitive com-
ponent due to fabrication process. For a small resistive nanode-
vice, in fact, can be assumed constant in the working fre-
quency range. On the other hand, this sensitivity could be an
additional feature of the circuit. In fact, the OST could be even
used for capacitive nanodevices. If we connect a small commer-
cial resistance in parallel to the capacitive nanodevice, the
oscillation frequency changes proportionally to the variation of
. It can be advantageous, e.g., giving a higher degree of flex- Fig. 11. Oscillation frequency of each Monte Carlo simulations run
, dotted line for the nominal run.
ibility, enabling further estimations. In the next Section VI
we will demonstrate with measurements that sensitivity can
be accounted for, particularly, not heavily affecting estima- fabrication process, each nanosensor in the array possibly needs
tion accuracy. We will show that coarse estimation can be an ad hoc calibration.
even possible. However, we leave in-depth analysis of this po-
tential feature for successive works, as here we characterize the A. Monte Carlo and Noise Simulations
circuit only for read-outs.
3) Calibration: A first calibration process can be achieved Fig. 10 shows superposed transient Monte Carlo simulations
assuming a fixed capacitor , a known load , with small par- of the OST, with , , , 50 runs.
allel capacitance 1, and by measuring the corresponding The thicker line that represents the nominal run. They have been
period and are off-chip commercial components. all referenced to the first positive edge of the nominal curve,
For each range A and B2, period is, respectively, considered as reference for our analysis. With process variations
and mismatches the frequency shifts from the nominal value by
58.4 kHz. Fig. 11 better evaluates the maximum frequency shift.
The horizontal dotted line represents the frequency of the nom-
inal run. In the worst case, we reach 72.4 kHz that corresponds
(6) to shift of 24% in frequency domain. Nevertheless, the average
frequency shift, considering all the 50 runs, is only 6%.
which leads to Fig. 12 shows a noise analysis on the OST. We included a
noise source across F (see Fig. 2) and the plotted curve is the
(7) input referred noise across . Since the OST usually works
from 100 Hz to 300 kHz, the noise contribution does not exceed
.
However, since the nanodevices integrated into the array
structure will have different electrical properties due to their
1Quantity larger than .
VI. MEASUREMENTS
2We assume that equations and The circuit has been implemented in RFCMOS
are valid with proportional to and . When the equation for the
full measurement range from to is considered, the problem cannot be technology and occupies silicon area. Fig. 13
mathematically solved with such easy steps. shows the microphotograph of the OST. It has been packaged
BONANNO et al.: A CMOS OPERATIONAL SCHMITT TRIGGER R-TO-F CONVERTER 983

Fig. 14. Effect of bias current on in load range.

decreases for high since hysteresis gap narrows.

Fig. 12. Input referred noise . A noise

source is connected to F in the OST circuit.

Fig. 13. Microphotograph of the R-to-F read-out circuit.

in QFN48 and soldered on a standard FR4 board 1.6 mm thick,

ad hoc designed to permit low-noise measurements.
Fig. 15. Measured frequency for different SMD resistors versus post-layout
simulations for different (a) Range . (b) Range
A. Set-Up . In all simulations, .
The ST-based oscillator has a very high impedance input and
very large resistors need to be used for validation. At 50 Hz, 1 The circuit power supply is 1.2 V and bias point is set using
pF parasitic coupling is , comparable to the high-end the common reference voltage , nominally 600 mV, and
measurement range of our oscillator. Preliminary tests on a gen- needed by the OpAmp. A 1 nF is mounted as an off-chip
eral purpose PCB evidenced a very large coupling with the 50 SMD component. Whether the circuit and the nanodevice are
Hz ac power line, from oscilloscope ground probes, from dc on-chip, can be integrated with smaller nominal value and
power supplies and from the human body. In these preliminary the OST can be accordingly designed.
tests, the measured frequency was heavily offset by these distur-
bance sources. To solve these problems, the IC was mounted on
B. Measurements Using Commercial Resistors
an optical isolated battery powered TX PCB, caged by an ad hoc
metal shielding box. The TX PCB, with a general power supply The circuit has been quantitatively validated using stan-
of 4.5 V with on-board voltage regulators, transmits oscillations dard 5% 0603 SMD and 1 Ohmite resistors, connected
through a fiber optic cable driver. The testing PCB comprises to the testing board with dedicated jumpers. As discussed in
an Avago HBFR1524 optical isolator driven by a Philips BSS87 Section III, the frequency can be also modified with the hys-
low-voltage power MOSFET connected to the output of the chip teresis gap width. Fig. 14 shows the dependency on for
through a SN74AVC1T45 level shifter. The transmitted signal one decade variation of . As the OpAmp gain increases with
is detected by another RX PCB mounting an Avago HBFR2524 , decreases (see Fig. 2) and the system
optical receiver, 1.5 m far from the transmitter board. The re- oscillates at higher frequency. sensitivity is .
ceiver board is eventually connected to a BNC connector for Fig. 15(a) and 15(b) report superposed simulated and experi-
statistical measurement runs. A 1 G/s Agilent MS07104A oscil- mental data for and range. The
loscope has been used for time-domain measurements on both simulated curves refer to three different . Assuming as
TX and RX PCB, while an Agilent 53132A Universal Counter the parasitic load capacitance, the R-to-T curve is verti-
has been used for mean and standard deviation measurements cally shifted-down, i.e., higher frequency for higher . The ef-
at the receiver PCB output. Sample parasitic have been deter- fect of the parasitic capacitance on the sample then, is simply
mined using an Agilent 4294A impedance-meter. the projected y-axis distance from the curve. A coarse
984 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 4, APRIL 2013

Fig. 16. Measured standard deviation of oscillation frequency for , using standard SMD resistors (uncompensated for , 100 sample data).
Measurement results show low , i.e., accuracy below 0.9% and 1.4% for low and high resistance range respectively. For loads of about , a higher
peak is obtained for , . This effect is due to external coupling through the sample wires and on the high impedance input of the OpAmp.

Fig. 17. (left) Measured standard deviation of digital signal with using standard resistors (uncompensated for , 100 sample data). Systematic
error around is strongly reduced widening the hysteresis gap of the OST. relative accuracy is below 0.1% in the range and below
0.8% in the range . The full-range accuracy does not exceed 0.8%. (right) Relative error between simulated and measured data. The blue curve
is plotted assuming , (uncompensated) whereas the red curve accounts for parasitic (compensated). has been measured using the Agilent 4294A
impedance-meter. Samples above could not be accurately measured. When is accounted for, relative error significantly decreases (bottom graph).

parasitic estimation, in this specific case constant in the related to the accuracy of the converter.3 With ,
kHz-range, can be obtained using the following equation, accuracy is below 0.9% up to while it rises for higher re-
sistance reaching a maximum 1.4%. External disturbances cou-
(8) pled through the sample connectors affect accuracy systemati-
cally, especially around . This can be overcome by ad-
justing the threshold: with , the 1 mV-order gap
where is the simulated period using a resistive-only load ,
is increased, i.e., significantly decreasing the sensitivity to ex-
is the measured period with the sample and is the sen-
ternal coupling. Figs. 16 and 17 report the equivalent accu-
sitivity reported in Table I. For such coarse parasitic estimation,
racy in the full measurement range for different sets. For
we assume that the variation between the simulated and the
, accuracy is below 0.1% from up to
sample resistance is negligible.
Figs. 16 and 17 report the full range measure- 3The measured std. deviation can be mapped to a relative measurement ac-
ments using both SMD and Ohmite resistors, averaging 100 pe- curacy in the domain. Accuracy is then defined assuming linear fit between
two closest measurements ( , ),
riods per measurement session. We report both mean frequency i.e., . is defined as
and standard deviation (Hz units) and , as it is .
BONANNO et al.: A CMOS OPERATIONAL SCHMITT TRIGGER R-TO-F CONVERTER 985

TABLE II
COMPARISON WITH THE STATE OF THE ART. N/A = NOT AVAILABLE , , RESULTS

and does not exceed 0.8% within the full measurement

range.
Fig. 17 (right) shows relative error between simulated and
measured period (uncompensated curve). As discussed in
Section IV-A, sensitivity to causes a higher frequency than
expected. As shown in Fig. 15 in fact, each experimental data
is below the resistive-only load curve. Here, we compared
measurements with simulations with both =0 and measured
value.4 If measured is accounted for, relative error can
be drastically reduced. We characterized each sample using
an Agilent 4294A impedance-meter to obtain parasitic at
different frequency. The instrument permits measurements not
exceeding . The bottom graph (Fig. 17 -(right)) reports
the measured for each SMD sample (already soldered to its
own jumper). By using these measured values in simulations
and comparing to experimental data (top figure), the mismatch
is now drastically reduced (compensated curve). The maximum
mismatch between compensated simulation and experimental Fig. 18. Example of measured hysteresis using a 1 Hz sine wave input,
data is now 1.4%. infinite oscilloscope persistency, XY mode.

C. Comparison With the State-of-the-Art A/D and D/A converters. Such circuit presents best performance
in term of accuracy, but it is not suitable for our application area
Table II compares this work with the state-of-the-art. The
due to the high power consumption (about 6 mW) and large sil-
96 dB dynamic range5 has been experimentally demonstrated
icon area .
using known test resistors. A similar range is achieved in [32]
and [3]. The low and high resistance ranges are obtained by fit- D. Other Measurements
ting terms , . The circuit proposed in [5] has similar lin-
earity in the whole conversion range (i.e., 5%), but [3] and [4] 1) Hysteresis: Fig. 18 shows the measured hysteresis gap
can achieve best result in term of linearity error compared to of the OST ( versus ) using a low frequency sine wave
this work. The mismatch between simulated and measured pe- input. For this experiment we used a very low frequency signal
riod does not exceed 1.5% and simulations can be even used with infinite oscilloscope persistency because hysteresis is
as reference for parasitic capacitance estimation (as previously typically defined at dc. The measurement, even corrupted by
shown in Section VI-B). Only [5] has better estimation per- noise, confirms that our system has a very low hysteresis.
formance but covers half the range. For our oscillator measured 2) Sinusoidal Regime: With low , the circuit can be used
accuracy does not exceed 0.8%. Given its silicon area and power in first approximation as an single-pole RC sinusoidal oscillator.
consumption, this enhanced ST oscillator can be finally used in A higher current flows through the resistance charging
an array architecture and properly optimized to meet integra- and discharging the capacitor at higher frequency. The sinu-
tion constraints. The high performance solution given is [5] has soidal behaviour is due to the reduced time constant of the oscil-
comparable performance, but area is about 15 times larger and lator that forces the OpAmp to immediately balance the contri-
power consumption depends on output frequency. In the archi- bution of ST circuit before that the output is set to logic value
tecture given in [33], the sensed resistance is converted into a “1” or “0.” The sinusoidal output amplitude is about 600
13-bit digital output exploiting a programmable gain amplifier, mV for but it progressively reduces for resistance
values approaching the critical (e.g., if
4The depicted relative error is defined as , ).
where and are the measured and the simulated period with null or
measured , respectively. Fig. 19 shows a generated sine wave, region . The 3-rd order
5Dynamic range defined as maximum versus minimum resistance ratio, frequency component is 40 dB below the peak emission. Under
decibel units, i.e., . these conditions the input voltage variation (i.e., on the order
986 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 60, NO. 4, APRIL 2013

Fig. 19. The oscillator can also operate in sinusoidal regime. Under this con-
dition, the differential input signal (not shown here) is large and hypotheses
for small-signal analysis are not satisfied.

Fig. 21. The nanogap electrodes can be effectively combined with the OST
oscillator for molecule detection. (a) Nanogap with no bonded molecules.
Fig. 20. SEM image of a nanogap fabricated through controlled electromigra- (b) Nanogap with bonded molecules.
tion of a gold wire [6].

of 20 mV) is not small and small-signal analyses cannot be is below 6 nm. An order of magnitude of the contacting area of
considered. each of these points is , and we can typically count 10
3) Tests With a Nanogap Electrode: Fig. 20 shows a Scan- contact points within a nanogap-based nanodevice. With such
ning Electron Microscope (SEM) image of a pair of nanostruc- contact points, the estimated total contacting area could be
tured gold electrodes (nanogap) used for our experiments [6]. . Since the average grafting density for alkanethiols
Monolayers of conductive Thiophene molecules have been self- self assembled monolayers is around
assembled onto the two facing gold electrodes [34] resulting in [37], and we use the same grafting density for our thiophene
a gold-molecules-gold molecular junction [35]. The nanogaps molecules, we can estimate about involved in
are fabricated through electromigration with a full custom PCB- the conduction in our contacting area. Thus, can be ap-
based modular system. The closest distance between the two proximated to 1 fF.
facing electrodes ranges 2–10 nm. Fig. 8 can represent the elec- depends on geometry of the nanogap structure (
trical model of such nanogap-based nanodevice. In particular, width, 25 nm thickness) and dielectric placed between elec-
the parallel capacitance is the sum of the molecular capaci- trodes. As mentioned above, in our case only few molecules
tance and the nanogap capacitance . The first contri- are bonded on the nanogap after drop casting using a volatile
bution can be estimated from [36], where the order of magnitude TetraHydroFurane (THF) solution with 1 nM molecular concen-
of the capacitance of a single molecule (ethylbenzene) is around tration. The THF solvent is very volatile (a drop of com-
. The number of molecules involved in the conduc- pletely evaporates in few minutes) leaving only the molecules
tion must multiply this value to get estimation. We can deposited binding the nanogap, thus can be approximated to
suppose that the molecular bridging is probable for a distance the air dielectric constant. Assuming and con-
less than 6 nm, due to molecule dimension. If we consider our sidering the dimension of electrode surface and
SEM image (see Fig. 20) of the nanogap-structure, we can no- the average distance between gold electrodes (20 nm), we can
tice that typically there are only few points where the nanogap assume that is not bigger than 0.022 fF.
BONANNO et al.: A CMOS OPERATIONAL SCHMITT TRIGGER R-TO-F CONVERTER 987

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[34] Q. Tang, Y. Tong, T. Jain, T. Hassenkam, Q. Wan, K. Moth-Poulsen, Paolo Motto has a background in information
and T. Bjørnholm, “Self-assembled nanogaps for molecular elec- technology. His expertise ranges from analog and
tronics,” Nanotechnology, vol. 20, no. 24, 2009. digital electronics to embedded system design for
[35] M. A. Reed, C. Zhou, C. J. Muller, T. P. Burgin, and J. M. Tour, micro and nano applications. His scientific interests
“Conductance of a molecular junction,” Sci., vol. 278, no. 5336, pp. are focused on nanotechnology with emphasis on
252–254, Oct. 1997. nanogap production and utilization. The scope of
[36] K. H. Bevan, D. Kienle, H. Guo, and S. Datta, “First-principles the nanogap covers from molecular electronics,
nonequilibrium analysis of STM-induced molecular negative-differ- biomolecular sensing and biomedical applications.
ential resistance on Si(100),” Phys. Rev. B, vol. 78, p. 035303, Jul. He currently works as programmer and network
2008. engineer at Department of Electronics of Politecnico
[37] H. B. Akkermanal, “Towards molecular electronics with large-area di Torino, Italy.
molecular junctions,” Nature, vol. 441, May 2006.

Alberto Bonanno received his degree in electronic

engineering at Politecnico di Torino, Italy, in 2005 Danilo Demarchi (M’10) received the engineering
and the Dr.Eng. degree in electrical engineering from degree and the Ph.D. degree in electronic engi-
Ecole Polytechnique Federale de Lausanne, Switzer- neering at Politecnico di Torino, Italy, in 1991 and
land, during a double degree project. 1995, respectively.
From 2005 to 2008 he worked in a private He has a full position as Assistant Professor at Po-
company on the development of EDA tools for litecnico di Torino, for the “Electronics for Bio Engi-
low-power IC design. He joined Politecnico di neering” and “Microsystems for Medicine” classes.
Torino in November 2008 for the design of a Pirelli He is currently working on micro and nano systems
smart sensor system. He joined the Istituto Italiano for electronics and biomedical applications. He is au-
di Tecnologia@Polito in 2011 as a Ph.D. student. thor and coauthor of 2 patents and of more than 50
His research activities are low-power digital IC design and mixed-signal IC scientific publications in journals and conference pro-
design for nanostructured materials read-out. ceedings related to micro and nano systems.
Prof. Demarchi is currently coordinating the microelectronics research lines
in the IIT@Polito Department, Center for Space Human Robotics (CSHR).

Marco Crepaldi (M’09) received the engineering

degree (summa cum laude) and the Ph.D. degree in
electronic engineering from the Politecnico di Torino Pierluigi Civera received the Dr. Ing. degree in elec-
(Polito), Turin, Italy, in 2005 and 2009, respectively. tronics engineering from the Politecnico di Torino,
During 2008 he was a Visiting Scholar at the Italy, in 1979 (summa cum laude).
Electrical Engineering Department, Columbia Uni- He joined the Department of Electronics at Po-
versity, New York. After the Ph.D., he worked as litecnico di Torino 1983 as a Graduate Researcher.
a Postdoc at the Vlsi-Lab, Electrical Engineering Since 1991 he is an Associated Professor for VLSI
department, Polito. He is currently a Junior Postdoc Architectures in the same department. His major
at the Istituto Italiano di Tecnologia @ Polito, Center interests include computer architectures, VLSI
for Space Human Robotics. His research interests design for telecom applications, and ASIC design
include ultra-low-power UWB transceivers design, VHDL-AMS behavioral and technology transfer to small and medium
modeling of wireless communications circuits and systems, ultra-low current enterprises. Recent research activities are mainly
amplifiers, integrated sensing elements for nanostructures, and professional devoted to microsystems design for biochemical and genetic applications.
digital audio-video broadcasting systems development. He has been manager for the Politecnico contribution for several European
projects: in the EUREKA PROMETHEUS PRoCHIP project, the JESSI project
“Methods and Tools for ULSI System Design: Architectural Strategies,” the
RACE II project Stratospheric, the RACE II project DTTB “Digital Terrestrial
Ismael Rattalino received his M.Sc. degree in Television Broadcasting.” He was in charge, as the local responsible or the
biomedical engineering from Politecnico di Torino, coordinator for several technology transfer activities and EU special actions in
Italy, in 2009. After a year spent as researcher microelectronics such as I-SMILE, MEPI, SUMIS, and FUSE.
assistant at the Department of Electronics at Po-
litecnico di Torino, he joined the Istituto Italiano
Tecnologia@Polito, Center for Space Human
Robotics, as a Ph.D. candidate.
His research focuses on the exploitation of
nanogap electrodes for biosensing and molecular
electronics.