Chapter 4 Densitometro Lunar

LUNAR® DPX-IQ Service Manual Rev.
E (3/98)
Chapter 4
Technical Description
This chapter includes discussions of the various interface circuit boards of the DPX-IQ.
4.1 The AMP Board .......................................................................................................4-1

4.1.1 Circuit Description .............................................................................................4-1
4.2 The Automatic Gain Stabilizer (AGS).......................................................................4-5
4.2.1 Signal Input .......................................................................................................4-5
4.2.2 Gain Modification ..............................................................................................4-5
4.2.3 Rollover.............................................................................................................4-6
4.2.4 Operate/Calibrate (OP/CAL)..............................................................................4-6
4.2.5 Amplification Stage............................................................................................4-6
4.2.6 Signal Output ....................................................................................................4-6
4.2.7 Amplify/Attenuate Indication ..............................................................................4-6
4.2.8 Performance and Operation ..............................................................................4-7
4.2.9 AGS Adjustment................................................................................................4-7
4.2.10 Test Points and LED's .......................................................................................4-9
4.3 The Dual Channel Analyzer (DCA) ........................................................................4-11
4.3.1 Function Description........................................................................................4-11
4.3.2 Circuit Analysis and Operation ........................................................................4-11
4.3.3 Technical Facts ...............................................................................................4-12
4.3.4 Recommended DCA Settings..........................................................................4-12
4.3.5 Test Points ......................................................................................................4-13
4.4 The MAX Board .....................................................................................................4-15
4.5 The XORB Board...................................................................................................4-21
4.5.1 Operations ......................................................................................................4-21
4.5.2 Solid State Transient Voltage Suppressors .....................................................4-21
4.6 The Single Board Controller (SBC) ........................................................................4-23
4.6.1 Microprocessor and Memory (U1, U2, U4, U21, AND U22) .............................4-23
4.6.2 Address Selection ...........................................................................................4-23
4.6.3 RS-232-C Interface (U7 & U8).........................................................................4-24
4.6.4 System Reset (U8, SW1) ................................................................................4-25
4.6.5 System Clocks (X1, X2, U15) ..........................................................................4-26
4.6.6 Event Counting (U13, U14, U17, U18, U19, U20, J1, J2) ................................4-27
4.6.7 Stepper Motor Control (U9, U10, U31, U32) ....................................................4-27
4.6.8 Limit Switch Sensing (U27, U31) .....................................................................4-27
4.6.9 I/O Ports (U23, U41)........................................................................................4-28
4.6.10 Watch Dog Timer (U48) ..................................................................................4-30
4.6.11 D/A (Remote Detector Amplifier High Voltage) Control (U44, U45) .................4-30
Technical Description Chapter 4

LUNAR® DPX-IQ Service Manual Rev. E (3/98)
4.6.12 D/A (Remote X-ray High Voltage and Current) Control (U36, U37) .................4-30
4.6.13 A/D (Remote X-ray High Voltage, Current and Amplifier High Voltage Feedback
Sense) (U35, U40, U42, AND U43) .............................................................................4-31
4.6.14 Thermocouple Sense (U38, U39) ....................................................................4-31
4.7 The OINK Board ....................................................................................................4-33
4.7.1 Motion System ................................................................................................4-33
4.7.2 Patient Locator Light .......................................................................................4-34
4.7.3 Collimator Control ...........................................................................................4-34
4.7.4 Fans................................................................................................................4-34
4.7.5 Indicators ........................................................................................................4-35
4.7.6 Emergency Stop..............................................................................................4-35
4.7.7 OP/CAL...........................................................................................................4-35
4.7.8 Error Detection ................................................................................................4-36
4.8 Optical Motion Interrupt (OMI) Board .....................................................................4-39
4.9 The Laser Board ....................................................................................................4-41
4.10 DPX-IQ Mechanics ................................................................................................4-43
Chapter 4 Technical Description

4.1 The AMP Board
Circuit Functions
• Amplify charge pulses from the PMT
• Shape the signal into a stable bipolar pulse
• Drive the pulse down a 50 Ω coaxial cable to the AGS board
The input to the AMP-04 circuit is a PMT/NaI charge pulse and output of the circuit is a
700 nsec bipolar pulse (3 Vpp) into 50 Ω.
4.1.1 Circuit Description

The AMP-04 amplifies charge pulses from the detector system operating at +600 to +800 Volts,
shapes the signal into a stable bipolar pulse, and drives the pulse down a 5.1 meter 50 Ω
coaxial cable. Maintaining constant pulse shape at high counting rates is a prime goal.
Pulses of charge from the PMT are passed through a 2200 pF voltage blocking capacitor
located in the PMT high voltage power supply. The input pulses go through the virtual ground of
the current to voltage converter formed from U1. R2 discharges C5 when the amplifier is in the
power-off state. The rise time of the pulse is set by the 6 MHz bandwidth of the current to
voltage converter, and the fall time reflects the 230 nsec decay of the NaI crystal. The
amplitude of the pulse is determined by the 3K Ω value of R3 and the voltage of the PMT
(approximately 700 Volts for the 200 mV signal with 100 KeV photons). The components of the
current to voltage converter (R3, C7, C6, C12) were chosen to maximize the output signal while
retaining stability and a large bandwidth. These values provide a flat 6 MHz bandwidth for input
capacitances of up to 100 pF.
The pulse shaping network composed of R6, R7 and C13 shortens the pulse. C13 and R7 set
the decay of the pulse to 100 nsec. The addition of R6 to this circuit cancels the 230 nsec
decay of the NaI crystal. The signal is then amplified by U2, an amplifier with a voltage gain of
16 and a bandwidth of 6 MHz.
C14 shapes the unipolar pulse into a bipolar pulse. This AC coupling also removes the effect of
after glow in the NaI crystal and DC drift problems in U4. The bipolar signal is amplified with a
voltage gain of 4.3 in U3, and passed to U4, a 50 Ω line driver. Two voltage amplification
stages were used to provide low DC drift with good high counting rate performance. Capacitor
clamping prevents fluctuations in the power supply level when the output signal is clipped.
AMP Board 4-1

Figure 1 shows the unipolar output of the first stage of amplification (TP4). Figure 2 shows the
output after the second stage of amplification (TP5). The last figure is the output of the line
driver and the output of the board (TP6).
4-2 AMP Board

Test Points
Test Point Signal
TP2 Input
First Amplifier Output
TP3
TP4 Second Amplifier Output
TP5 Third Amplifier Output
TP6 Output
TP7 +12 VDC
TP8 -12 VDC
TP9 Ground
Table 4.1.1
AMP Board 4-3

THIS PAGE LEFT BLANK INTENTIONALLY
4-4 AMP Board

4.2 The Automatic Gain Stabilizer (AGS)
Circuit Functions
• Amplifies high channel pulses
• Attenuates low channel pulses
Operations
The analog section of the AGS-05 consists of an input divider, an input unity-gain buffer, a
variable gain stage through the use of an N-Channel JFET, an amplification stage followed by
an AC coupling network, and an output unity gain current driver. The digital section consists of
an "AMPLIFY" and "ATTENUATE" pulse qualifier, an "AMPLIFY/ATTENUATE" mode indication
circuit, two 4-bit binary UP/DOWN counters, a "ROLLOVER/RELOAD" circuit, and a D/A
converter to control the gate voltage to the JFET for gain control.
4.2.1 Signal Input

A signal entering the AGS (TP4) sees 50 of input impedance and is divided by 4.24 before it
passes through a unity-gain high-output current buffer (U1-LH0002CN). The signal then passes
through two JFETs connected in series with their gates shorted to their sources (Vgs=0). This
way they have a constant drain to source resistance, and are the equivalent of series resistors.
The series JFET's (Q1 and Q2) are used to provide a thermally stable voltage divider with Q3.
4.2.2 Gain Modification

Gain control in the AGS-05 is accomplished through the use of N-channel JFETs (Q1, Q2, Q3, -
2N4391). The two JFETs with Vgs=0 are in series with a third JFET which has its gate voltage
modulated to vary its drain to source resistance. These three JFETs form a voltage divider with
the output taken from the lower JFET which has its gate voltage varied to provide a variable
output. The variation in signal seen at Q3's drain is a direct relationship to the variation of its
gate voltage. Because the thermal characteristics of the JFET's are similar, thermal stability is
enhanced by using three JFET's to form the voltage divider. Therefore, the effects of
temperature are canceled out and no ratio changes will result.
When an "AMPLIFY" pulse comes in from the AGSDCA it is qualified by U2 (74LS00) and the
counter pair (U3 & U4 - 74LS193) is incremented or "CLOCKED" up. When an "ATTENUATE"
pulse comes in it is qualified and the counter pair is decremented or "CLOCKED" down. The
counter outputs D0-D7 are connected to a D/A converter (U7 - AD558KN), the counter range is
from 00H to FFH with 80H being the center of the range. Two potentiometers (R20 & R18) and
an op amp circuit (U8 - LF351N) scales the DAC's output voltage and inverts it to drive the JFET
gate of Q3. If "ATTENUATE" pulses continue to clock the counters, they will clock down to 00H.
There the JFET gate voltage will be maximum (-4 to -6 VDC) and the AGS will be at a minimum
gain of 0.80 as set by R20. Unity gain of the AGS should be adjusted at a counter state of 80H
(center range) by R18. If "AMPLIFY" pulses continue to clock the counters, they will clock up to
FFH where the JFET gate voltage will be minimum (0VDC) and the AGS will be at a maximum
gain of about 1.50; this is not adjustable and will vary slightly because of differences in forward
transfer characteristics between JFETs.
AGS Board 4-5

4.2.3 Rollover
When the input signal to the AGS increases or decreases until it is out of range the AGS
counters rollover, and the CARRY or BORROW outputs of the MSD counter are gated back into
the LOAD inputs of the counters. If the counter rolls over at either end of the count interval (00H
or FFH), the counters will re-load 80H and the AGS will be reset to unity gain.
4.2.4 Operate/Calibrate (OP/CAL)

Also gated into the LOAD input is the Operate/Calibrate (OP/CAL) signal (TP11). For detector
peaking, the bipolar signal must be allowed to vary in order to find the optimum high voltage
setting for PMT bias. To perform this the OP/CAL signal is pulled LO for CAL and the AGS
counter is forced to output 80H which holds the AGS at unity gain. The AGS will remain at unity
gain as long as OP/CAL is held LOW. During normal stabilizer operation this signal is HIGH for
OP mode and the AGS will perform gain control.
4.2.5 Amplification Stage

An op amp (U9 - EL2006) configured as a non-inverting amplifier amplifies the signal by a factor
of 10 before it is AC coupled by an RC network. This RC network makes the low frequency
cutoff about 700 Hz, which blocks all DC offsets from reaching the AGS output amplifier and no
DC offset adjustments are necessary. There is an optional location for a DC offset adjustment
potentiometer (R31 - 10 k) if the AC coupling capacitor (C24 - 0.47uF) is opted to be shunted.
This amplification stage is needed to compensate for reductions in the system so that the
overall gain of the AGS at center range (in CAL mode where counter is at 80H) is unity. The
following is an equation of the AGS stage gains at unity:
INPUT VOLTAGE JFET AMPLIFICATION STAGE OUTPUT DIVISION

DIVIDER DIVIDER GAIN DUE TO DCA LOAD
0.24 X 0.55 X 10 X 0.75 = 1.00
4.2.6 Signal Output

The gain-adjusted signal is output driven by a unity gain current driver (U10-LH0002CN)
through a 10 Ω resister for short circuit protection. The current amplifier power pins are heavily
decoupled to ground to maintain clean power supply rails during peak driving conditions.
4.2.7 Amplify/Attenuate Indication

There are two LED indicators on the AGS that are driven by the same signals that increment
and decrement the counters. They visually indicate the gain adjustment occurring within the
AGS. Each time an "AMPLIFY" or "ATTENUATE" pulse comes in to the AGS, the
corresponding LED should flash. In the OPERATE mode the lamps should blink at a relatively
equal rate. If they are not blinking evenly it means that the AGS has not found a quiescent
adjustment point or that there is a break in the system feedback.
4-6 AGS Board

4.2.8 Performance and Operation

The best operation of the AGS is dependent on many different system operating parameters.
The characteristics of the tube head, high voltage power supplies, detector and amplifier all
have an effect on the operation of the AGS. When the x-ray beam is "hardened" or attenuated
and the count rate is reduced, the AGS adjustment is not critical. However, at the high count
rates of an unattenuated beam the system may require fine tuning for best performance.
4.2.9 AGS Adjustment

The need for an adjustment of the AGS is usually discovered during the acquisition of a fast
femur scan. White lines may appear in the image near the trochanter, or an area of white may
appear outside the bone, or the trochanter area may be too small when analyzed. If the normal
bag of rice (12 cm) placed along the thigh does not solve the problem, then the AGS operation
should be investigated.
Another symptom which indicates poor operation of the AGS is the appearance of white pixels
around the outside of the body in a total body scan. The effect is similar to a "halo" and so the
problem is referred to as a total body "halo" problem. If the problem is benign, it will only be
seen during acquisition, but if the problem worsens it will be seen in analysis as well.
NOTE: Unstable AGS operation during total body scans manifests itself as missing bone
pixels near the extremities of the skeleton.
AGS problems are usually caused by a failing detector. The first step in diagnosing this failure
should be to analyze the Quality Assurance History to see if the detector is failing, and replace it
if necessary.
For problems associated with misadjusted DCA's (see section 4.3), start with the recommended
DCA voltages :
DCA TEST POINT MEASUREMENTS IN VOLTS
DPXDCA AGSDCA
TP4 1.200 2.020

TP5 1.970 2.450
TP6 1.675 2.335
TP7 2.800 2.800
Table 4.2.1
These voltages are the settings which are currently used in the Lunar factory.
Use the static counter from the diagnostics software to set the operating voltage to 76 kV and
the current to 150A. This test may be performed with or without the table top in the x-ray
beam, but nothing else should be in the path of radiation. Open the shutter and observe the
AGS Board 4-7

counts. If the AGS is operating correctly, the low channel counts should be greater than the
high channel counts and both counts should be stable (approximately ±3000 counts from the
mean value). If the low channel counts are not stable or are lower than the high channel
counts, begin to adjust the AGSDCA (the DCA board in the rear of the scanner).
If an oscilloscope is available, adjust DCA-T4 until AGS-TP12 does not rollover. An example of
a stable AGS signal as seen at TP12 is shown in figure 1.
Use the aluminum wedge to perform the AGS Test (see section 6.2) and check the scanner's
ability to give reasonable counts.
4-8 AGS Board

4.2.10 Test Points and LED's

There are two LED's on the AGS board. The amber LED signifies an Amplify signal from the
AGS DCA board. The green LED signifies an Attenuate signal from the AGS DCA board.
These two LED's should flash quickly enough during a scan as to appear to be on constantly. If
they are not, no counts are reaching the AGS board through the AGS DCA.
Test Point Signal
TP1 +12 VDC
TP2 GND
TP3 -12 VDC
TP4 Signal Input
TP7 Attenuate
TP8 Amplify
TP11 OP/CAL
TP12 Regulation
TP14 +5 VDC
TP15 GND
TP19 Output
TP20 GND
AGS Board 4-9

4-10 AGS Board

4.3 The Dual Channel Analyzer (DCA)
Circuit Functions
• Discriminate energy levels
• Send TTL pulses to SBC board (DPXDCA)
• Send Amplify/Attenuate signal to the AGS board (AGSDCA)
4.3.1 Function Description

The input signal is first conditioned by the input diode clamp circuit. This limits the input signal
to a range of -0.7 VDC and +4.0 VDC thereby protecting the comparators from excessive input
differential voltage. The signal passes to the two pairs of comparators. The Lower Level
Discriminator (LLD) triggers as the input rises past the threshold of either 1.25 VDC (38 keV) or
2.00 VDC (for 70 keV). This produces no pulse at that channel's output (300 ns or OUT). If the
signal reaches and exceeds the Upper Level Discriminator (ULD), a signal level is set for
inhibiting output (OUT INH). If the signal does not reach the ULD, then no inhibit level will be
set.
When the input signal falls below the lower threshold (LLD), a 300 ns TTL level pulse is
generated and is gated with the output inhibit flag (OUT INH) which either enables or inhibits the
output pulse. Once the pulse is observed at the output, it will not be prematurely inhibited by
any stray ULD level. The output signal is then sent to the SBC event counter via J3.
4.3.2 Circuit Analysis and Operation
Input Circuit
The input impedance requirement of the circuit is 90 . This is achieved by R1, a shunt to
signal reference. The input is current limited by R2 and clamped to a range from +4 VDC to -
0.7 VDC by resistors R3 and R4, diodes CR1 and CR2 and capacitor C0. (The differential input
voltage for the LM306 is ±7 VDC max.) The signal is then fed to the inverting input of each
comparator.
Precision Voltage Reference

In order to accurately discriminate between energy levels, a stable reference is required. The
reference is set to 5V by using an LT1029ACZ (U1).
Comparators
Each ULD comparator in the circuit has a 220 Ω resistor in series with the non-inverting input
and a 1MΩ resistor (e.g. R26 and R36 for U2) in the feedback loop to provide the necessary
hysterisis. A 150 kΩ resistor and a 1N5817 diode provide the hysterisis for the LLD
comparators. A 0.1µF ceramic filter capacitor is attached from each reference divider to analog
ground to improve noise immunity when using potentiometers.
DCA Board 4-11

Lower Level Discriminator (LLD)

Each lower level discriminator drives a Schottkey NAND gate (both inputs), thus inverting the
signal. The signal is then NANDed with the Retrigger Inhibit signal to avoid retriggering and
possibly extending the output pulse width. This pulse charges C14 or C15. The charge and
discharge time determines the pulse width of the DCA output. This pulse is available at the
output driver (U10) and is passed through if the ULD has not been reached.
Upper Level Discriminator (ULD)

If the ULD references are exceeded, the preset of a D-type flip-flop (U8) is asserted. The output
of the flip-flop is NANDed with the current inverted output so as not to prematurely terminate the
output once it has started. The positive going transition of the Retrigger Inhibit pulse, which
occurs at the end of the DCA event pulse, will clock the flip-flop. The flip-flop output is set LOW
by this rising clock edge, and OUT INH will be inactive allowing subsequent output.
Output Driver
The output driver selected was the DS75121 or N8T13 dual line driver. It is essentially a low
impedance line driver with a logic AND input.
4.3.3 Technical Facts

Power Supply: +12V @ 0.175A, -12V @ 0.25A, +5V @ 0.200A
Input Impedance: 95 Ω
Output Current: approximately 5 mA
Output pulse width 300 ns (±50 ns)
4.3.4 Recommended DCA Settings
DPX DCA AGS DCA

TP4 1.200 2.020
TP5 1.970 2.450
TP6 1.675 2.335
TP7 2.800 2.800
These voltages are the settings which are currently used in the Lunar factory.
4-12 DCA Board

4.3.5 Test Points
Test Point DPX DCA AGS DCA
TP1 Ground Ground
TP3 Input Input
TP4 Channel 1 Lower Limit Channel 1 Lower Limit
TP5 Channel 2 Lower Limit Channel 2 Lower Limit
TP6 Channel 1 Upper Limit Channel 1 Upper Limit
TP7 Channel 2 Upper Limit Channel 2 Upper Limit
TP8 LLD Channel 1 LLD Channel 1
TP9 LLD Channel 2 LLD Channel 2
TP11 ULD Channel 1 ULD Channel 1
TP12 ULD Channel 2 ULD Channel 2
TP15 Digital Ground Digital Ground
TP16 Low Channel Counts Amplify
TP17 High Channel Counts Attenuate
DCA Board 4-13

4-14 DCA Board

4.4 The MAX Board
Circuit Functions
• Control x-ray tube current
• Regulate current to Filament Transformer
Operations
The MAX board and the filament transformer in the Tube Head form a power supply that
regulates current in the X-ray Insert by controlling the filament temperature. As the filament
temperature increases, there are more electrons available to be accelerated to the anode.
The SBC sends a control signal to the MAX board at J6 (which can be measured at TP11). The
voltage of this signal is proportional to the desired current through the X-ray Insert. A one volt
signal from the SBC should yield a 1.0mA insert current. The Positive High Voltage Power
Supply will put a 1.0VDC signal on the MA MONITOR output which is routed to XORB TP5 and
finally MAX J2 (TP8). This voltage is buffered by U2B and returned to the SBC at J5 (TP9) as a
feedback monitor.
The board is divided into seven functional sections. These sections are:
1. Filament Transformer: While the filament transformer is in the Tube Head enclosure
and not actually on the MAX, it is really the transformer's output that the MAX controls.
The center-tapped primary winding is wound on a small ferrite core. Each end of the
primary is driven by one of the two power FET's (Q1 or Q2). The voltage at the
transformer's center tap (TP13) is what determines the power output to the insert
filament.
The secondary winding is made of high voltage cable wound on top of the primary
windings. The secondary drives the insert filament, supplying up to about 2.5 Amps.
MAX Board 4-15

2. Power FET's and Snubbing Network: The IRF 530 power FET's, Q1 and Q2, are
power switches driven by U4. They pull the filament transformer leads to ground, thus
driving the transformer. The snubbing network is connected across the drains of the two
power FET's. This network consists of R1, C7, and the two MOV's, VR1 and VR2. This
network is intended to absorb the transient spikes created by the rapid switching of
current in the primary of the filament transformer.
3. FET Driver: The FET driver consists of U4, an SG3525 switch mode power supply
controller. However, on the MAX board it is used as an oscillator providing two 180
degree phase shifted outputs to drive Q1 and Q2. It has open collector totem-pole
outputs connected to a 12-volt source that is separate from the rest of the board to keep
switching noise out of the 12 volt supply. R15 and C16 set the operating frequency of
the MAX at 16-17 kHz. R2 and R3 set the symmetry (i.e. on versus off times) of the
square wave outputs. They set both outputs at about 49% on time, 51% off time, slightly
under a 50% duty cycle. R16 sets the dead time between one output switching off and
the other switching on.
This dead time prevents Q1 and Q2 from turning on simultaneously, shorting the positive
center tap of the filament transformer to ground. R10 and C3 provide some power
supply decoupling. R18 and R19 slow the charging/discharging time of the gate
capacitance of Q1 and Q2. This causes them to turn on and off more slowly and helps
reduce some of the switching noise a faster rise/fall time would produce. The wave
forms at the gates of Q1 and Q2 are seen at TP1 and TP2.
4. Feedback Buffer AMP: The mA input buffer amp (U2B) receives its input from J2, the
mA feedback input connector when. This signal comes from the mA MONITOR output
of the Positive High Voltage Power Supply. It is in the form of an 0 to 5 VDC signal,
corresponding to a 0 to 5 mA current output. Op amp U2B buffers this signal. The
output goes to J5, the mA feedback output connector, is inverted by U3A and then goes
to the input of the error amp. The output at this connector goes to the SBC to allow it to
monitor the tube current. C8 filters AC components in the mA FEEDBACK input signal.
4-16 MAX Board

The mA input buffer amp receives its input from J2, the mA feedback input connector.
This signal comes from the mA MONITOR output of the Negative High Voltage Power
Supply. It is in the form of an 0 to 1 VDC signal, corresponding to a 0 to 1 mA current
output. U3A is used to buffer this signal. The output of the amp goes to the input of the
error amp and to J5, the mA feedback output connector. The output at this connector
goes to the SBC to allow it to monitor the tube current.
5. Error AMP: The other half of U3 (U3B), Q3 and Q4, comprise the error amp. In normal
operation (jumper JB2 in the normal position) a summing junction is applied to the
inverting input of the error amp. This voltage comes from the SBC via J6, the mA control
input. The mA CONTROL input voltage can be measured at TP11. The signal from the
output of U3A is applied to the summing junction of the error amp. The difference
between these two signals is amplified by U3B. The gain of this stage is set at about 24
by R29 and R31. The error signal and is fed to the base of Q3 which drives the base of
emitter follower Q4. It is Q4 that controls the voltage on the center tap of the Filament
Transformer and therefore the insert current.
MAX Board 4-17

As an example of loop operation, assume the insert current starts to drop from its 0.750
mA set point. The voltage at the input of U2B would start to drop. This would cause its
output to drop also. The error amp (U3B) compares the mA feedback voltage with the
mA control voltage and generates an error signal. This signal would be the difference
between the two voltages amplified by the gain of the error amp. This voltage is fed to
the base of Q3, causing it to start to turn off. As this happens, the base of Q4 increases
causing it to turn on further and increase the voltage on the center tap of the filament
transformer. This in turn increases the filament current and therefore the insert current
until it returns to its set point.
As for the rest of the components; R11, C6, R13, R27, R28, C10, C17 and C26
decouple U3 and U2 from noise on the +12 volt power supply; R6 provides base current
to Q4, turning it on unless Q3 holds it off; R7 limits current through Q3; C9 and C14
filters ripple and noise on the Filament Transformer center tap.
6. Logic and Driver Power Supplies: There are two +12V power supplies which consist
of two LM7812 voltage regulators. One power supply (TP20) is for the logic circuitry,
and the other supplies power (TP6) strictly to drive the power FET's. They have
separate chassis and signal grounds in an effort to keep switching noise out of the
control circuitry, and share a common ground only at the 28 volt input connector, J1
(TP10).
7. kV Lockout: This circuit prevents filament drive until the kV is high enough to assure a
stable start of control loop closure.
Prior to kV ramp-up, U2P2 is approximately 0 VDC and U2P3 is approximately 2.0VDC.

Therefore, U2P1 is at the +12V rail. This turns Q5 on through R35. When the +28VDC
power supply is turned on, a brief spike at TP13 will be seen as the slow start circuit
(C23, C24, R35 and R36) stabilizes. The filament drive (TP13) will be held low until the
kV monitor reaches the comparator trip point of approximately 2.0VDC (40 kV applied to
the insert).
As the trip point is reached, U2 changes state and the slow start circuit allows Q5 to turn
off slowly (10-20 ms). As Q5 turns off, control of the loop is transferred to U3B and Q3.
During normal operation of the control loop, Q5 is turned off and thus is out of the circuit.
Final Notes
1. There is a MAX board "test mode" which bypasses SBC control and external current
sensing. Then the insert current is controlled by adjustment of R4. To configure the
MAX board for the "test mode", set jumpers JB1, JB2, and JB3 to short pins 1, 2, and 3.
2. There are two light-emitting-diode indicators on the board. If the red LED is lit and the
green LED is out, the filament power fuse (F1) is blown. If both the red and green
indicators are out, there is no +28 VDC power to the board.
4-18 MAX Board

Test Points
Test Point Signal
TP1 Output A from U4
TP2 Output B from U4
TP3 Ground
TP4 Output of Q1 (Filament Drive signal)
TP5 Output of Q2 (Filament Drive signal)
TP6 +12 VDC
TP8 mA Feedback Input
TP9 mA Feedback Output
TP10 Signal Ground
TP11 mA Control
TP12 +28 VDC
TP13 Filament Drive signal
TP14 -12 VDC
TP15 Set Point
TP16 Emitter Follower Drive
TP17 Clamp Out
TP19 kV Sample
TP20 +12 VDC
MAX Board 4-19

4-20 MAX Board

4.5 The XORB Board
Circuit Functions
Provide protection to the system electronics from transients
4.5.1 Operations
The XORB board is designed to prevent high voltage transients, generated in the x-ray system,
from entering the rest of the DPX-IQ system electronics. The transient energy is decoupled to
the local chassis ground by three types of solid-state devices, described below. Since the high
voltage power supplies are tightly coupled and in close proximity to the XORB board, the energy
does not find its way into the rest of the system.
The XORB board also functions as an terminal for the signals that control and monitor the High
Voltage Power Supplies. Test points for all of the important high voltage control signals are
located on the XORB board.
Normally, the XORB board has no effect on any of the signals that pass through it. All of the
signals (including signal grounds) that pass through the board are connected to chassis ground
through one or more transient suppressors.
If a high voltage transient appears on one or more of the signal lines, and it exceeds the
threshold of the transient suppressor(s), it will be shunted to the chassis ground. Since the
source of the energy for the transients (the High Voltage Power Supplies) is tightly tied to the
chassis, the transient energy is efficiently returned to these supplies. This shunted energy
never reaches the DPX-IQ logic circuitry where it could cause damage.
The signals that appear on the XORB board are as follows:

• All connections to the solenoid assy.
• The Tube Head Thermocouple.
• The Tube Head Thermostat and Filament Transformer drive.
• All control signals to or from the High Voltage Power Supplies.
4.5.2 Solid State Transient Voltage Suppressors

Solid State Transient Voltage Suppressors are essentially just high power avalanche diodes.
They have a large die size, thus they can handle a large amount of power for a short time. They
have a specific voltage above which they begin to conduct, below which they appear as an open
circuit. There are two types on this board, 7.5 volt and 28 volt, depending on the circuit they are
protecting. The Solid State Transient Voltage Suppressors are used on almost all of the signal
lines that are not ground. The exception are the Filament Transformer drive signals which are
protected by Metal Oxide Varistors (MOV's).
MOV's are bipolar suppressors which will clamp at the same voltage above and below ground.
XORB Board 4-21

The 1N4004's are used in reverse - parallel combinations to clamp signal grounds to ± 0.7 volts
of chassis ground. They were chosen for their current handling ability.
Test Points
Test Point Signal
TP1 -A Monitor
TP2 -kV Monitor
TP3 -kV Programming
TP4 -V Reference
TP5 +A Monitor
TP6 +kV Monitor
TP7 +kV Programming
TP8 +V Reference
Use the anode side of one of the solid state transient voltage suppressors for ground.
4-22 XORB Board

4.6 The Single Board Controller (SBC)
Circuit Functions
• Count pulses from the DPXDCA
• Tube head high voltage and current control
• RS-232-C communications with host computer
• Motion control
• Limit switch and thermocouple sensing
Operations
The LRC Single Board Controller VER-03 (SBC-03) consists of a single circuit board that uses
the Intel 8032 microprocessor with a RS-232-C interface and up to 56k of memory (8k EPROM,
8k EEPROM, 8k NVRAM, and 32k RAM). The EEPROM is utilized to allow easy program
modification and the NVRAM is used to retain data during power loss.
4.6.1 Microprocessor and Memory (U1, U2, U4, U21, AND U22)
The memory decoding configuration is set to decode 8k x 8 blocks. The lower 56k is read/write
memory while the last 8k is used to decode the peripheral components (8254's, 8255's, etc.).
The maximum allowable access time is 250 ns for any memory selected.
U21 is designated as the "boot" location since the 8032 vectors to 0000H upon reset. This must
be nonvolatile. U22 contains the firmware that operates the SBC. U1 and U2 may be used to
store data or expand the firmware.
4.6.2 Address Selection

U6 (74LS138) is configured as the memory and I/O address decoder. Outputs Y0-Y6 are used
to access the memory while output Y7 is used to select yet another series of decoders U11 and
U34(74LS138's). U11 and U34 are arranged to operate as a 4-to-16 address decoder which
are used to access I/O. The following are pertinent addresses:
SBC Board 4-23

ADDRESS CHIP SELECT SELECTED DEVICE
0000H - 1FFFH U6P15 U21 (EPROM)
2000H - 3FFFH U6P14 U22 (EEPROM)
U6P13 U1 (NVRAM)
4000H - 5FFFH
6000H - DFFFH U33P6 U2 (RAM)
I/O DEVICES
E0X0H - E0X3H U11P15 U13 (8254 PMT COUNTS)
E2X0H - E2X3H U11P14 U14 (8254 REF COUNTS)
E4X0H - E4X3H U11P13 U9 (8254 TRANS MOTOR)
E6X0H - E6X3H U11P12 U10 (8254 LONG MOTOR)
E8X0H - E8X3H U11P11 U23 (8255 PORT A,B,C)
EAXXH U11P10 U48 (WATCH DOG TIMER)
F0XXH U34P15 U44 (558 AMP HV D/A)
F2X0H - F2X3H U34P14 U35 (574 12-BIT A/D)
F4X0H - F4X3H U34P13 U41 (8255 PORT D,E,F)
F6XXH U34P12 U38 (670 THERMO A/D)
F8X0H - F8X1H U34P11 U36 (667 KV D/A)
FAX0H - FAX1H U34P10 U37 (667 MA D/A)
"X" Represents a "Don't Care" condition; any hexadecimal character will yield a valid address to
select these devices.
4.6.3 RS-232-C Interface (U7 & U8)

A MAX251 and MAX250 chip set provides the interface between the 25-pin D-connector and U4
(8032). The interface consists of a MAXIM MAX251 and MAX250 chip set, four (4) 6N136
optocouplers used for optical isolation, and a Schott Corp. isolation transformer (67129080)
providing power to the isolation source. This design supports a data transmission rate of up to
57.6 kBps (kBaud). It also provides a minimum of 1500 volts isolation for one minute between
the port and the SELV circuitry.
4-24 SBC Board

Table 4.1.7 summarizes the signals routed between the acquisition computer and the serial
interface.
Input Pin# Output Pin # Signal
U7P10 U8P9 DTR (Microprocessor Reset)

Data Terminal Ready
U7P9 U8P12 RXD (Receive Data)
U8P4 U7P12 TXD (Transmit Data)
U8P5 (RTS) U7P11 (CTS) RTS (Request to Send)

CTS (Clear to Send)
Table 4.1.7 - Serial Interface Signals
SBC Communications
The Acquisition Computer and the EXPD-SBC board communicate via a standard RS-232 serial
communications link. Instructions to/from the computer are sent via this link through the
optically isolated serial I/O interface, and from/into the 8032 microprocessor chip located on the
EXP-Daughter board.
The serial communications signals are summarized in table 4.1.7. The baud rate and protocol
are set using special registers within the 8032. The serial port is set as COM2 and the interface
serial communications parameters used are as follows:
Baud Rate 9600 - 57.6 kBaud

Data Bits 8
Stop Bits 1
Parity Even
4.6.4 System Reset (U8, SW1)

The LRC SBC-03 may be reset by pressing the momentary switch (SW1). This pulls U4P9 high
and "reboots" the 8032 causing it to vector to address 0000H.
SBC Board 4-25

4.6.5 System Clocks (X1, X2, U15)

A 11.0592 MHz quartz crystal (X1) in a dual-in-line package (DIP) generates TTL level pulses at
X1P8. This provides the driving input to the 8032.
A 2.0 MHz quarts crystal (X2) in a DIP generates TTL level pulses at X2P8. This provides the
clock signals to U9 and U10 (8254's) that generate the motor pulses. This clock is further
divided down by U15 (74LS163) to provide a 125 KHz clock signal to U13 which is used to
create the sample count interval.
4-26 SBC Board

4.6.6 Event Counting (U13, U14, U17, U18, U19, U20, J1, J2)
Two Intel 8254's (16-bit timer/counters) U13 and U14 are used to generate the count interval
and count the individual events from the LRC DCA-03 boards. U13 is used to generate the
count interval and to count events from the PMT through J2. High speed opto-couplers (HCPL-
2200's) U17-U20 are utilized for isolation and noise reduction.
Counter 0 of U13 is operated in mode 3 to generate the count interval by interrupting the 8032
(INT1) causing it to vector to the data acquisition routine. The clock line of Counter 1 (mode 2)
U13 is used to count events from Channel 1 (J2P3). Likewise Counter 2 (mode 2) U13 is used
to count events from Channel 2 (J2P1). Counters 1 and 2 on U14 could be used in the same
configuration as counter 1 and 2 on U13 to count the other events. The 8254 can count up to 8
MHz, which is well above the limit dictated by the DCA output pulse width of 0.3 µs (3.3 MHz).
4.6.7 Stepper Motor Control (U9, U10, U31, U32)

Independent open-loop control of two stepper motors is accomplished by programming the
8254's (U9 for the transverse motor and U10 for the longitudinal motor) to generate square
wave pulses (in an a stable multi-vibrator configuration). Motor selection and direction is
controlled by Port A of U23 (8255). B4 of Port B of U23 is read to determine whether U9 is
generating motor pulses and B5 of Port B of U23 is read to determine if U10 is generating motor
pulses.
The three counters of each 8254 (U9 and U10) operate in the following manner. Counter 0
outputs the motor pulse while CLK2 on Counter 2 is connected to OUT 0 and counts the pulses
(their gates are common). Counter 2 is preloaded with 10, and when it reaches 0, OUT 2 goes
low enabling Counter 1 at CLK1. When Counter 1 (gate enabled by an output on U23) reaches
the preloaded number of steps, OUT 1 goes low and disables both Counter 0 and Counter 2.
Hence Counter 2 is the prescaler (x10). If Counter 1 is loaded with 300 steps, the 3000
microsteps (3000 pulses) are output from Counter 0.
When U15P1 is low, closure of limit switch 3 or 4 will stop the transverse motor (U12P6) as well
as close the solenoid. When U15P38 is low closure of limit switch 1 or 2 will stop the
longitudinal motor (U12P3) as well as close the solenoid. When U15P1/U15P38 is high, the
state of the limit switch circuitry (U27 and U31) is "overridden" and the motors will continue to
step. This is necessary to move the carriage off any limit switch such as when the scanner is
"homed".
4.6.8 Limit Switch Sensing (U27, U31)

Four limit switches are sensed via two IC's (U27 and U31) yielding a Schmitt triggered AND
configuration which will close the solenoid (source shutter) via U33P8 and stop the motors (if
U15P1/U15P38 is low) when a limit switch is closed, causing a "Shutter Failure". A 4.7 kΩ - 2.2
µF debouncing network is connected to each limit switch via J4 and J5.
SBC Board 4-27

4.6.9 I/O Ports (U23, U41)

As discussed in previous sections, the 8255's are used for all I/O output. Port A controls the
motor selection, solenoid, and collimator. Port B is a input port and senses limit switches, motor
status (running or stopped), shutter closure, and collimator position. Port C is configured to be
half in and half out. The lower four bits are used to sense the position switches while the upper
four bits are used as outputs to turn on power to the motors, place the AGS in OP/CAL mode,
override the motion detection circuitry on the OINK-02, and turn on the relay for the x-ray power
supplies. Port D is used to control an analog multiplexer on the SBC which will be discussed
later, also controls the patient locator light, and doubles as a control for the x-ray relay and the
motion detection selector for safety reasons (if one 8255 malfunctions the other 8255 will still be
able to deactivate these lines). Port E is used to read the scanner failure latch to find out what
caused the scanner to fail. Port F is presently unused.
U23 I/O BIT ASSIGNMENTS
HEX DATA P/N SIGNAL DESCRIPTION

ADDRESS BIT
E8X0H PA0 4 TRAN RUN/HOLD 0=HALT, 1=RUN
PA1 3 TRAN REV/FWD 0=FORWARD, 1=REVERSE
PA2 2 SHUTTER 0=OPEN, 1=CLOSE
PA3 1 TRANS OVERRIDE 0=DO NOT, 1=OVERRIDE LSW
PA4 40 LONG RUN/HOLD 0=HALT, 1=RUN
PA5 39 LONG REV/FWD 0=FORWARD, 1=REVERSE
PA6 38 LONG OVERRIDE 0=DO NOT, 1=OVERRIDE LSW
PA7 37 COLLIMATOR 0=SMALL, 1=LARGE COLL
E8X1H PB0 18 LMT SWITCH 4 0=CLOSED, 1=OPEN
PB1 19 LMT SWITCH 3 0=CLOSED, 1=OPEN
PB4 22 TRANS MOTOR SENSE 0=STOPPED, 1=RUNNING
PB5 23 LONG MOTOR SENSE 0=STOPPED, 1=RUNNING
PB6 24 SHUTTER SENSE 0=OPEN, 1=CLOSED
PB7 25 COLLIMATOR SENSE 0=SMALL, 1=LARGE
E8X2H PC0 14 LR POS SW 0=LONGREV
4-28 SBC Board

PC1 15 LF POS SW 0=LONGFOR
PC2 16 TR POS SW 0=TRANREV
PC3 17 TF POS SW 0=TRANFOR
PC4 13 X-RAY RELAY 0=ON, 1=OFF
PC5 12 MOTION DET OVERRIDE 0=OVERRIDE, 1=NORMAL
PC6 11 AGS CONTROL 0=CALIBRATE, 1=OPERATE
PC7 10 MOTOR PWR RELAY 0=ON, 1=OFF (+24V)
E8X3H 8255 U15 CONTROL WORD = 83H PA OUT, PB IN, PCL IN, and PCH OUT
U41 I/O BIT ASSIGNMENTS
HEX DATA P/N SIGNAL DESCRIPTION

ADDRESS BIT
F4X0H PD0 4 LSB OF U42 MUX CONTROL SELECTS INPUT TO U42
PD1 3 MSB OF U42 MUX CONTROL SELECTS INPUT TO U42
PD2 2 N/C UNUSED
PD3 1 N/C UNUSED
PD4 40 X-RAY RELAY 0=ON, 1=OFF
PD5 39 MOTION DET OVERRIDE 0=OVERRIDE, 1=NORMAL
PD6 38 N/C UNUSED
PD7 37 PAT LOCATOR LIGHT 0=ON, 1=OFF
F4X1H PE0 18 THERMOSTAT ERROR 0=YES, 1=NO
PE1 19 E-STOP BUTTON ENGAGED 0=YES, 1=NO
PE2 20 28 V PWR SUPPLY FAILURE 0=YES, 1=NO
PE3 21 TRANS MOTOR FAILURE 0=YES, 1=NO
PE4 22 LONG MOTOR FAILURE 0=YES, 1=NO
PE5 23 N/C UNUSED
PE6 24 N/C UNUSED
PE7 25 STOP BUTTON POSITION 0=ENGAGED, 1=NOT ENGAGED
F4X2H PORT F IS UNUSED
SBC Board 4-29

F4X3H U41 CONTROL WORD = 82H PA AND PC OUT, PB IN
"X" in the address indicates a "Don't Care" condition; any hexadecimal character will yield a
valid address for the device.
4.6.10 Watch Dog Timer (U48)

The watch dog timer provides an orderly system shut down if a malfunction occurs with the
8032, the address lines, data lines, memory or peripheral devices. It will reset the SBC-03 if it is
not pulsed at least once every second. Counter 0 of U14 is programmed by the 8032 to provide
a 0.5 second pulse that interrupts the 8032. When the 8032 gets interrupted, its primary task is
to pulse the watch dog timer to prevent the reset signal.
4.6.11 D/A (Remote Detector Amplifier High Voltage) Control (U44, U45)
An 8-bit AD558 (U44) sits on the data bus and latches the values to be output when U44P10 is
strobed by the decoder. An integral on chip-op amp then drives the non-inverting input of the
OP-77 (U45P3) which is configured as a differential amplifier. R43 provides the offset voltage to
U45P2 which sets the output offset of U45. A DC offset is required in order to operate the high
voltage supply in the 600-800 VDC region of interest. R44, R45, R47, R48, R49, and R51 were
selected to yield approximately a 1 volt increment for each single D/A set point increment (e.g.,
a D/A transition of 212 to 213 would increase the high voltage by approximately 1VDC). D2
clamps the output at 8.2VDC to prevent over voltages (9VDC maximum input control to the HV
supply).
4.6.12 D/A (Remote X-ray High Voltage and Current) Control (U36, U37)
Two 12-bit AD667's are used to set the high voltage and current in the X-ray Insert. U36 and
U37 are set up to provide a linear 0 - 5 volt output. U36 is used to provide the control for the
high voltage. Its relationship to the high voltage is that the 0 to 5 volt output of U36 corresponds
to a 0 to 100 kV output in the voltage. This control voltage (U36P2) is connected to a positive
50 kV power supply and a negative 50 kV volt power supply so it can be said that a 1 bit change
on U36 is a 244.14 volt change in the high voltage.
U37 is used to provide control for the X-ray Insert current. The 0 to 5 volt output of U37
corresponds to a 0 to 5 mA output in the insert current (i.e. a 1 bit change on U37P2 is a 1.22
µA change in the insert current).
4-30 SBC Board

4.6.13 A/D (Remote X-ray High Voltage, Current and Amplifier High Voltage
Feedback Sense) (U35, U40, U42, AND U43)
U35 is a 12-bit A/D that is used to sense the high voltage setting, the X-ray Insert current, and
the Detector amplifier high voltage. U40 is a 5 volt reference for U35. U41 is a 8 to 1 analog
multiplexer that is controlled by two bits on Port D of U41. Depending on the setting of these
bits, U42 allows either the positive high voltage feedback, negative high voltage feedback, X-ray
Insert current feedback, or the Detector amplifier high voltage feedback to pass through to
U43P3. U43 is a unity gain op amp that passes its signal to the input of U35P13. U35 then
senses this voltage and places its digital value on the data bus when the 8032 requests it.
4.6.14 Thermocouple Sense (U38, U39)

U38 and U39 are used to sense the Tube Head temperature. U39 is a thermocouple amplifier
that converts its thermocouple input to an output that corresponds to a 10 millivolt change per
degree Celsius. This output voltage U39P9 is sent to U38P18
which is a 8-bit differential A/D that is set up so that a 10 millivolt input voltage change creates a
one bit change in the digital value. So, a one degree Celsius change in Tube Head temperature
creates a one bit change in the A/D value of U38 that gets read by the 8032.
SBC Board 4-31

Test Points
Test Point Signal

TP1 +5 VDC
TP2 +12 VDC
TP3 -12 VDC
TP4 GND
TP5 11.0592 MHz
TP6 2.0 MHz
TP7 125 kHz
TP8 Transverse Pulse
TP9 Longitudinal Pulse
TP14 mA OUT
TP15 kV OUT
TP16 +kV FEEDBACK from XORB
TP17 mA FEEDBACK from MAX
TP18 PMT HV FEEDBACK
TP20 AMP HV PROGRAM
TP21 RESET
TP24 -kV FEEDBACK from XORB
TP25 ISO GND
TP26 ISO +V
TP27 ISO -V
4-32 SBC Board

4.7 The OINK Board
NOTE: This discussion covers revision E and higher OINK boards. The theory holds for
02C boards but the components have changed. For compatibility issues please
see DXSE0003, DXSE0025, and DXSE0026 in Chapter 6.
Circuit Functions
• Motor Control
• Laser Control
• Collimator Control
• Fan Control
• Indicator Control
• Emergency Stop Detection
• Error Detection
4.7.1 Motion System
Motor Control
Motor control signals (TRANS & LONG: PULSE, RUN/HOLD, AND REV/FWD) are applied to
the OINK at J1, a dual-row 16-pin connector which comes from the SBC (J3). Each signal is
buffered through one channel of U1, the 7407. Buffering assures that these signals can sink 16
mA when LOW (i.e. are true TTL).
The buffered signals leave the OINK through J6 and J7, and connect directly to the micro
stepper motor controllers (Centents). R35 and R36 are bias resistors, matched to the stepper
motors, specified in the Centent manual. The OINK adds optical isolation to the RUN/HOLD
lines. Please refer to DXSE0003 (Chapter 6) for replacement compatibility information.
Position Controls
Signals from the control panel rocker switches are brought in to the OINK via J12, optically
isolated by ISO5, and sent to the SBC via J2. C31 through C34 provide debouncing.
Motion Detection
If the Tube Head Carriage should stop during a scan, undesired exposure may occur. Circuitry
on the OINK senses loss of motion and can cut the +28VDC supply via K1. Slotted disks
mounted on the motor gears interrupt an infra-red beam from an optical sensor. The pulses
created by the sensor arrive at J13 and J14. If they should time out at U7, K1 shuts down the
+28 VDC power to the MAX board.
U8 and U9 provide delay to allow use of both the rising and falling edges of the pulses for better
resolution. SBCO-RIDE (active LOW) enables U10, and pulses are counted at U7, a one-shot.
U7 is reset by the pulses from the optical sensors. After each reset, pin 7 or pin 15 drop down
to 0.7V and then C27 or C31 begin to charge. If either capacitor reaches roughly 2.1V before
OINK Board 4-33

the next pulse from the optical sensor arrives, a LONG INT signal (TP8) or TRANS INT signal
(TP7) is created. The transverse time out is set at 2.5 seconds at U7A. The longitudinal time
out is set at 20 seconds at U7B.
When SBCO-RIDE is asserted, U4B gates an interrupt signal should either half of U7 time out.
A motion failure or a dropout of the +28VDC supply, sends an interrupt (U5) to the SBC shutting
down the Tube Head. When SBCO-RIDE is LOW, the longitudinal and transverse motion
detection systems are prevented from interrupting the SBC. This is the state of the scanner
except when a patient scan is in progress.
Revision E and higher OINK boards require that R1 on the OMI board be removed. R1 is
required for revision 02C OINK boards however. Please refer to DXSE0003 (Chapter 6) for
further information.
Motor Kill
The MOTOR KILL signal comes from the SBC via J2P9. It is active HIGH, and held LOW
during OINK operation. When LOW, it turns on Q7, which in turn energizes relay K3, closing
solid state contacts, keeping +26VDC applied to J6 and J7 (Centent motor controllers). In case
of undesirable operation, MOTOR KILL would be set HIGH, the +26VDC would be killed to the
Centents only, and motor action would stop. A 1N6283 Zener diode on the 26VDC line on the
motor side of the motor kill relay suppresses transients caused by the collapsing field in the
motor when the motor kill relay opens.
4.7.2 Patient Locator Light

This signal is applied to the OINK at J1P11. It controls one of ISO4's isolators, which turns on
Q6, a PNP transistor used for its current drive. The signal leaves at J8 to the Laser PCB.
4.7.3 Collimator Control
Solenoid Control
The two solenoids (shutter and collimator) are actuated in response to signals from the SBC
which enter the OINK at J1. As with the locator light, one of the ISO's is used to control a PNP
transistor. Current is controlled by an RC network consisting of a 470uF capacitor and an 75
ohm resistor. The resistor is twice the working resistance of the solenoid, and allows only a
9VDC final drop across the solenoid. The capacitor allows an initial inrush of current when Q5
or Q4 delivers +26VDC before the capacitor charges. RC = 38ms.
Collimator Limit Switch Detection

Two limit switches are mounted on the collimator assembly of the scanner, one for the shutter
solenoid, one for the collimator solenoid. When activated, they are sensed through J11,
debounced, and sent to the SBC via J1.
4.7.4 Fans
There are two fans on the Tube Head, wired in series, powered by the +26VDC power supply.
They hook up at J26. The fans are on at all times.
4-34 OINK Board

4.7.5 Indicators
Shutter Open Light

This signal from a limit switch on the Shutter/Collimator Assembly is applied to the OINK at
J11P3. The limit switch is closed when the Shutter is opened. The signal returns to the SBC
from J1.
Shutter Open Light Safety Circuit

This circuit ensures that a burned out LED condition will prevent the shutter solenoid from
opening. Q2 enables the ground return for the Shutter Solenoid depending on lamp continuity.
If the LED is burned out, there is no path from the +26VDC (Q3 emitter), through R50, to the
base of Q2. +26VDC is therefore held at the base of Q4, and the solenoid will not actuate.
When the LED is intact, voltage is available (current flow through R50, the lamp, R52, and R53
to the base of Q2), enabling the grounding of ISO3.
X-ray On Light
This signal, in the form of current feedback indicating current to the tube head, is applied to the
OINK from the SBC at J1P10. Determination of Insert current greater than ≈41µA is made at
U11, an LM111 comparator. If current is detected, a signal is passed through ISO4 and leaves
on J8.
Power On Light
Power on for the entire scanner is indicated by the presence of +26VDC to the OINK. J5 sends
this voltage to the lamp on the Control Panel.
End of Exposure Alarm

An OR gate, U9, senses either the shutter solenoid limit switch reopening or dropout of Insert
current. This controls a channel of ISO3, and a relay. A sharp "ping" sound is heard, indicating
a "safe" condition. J22 leads to the alarm itself.
4.7.6 Emergency Stop

The Control Panel Emergency Stop button's normally closed contacts come to the OINK at J17,
and apply power to relay K1. When K1 is on, +26VDC is applied at J16 to a relay which
controls the +28VDC power supply. The relay coil is also wired in series with the Tube Head
Thermostat. Should either the Thermostat open up or the E-stop button be pressed, power
drops out from the relay, and +28VDC drops out to the HV power supplies. These conditions
are also fed to the SBC via ISO1, U8, U1, and finally J18, another dual-row 10-pin header.
4.7.7 OP/CAL
The OP/CAL signal is also routed through the OINK from the SBC to the AGS.
OINK Board 4-35

4.7.8 Error Detection

The OINK board monitors five hardware errors; transverse and longitudinal motion errors (see
Motion Detection in section 4.7.1), +28 VDC power supply faults (input at J2 pin6), emergency
stop conditions (input at J17), and tube head thermostat errors (input at J15). If one of these
errors is asserted, it is latched by U1, and is reported to the SBC via J18. At the same time, an
interrupt pulse is sent to the SBC via J19 to reset the microprocessor and thereby halt system
operation. The following table summarizes possible readouts of U1 and the corresponding error
messages reported by the software.
OINK U1 Hexadecimal Errors

Equivalent
Q4 Q3 Q2 Q1 Q0
0 1 1 1 1 15 Transverse Motion
1 0 1 1 1 23 Longitudinal Motion
1 1 0 1 1 27 +28 VDC Power Supply
1 1 1 0 1 29 Emergency Stop Condition
1 1 1 1 0 30 Tube Head Thermostat
1 1 1 1 1 31 Any of the Above
4-36 OINK Board

Test Points
For Rev. 02C For Rev. E and Signal

Higher
TP1 TP16 +5 VDC
TP2 TP15 +5 GND
TP3 TP14 OP/CAL
TP4 TP13 Motor Kill
TP5 TP17 Transverse Run/Hld
TP6 TP12 Transverse Pulse
TP7 TP1 +26 VDC
TP8 TP2 +26 GND
TP9 TP18 Longitudinal Run/Hld
TP10 TP11 Longitudinal Rev/Fwd
TP11 TP10 Transverse Rev/Fwd
TP12 TP9 Longitudinal Pulse
TP13 TP8 Longitudinal Interrupt
TP14 TP7 Transverse Interrupt
TP15 TP19 +28 GND
TP16 TP20 +28 VDC
TP17 TP6 Interrupt
OINK Board 4-37

4-38 OINK Board

4.8 Optical Motion Interrupt (OMI) Board
Circuit Functions
Reports Motion to the OINK board
Operations
Optical Motion Interrupt (OMI) boards are used to detect motion in both the X and Y axes. As
the carriage moves transversely, a slotted disk attached to the pulley near the front of the
scanner rotates through a slot in a OMI board, interrupting an infra-red beam of light. This
creates the signal in figure 1 that is sent to the OINK board. Another slotted disk is attached to
the foot-end pulley to detect longitudinal movement (see figure 2). If the appropriate signal is
absent while there is supposed to be movement, an emergency stop condition will occur.
OMI Board 4-39

4-40 OMI Board

4.9 The Laser Board
Circuit Functions
• Regulation of the power to the Laser
• Send power to Laser indicator
Operations
The Laser Board is mounted next to the detector in the upper arm. The board has two J
connectors, VIN and VIDEO OUT. VIN is the power to the board and is controlled by transistor
Q1 on the OINK board. VIDEO OUT connects to the LED on the front panel. Both the LED and
the laser are lit when there is power to the board. The laser itself is hardwired to the board and
cannot be ordered separately.
It is possible to destroy transistor Q1 on the OINK board by grounding D1 or C1 on the Laser

board when the power to the laser is on. There is a grounding wire attached to the laser board
with one of the mounting screws, if any additional grounding wires are attached at this point, it is
possible to short D1 and C1 to ground as the screw is tightened.
The following table has the laser specifications.
Specifications Laser Specifications Laser
LUNAR Part 1462 Aspect Ratio 4 to 1

Number
Output Power <1 mW Divergence 0.2 mrad
Wavelength 670 nm Astigmatism 11 microns
Frequency Drift 0.25 nm/C Laser Lifetime 50,000 hours
Laser Structure Gain guided Optimal Spot 500 microns
Laser InGaAIP Bore Sighting 2 mrad

Composition
Spatial Mode Single Current Draw 105 mA
Longitudinal Multiple Voltage Input 4-6 VDC

Mode
Beam Dimensions 3.3/0.8 mm Safety Rating Class II
Laser Board 4-41

4-42 Laser Board

4.10 DPX-IQ Mechanics
Motors and Controllers

Both the Transverse and Longitudinal Stepper Motors are controlled by Centent CN0142 Micro-
step Drives. These are powered by the 26 VDC power supply via the OINK (pin 2 J6 and J7).
The Longitudinal controller is located adjacent to the High Voltage Power Supplies on the
Electronics Mounting Chassis. The Transverse controller is located on the metal panel below
the Tube Head near the cable track connection to the Rear Longitudinal Carriage. These motor
controllers are interchangeable.
The motors used are Oriental Motors Vexta Stepping Motors (PH265-05 for Transverse, PH296-
01 for Longitudinal). The Longitudinal Stepper Motor is located on its assembly at the head end
of the scan table, just inside the side door. The Transverse Motor is located on the underside of
the Rear Longitudinal Carriage. The transverse motor is run in parallel operation (for better
speed and torque) at its maximum current rating as listed below. The longitudinal motor is run
in series operation.
Current Settings
The current settings for the Centents are determined by an external resistor which is located on
the OINK. For the Transverse Centent R9, 3.3 MΩ sets the current to 3.5A, and R10 at 82K
ohms sets Longitudinal current to 4.5A.
Belts
Both motors are geared down by a combination of drive belts and pulleys. These belts are
attached to the Rear Longitudinal and Source carriages with belt clamps to provide longitudinal
and transverse motion.
Scan Speeds
The Transverse motor is run at four speeds for the Fast, Medium, Slow and Detail scan modes.
Fast Scan 3072 steps/second (153.6 mm/sec.)

Medium Scan 1536 steps/second (76.8 mm/sec.)
Slow Scan 768 steps/second (38.4 mm/sec.)
Detail 384 steps/second (19.2 mm/sec.)
The motors are pulsed by the SBC at 10 pulses/step.
The firmware on the SBC is told by the software which scan speed has been selected. For the
selected scan speed the firmware has stored in memory a starting speed and ending speed.
The motor is therefore ramped up to its "slewing" (maximum speed, as above) rate. The motor
is also ramped down at the end of a scan line to allow for smooth reversals in direction.
Mechanics 4-43
Cables
There are also Transverse and Longitudinal Drive Cables in the scanner. The Longitudinal
Drive Cable runs around the perimeter of the scan table. It is clamped down on both the Front
and Rear Longitudinal carriages to keep them rigidly connected and in alignment.
The Transverse Drive Cable is clamped down on both the Source and Detector carriages and
keeps them moving together in alignment. This cable is run on pulleys through the arm column
and can be difficult to replace.
Both of these cables are fastened into correct position during installation, and should not need
adjustment.
4-44 Mechanics

Chapter 4 Densitometro Lunar

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LUNAR® DPX-IQ Service Manual Rev.

4.1 The AMP Board .......................................................................................................4-1

Technical Description Chapter 4

Chapter 4 Technical Description

4.1 The AMP Board

4.1.1 Circuit Description

AMP Board 4-1

4-2 AMP Board

Test Point Signal

First Amplifier Output

TP4 Second Amplifier Output

TP5 Third Amplifier Output

TP7 +12 VDC

TP8 -12 VDC

AMP Board 4-3

THIS PAGE LEFT BLANK INTENTIONALLY

4-4 AMP Board

4.2 The Automatic Gain Stabilizer (AGS)

4.2.1 Signal Input

4.2.2 Gain Modification

AGS Board 4-5

4.2.4 Operate/Calibrate (OP/CAL)

4.2.5 Amplification Stage

INPUT VOLTAGE JFET AMPLIFICATION STAGE OUTPUT DIVISION

0.24 X 0.55 X 10 X 0.75 = 1.00

4.2.6 Signal Output

4.2.7 Amplify/Attenuate Indication

4-6 AGS Board

4.2.8 Performance and Operation

4.2.9 AGS Adjustment

DCA TEST POINT MEASUREMENTS IN VOLTS

TP4 1.200 2.020

AGS Board 4-7

4-8 AGS Board

4.2.10 Test Points and LED's

Test Point Signal

TP1 +12 VDC

TP3 -12 VDC

TP4 Signal Input

AGS Board 4-9

THIS PAGE LEFT BLANK INTENTIONALLY

4-10 AGS Board

4.3 The Dual Channel Analyzer (DCA)

4.3.1 Function Description

4.3.2 Circuit Analysis and Operation

Precision Voltage Reference

DCA Board 4-11

Lower Level Discriminator (LLD)

Upper Level Discriminator (ULD)

4.3.3 Technical Facts

4.3.4 Recommended DCA Settings

DPX DCA AGS DCA

TP5 1.970 2.450

TP6 1.675 2.335

TP7 2.800 2.800

4-12 DCA Board

4.3.5 Test Points

Test Point DPX DCA AGS DCA

TP1 Ground Ground