VLSI
VLSI
VLSI
Higher dose of boron implemented into base collector region. This causes contact resistance
&
a) Prevention b) Formation [ ]
a) Polysilicon b) Si c) Cu d) Al [ ]
c) Coupling d) De-coupling
15. The drain current flow in ideally independent of drain –source voltage when the channel
is --------------- [ ]
16. ------------------------- process is used to transfer the layout pattern from masks to wafer. [ ]
17. According to Moore’s law, the number of transistors that could be manufactured on a
chip [ ]
UNIT-2
a) 4 x 4 b) 2 x 2 c) 8 x 8 d) 1 x 1
a) 4 b) 1 c) 2 d) 5
a) 5 to 15 / Sq b) 1 to 3 / Sq c) 1 to 5/Sq d) none [ ]
a) Si3N4 b) Si c) Si N d) Si2O2
15. In CMOS inverter to have equal raise & fall times , Wp is approximately equal to
UNIT-3
7. In CMOS inverter to have equal raise & fall times , Wp is approximately equal to
11. In constant electric field model, power dissipation per unit area is scaled by
a) α
b) β
c) 1
d) β2
12. As the channel length is reduced in a MOS transistor, depletion region width must be
a) increased
b) decreased
c) must not vary
d) exponentially decreased
17. Maximum transit time occurs when the size of the transistor is
a) minimum
b) maximum
c) does not depend on size
d) double
18. The breakdown voltage can be reduced by _____ electric field strength
a) increasing
b) decreasing
c) does not depend
d) exponentially decreasing
UNIT-4
17. The power dissipation in Pseudo-nMOS is reduced to about ____ compared to nMOS
device
20. In clocked CMOS logic, rise time and fall time are
a) faster (b) slower
c) faster first and then slows down (d) slower first and then speeds up
22. CMOS domino logic is same as ______ with inverter at the output line
a) clocked CMOS logic (b) dynamic CMOS logic
c) gate logic (d) switch logic
a)
b)
c)
d)
a) PMOS logic for complement of (AB+C) (b) NMOS logic for complement of (AB+C)
c) PMOS logic for complement of (A+B).C (d) NMOS logic for complement of (A+B).C
b)
c)
d)
b)
c)
d)
38. IR drops brings ______ in noise margin
a) increase (b) decrease (c) does not affect (d) stabilisation
b)
c)
d)
UNIT-5
1. The circuit should be tested at
a) design level (b) chip level (c) transistor level (d) switch level
6. In testability, which terminology is used to represent or indicate the formal evidences of
correctness?
a) Validation (b) Verification (c)Simulation (d) Integration
16.Which among the following operation/s is/are executed in physical design or layout
synthesis stage?
a) Placement of logic functions in optimized circuit in target chip
b) Interconnection of components in the chip
c) Both a and b (d) None of the above
19. Infloorplanning, which phase/s play/s a crucial role in minimizing the ASIC area
and the interconnection density?
a) Placement (b) Global Routing (c) Detailed Routing (d) All of the above
24. Routing technique used in below diagram belongs to which IC technology [L2]
a) Channelled gate array (b)Channel less gate array (c)Structured gate array (d) Channelling
Gate array
a) Channelled gate array (b)Channel less gate array (c)Structured gate array (d) Channelling
Gate array
a) Channelled gate array (b)Channel less gate array (c)Structured gate array (d) Channelling
Gate array
a). OR gates b) NAND gates c). AND gates d). NOR gates