A Novel Compact Complementary Colpitts Differential

CMOS VCO with Low Phase-Noise Performance

Chien-Cheng Wei, Hsien-Chin Chiu, Yi-Tzu Yang, and Wu-Shiung Feng

Department of Electronic Engineering, Chang Gung University, Taoyuan, Taiwan, Republic of China

Abstract — A low phase-noise Ka-band CMOS voltage- capacitors were used to form the resonate tank and
controlled oscillator is proposed in this paper. The CMOS balance the phase and amplitude of two outputs. Besides,
VCO core adopts a new complementary Colpitts structure in
a 0.18-μm CMOS technology to achieve the differential-
this topology requires no additional bias circuit for VCO
ended outputs with low phase-noise performance, as well as core and buffer interfaces. Thus, compared to the other
operate at much higher frequency. The VCO oscillates from topologies oscillated at around 30 GHz, the novel
29.8 to 30 GHz with 200MHz tuning range. The measured complementary Colpitts VCO with differential-ended
phase-noise at 1-MHz offset is -109 dBc/Hz at 30 GHz and outputs achieves larger transconductance, lower phase-
105.5 dBc/Hz at 29.8 GHz. The power consumption of the
VCO core is only 27 mW. To the authors’ knowledge, the
noise, and more relaxed oscillation condition within an
proposed CMOS VCO achieves the best figure of merit uncomplicated structure and small size.
(FOM) of -185 dB at 29.95-GHz band.
II. VCO DESIGN AND IMPLEMENTION
Index Terms — Voltage-controlled oscillators (VCOs), low
phase-noise, complementary Colpitts, differential-ended. The most popular oscillator in modern CMOS
circuits is the LC tank cross-coupled oscillator. In general,
I. INTRODUCTION the complementary structure shows a better performance
than the NMOS-only and PMOS-only structure, as a result
Recently, with advances in radio frequency (RF) of the reduced hot carrier effect, better up/down swing
CMOS technology, CMOS technology has been symmetry, and higher transconductance of the constituting
extensively adopted in wireless communication transistors [3]. However, the Colpitts oscillator is also a
applications because of their low cost and the ability to be well-known topology of the oscillators. Compared to the
integrated with digital circuits. However, owing to the above common cross-coupled oscillators, the Colpitts
increase in the operation frequency in the modern oscillator provides the better performance in phase-noise
communication systems, a high-quality voltage-controlled owing to its highest power-transferred efficiency [7].
oscillator (VCO) in RF transceiver is quite demanded to Therefore, a previous study proposed a new architecture
generate local clocks for mixing the RF and IF signals. of combining the complementary and Colpitts oscillator
Therefore, design and implementation of low phase-noise [4], as depicted in the Fig. 1(a). A common-source
CMOS VCOs is known as a big challenging block due to configuration with one inductor and two capacitors were
the inborn limitations of standard CMOS process introduced to form the Colpitts structure. The PMOS M2
technology. Most of the previously studies describe some stacked on the top of NMOS M1, was employed to replace
high-performance VCOs in cross-coupled topologies [1]– the large-size inductor as a RF choke, as well as increase
[5] by using their proposed techniques. In these the overall transconductance for larger negative-resistance.
techniques, the layout issues such as active and passive
devices design were major discussed to optimize the Vdd Vdd
phase-noise performance. And the reduction in the
parasitics effects was also analyzed to overcome the M2 M2
drawbacks that could be easily appeared in the higher L1 L2
Vg L1 Vd Vg Vd
frequency-bands.
Therefore, in order to provide a high-quality LO C2 C1 CT C2
signal in millimeter wave regions, a new complementary
M1 M1
Colpitts oscillator is introduced in this paper. The novel
topology is simply constructed of two transistors and a
passive LC network. A complementary PMOS and NMOS (a) (b)
transistor pair was employed to generate a larger negative- Fig. 1 (a) Published complementary Colpitts oscillator in [4].
resistance, and a center-tapped inductor with grounded (b) Proposed new complementary Colpitts oscillator topology.
 However, the proposed complementary Colpitts of the proposed complementary Colpitts differential
oscillator in [4] only operates for single-ended output, CMOS VCO. The grounded capacitors C1 and C2 were
which cannot be applied in differential-ended systems replaced by the accumulation-mode varactors as the
owing to the unbalance output power and phase between control component for fine-tuning the oscillation
Vd and Vg. Therefore, a novel LC network is introduced in frequency. Besides, in order to drive the 50-Ω load of test
the complementary Colpitts oscillator core to generate a instrument, the open-source buffers and the external bias-
180° out of phase between gate and drain terminals of M1 tees were employed.
and M2, as shown in Fig. 1(b). The proposed LC network
is composed of two series inductors L1 and L2 with three
grounded capacitors C1, C2, and CT. The grounded
capacitor CT is an important key parameter to adjust the
phase and amplitudes between two output ports. From the
small-signal analysis, the transfer function between gate
terminal (Vg) and drain terminal (Vd) in Fig. 1(b) can be
expressed as

Vd = −V g (1 − ω 2 L1C1 + ω 2 L2 C1
(1)
+ ω 2 CT L2 − ω 4 L1 L2 C1CT )
Fig. 2 Simulated results of output waveform for gate and drain
And after deriving the close-loop of the proposed circuit,
terminals in the proposed VCO.
the oscillation frequency can be approximated by

C1 + CT + C2
ω0 ≈ 4 (2) 0.40 184

L1 L2C1C2CT
0.39

Phase Difference (degree)

Power Difference (dB)

182
Assuming that the two inductance L1 and L2 in (1) are 0.38
identical owing to the use of center-tapped inductor in this
design, the two terms of ω 2 L1C1 and ω 2 L2C1 in (1) can 0.37 180
be neglected at first. And then substituting the oscillation
0.36
frequency ω 0 of (2) into (1), the relationship between two 178
outputs can be found that Vg ≈–Vd, which means the 0.35
amplitudes of two outputs are approximately the same
with a phase difference of 180°. Fig. 2 displays the 0.34
0.100 0.102 0.104 0.106 0.108 0.110
176
0.112
simulated results of output waveforms at gate and drain CT value (pF)
terminals, respectively. And the simulated results of CT
value versus the difference of output power and phase is Fig. 3 Simulated results of CT value versus the difference of
shown in Fig. 3. These results show that the proposed LC output power and phase between two outputs.
network can optimize the output waveforms after
carefully choosing the value of CT.
Thus, by adopting the low-parasitic and high- Vdd Vdd Vdd
transconductance topology, there exists more potential in M2
the design of a low-noise oscillator in high frequency with
low power. Traditionally, the Colpitts oscillator is a
Vo+ Bias-Tee Bias-Tee
Vo-
simple oscillator core, which has been the most favored L1 L2
topology for low phase-noise [6-8]. However, since the M3 M4
conventional Colpitts oscillator needs additional circuits C1 CT C2
for bias and buffer interfaces, its oscillation performances
may be degraded by the parasitics in high frequency. In Vctrl Vctrl
this work, the novel complementary Colpitts adopts the M1
self-bias technique for VCO core and buffer interface,
which provides better oscillation performance compared Fig. 4. Circuit schematic of the proposed complementary
to other topologies. Fig. 4 plots the fully circuit schematic Colpitts differential CMOS VCO.
 III. MEASUREMENT RESULTS can be further suppressed by the loop filter of the
frequency synthesizer. Table I compares the Ka-band
By using a 0.18-μm CMOS 1P6M standard process
VCOs released over the past few years. It shows that the
from Taiwan Semiconductor Manufacturing Company,
phase-noise of this novel VCO is the lowest of any circuit
Ltd. (TSMC), a 30 GHz new complementary Colpitts
operated near 30 GHz. The figure-of-merit (FOM) is also
VCO with differential outputs was implemented for
the best record of –185dBc/Hz compared to other
demonstration. To characterize the circuit performance of
applications.
the proposed VCO, the on-wafer measurement was
utilized in this work. Fig. 5 shows the microphotograph of
the fabricated circuit, a symmetrical layout is used for
VCO design to ensure the fully differential operation. The
total chip area including the dc and rf pads is 0.6 × 0.4
mm2, where the active area occupy only around 0.45 × 0.3
mm2. The designed VCO including two output buffers
operates at a supply voltage of 1.8 V with total power
consumption of 27 mW. Fig. 6 plots the oscillation
frequencies were from 29.8 to 30 GHz under controlled
voltages from –0.6 to 1.5 V. This figure also shows the
measured output spectrum at controlled voltages of 0.5 V,
which demonstrates that the proposed VCO structure can
easily work at millimeter wave frequency band owing to Fig. 5 Microphotograph of the fabricated VCO.
its lower parasitic. Fig. 7 and 8 plots the measured output
power and its related close-in phase-noise by using the
31.0
Agilent E4407B spectrum analyzer and E5052A signal
source analyzer, respectively. And all losses from the 30.5
adaptors, cables, and bias-tees in the measurement setup
Frequency (GHz)

were calibrated and deembedded in the experimental 30.0

results. As shown in Fig.7, the measured output power of
the differential ports, gate port and drain port, were both 29.5
higher than –7 dBm and have a similar power level. It is
29.0 Simulation
because the new complementary Colpitts VCO adopted a Measurement
proposed LC network to balance the output power 28.5
between the two ports. The measured phase-noise, as
shown in Fig. 8, was 110 dBc/Hz at 1 MHz offset at 28.0
-0.5 0.0 0.5 1.0 1.5
oscillated frequency of 29.95 GHz. The above
measurement of free-running phase-noise shows that the Controlled-Voltage (V)
Ka-band CMOS VCO is sufficient for wireless
communication applications. However, by utilizing the Fig. 6 Performance of the oscillation frequency and the
VCO in a 30 GHz frequency synthesizer, the phase-noise measured output spectrum for the proposed VCO.

TABLE I
PERFORMANCE SUMMARY OF THE 30GHZ VCOS
Ref. Year Process PDC f0 Phase noise FOM
0.12μm -99dBc/Hz
[19]
[9] 2004
HBT
3.7mW 33GHz -183dBc/Hz
1MHz offset
0.15μm -102dBc/Hz
[10]
[20] 2003
pHEMT
80mW 28.3GHz -172dBc/Hz
1MHz offset
0.35μm -102dBc/Hz
[11]
[21] 2006
CMOS
117mW 30.9GHz -171dBc/Hz
1MHz offset
This 0.18μm -110dBc/Hz
2007 27mW 29.9GHz -185dBc/Hz
work CMOS 1MHz offset
 ACKNOWLEDGEMENT
0 The authors would like to acknowledge fabrication
support provided by Taiwan Semiconductor
-2 Manufacturing Company (TSMC) through the National
Output power (dBm)

Chip Implementation Center (CIC).

-4

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