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 WEED Workshop on Energy-Efficient Design held in conjunction with ISCA 36 pp. 44-49

Near Threshold Computing: Overcoming Performance Degradation

from Aggressive Voltage Scaling
Ronald G. Dreslinski, Michael Wieckowski, David Blaauw, Dennis Sylvester, and Trevor Mudge
Department of Electrical Engineering and Computer Science
University of Michigan - Ann Arbor, MI

Abstract When we examine history, we readily see a pattern:

generations of previous technologies, ranging from
Power has become the primary design constraint for vacuum tubes to bipolar to NMOS-based
chip designers today. While Moore’s law continues to technologies, were replaced by their successors
provide additional transistors, power budgets are when their energy overheads were prohibitive.
beginning to prohibit those devices from actually However, there is no clear successor to CMOS today.
being turned on. To reduce energy consumption, The available alternatives are far from being
voltage scaling techniques have proved a popular commercially viable, and none has gained sufficient
technique with subthreshold design representing the traction, or provided the economic justification for
endpoint of voltage scaling. However, while overthrowing the large investments made in CMOS-
extremely energy efficient, subthreshold design has based infrastructure. Therefore, there is a strong
been relegated to niche markets due to its major case supporting the position that solutions to the
performance penalties. In this paper we explore Near power conundrum must come from enhanced
Threshold Computing (NTC), a design space where devices, design styles and architectures, rather than
the supply voltage is approximately set to the a reliance on the promise of radically new
threshold voltage of the transistors. This region technologies becoming commercially viable. In our
retains much of the energy savings of subthreshold view, the solution to this energy crisis is the universal
operation with more favorable performance and application of aggressive low voltage operation
variability characteristics. This makes it applicable to across all computation platforms. This can be
a broad range of power-constrained computing accomplished by targeting so-called “near-threshold
segments from sensors to high performance servers. operation” and by proposing novel methods to
In this paper we briefly discuss several barriers to the overcome the barriers that have historically relegated
wide spread adoption of near threshold computing ultra-low voltage operation to niche markets.
and focus, in detail, on techniques to overcome the
performance barrier of aggressive voltage scaling. CMOS-based technologies have continued to march
in the direction of miniaturization as per Moore's law.
1. Intro: New silicon-based technologies such as FinFET
devices [2] and 3D integration [3] provide a path to
Over the past four decades, the number of transistors increasing transistor counts in a given footprint.
on a chip has increased exponentially in accordance However, using Moore's law as the metric of progress
with Moore's law [1]. This has lead to progress in has become misleading since improvements in
diversified computing applications, such as health packing densities no longer translate into
care, education, security and communications. A proportionate increases in performance or energy
number of societal projections and industrial efficiency. Starting around the 65nm node, device
roadmaps are driven by the expectation that these scaling no longer delivers the energy gains that drove
rates of improvement will continue, but the the semiconductor growth of the past several
impediments to growth are more formidable today decades, as shown in Figure 1. The supply voltage
than ever before. The largest of these barriers is has remained essentially constant since then and
related to energy and power dissipation, and it is not dynamic energy efficiency improvements have
an exaggeration to state that developing energy- stagnated, while leakage currents continue to
efficient solutions is critical to the survival of the increase. Heat removal limits at the package level
semiconductor industry. Extensions of today's have further restricted more advanced integration.
solutions can only go so far, and without Together, such factors have created a curious design
improvements in energy efficiency, CMOS is in dilemma: more gates can now fit on a die, but a
danger of running out of steam. larger portion cannot actually be used due to strict
power limits.

 
 WEED Workshop on Energy-Efficient Design held in conjunction with ISCA 36 pp. 44-49

shift where ultra-low voltage operation is applied

At the same time, we are moving to a “more than ubiquitously across application platforms and forms
Moore" world, with a wider diversity of applications the basis for renewed energy efficiency.
than the microprocessor or ASICs of ten years ago.
Tomorrow's design paradigm must enable designs However, NTC does not come without some barriers
catering to application spanning from high- to widespread acceptance. Three of the key
performance processors and portable wireless challenges that have been poorly addressed to date
applications, to sensor nodes and medical implants. are: 1) 10X or greater loss in performance; 2) 5X
Energy considerations are vital over this entire increase in performance variation, and 3) 5 orders of
spectrum, including high-performance platforms, magnitude increase in functional failure of memory as
personal computing platforms, and sensor based well as increased logic failures. Overcoming these
platforms. barriers is a formidable challenge requiring a
synergistic approach combining methods from the
1.0 algorithm and architecture levels to circuit and
Norm. Total Energy

technology levels. In this paper we will focus on the

stagnant
Vdd scaling 2 first barrier, performance degradation.
2.7X
Vdd [V]

0.5 2. Near Threshold Computing (NTC):

1
Energy consumption in modern CMOS circuits largely
2.6X
1.7X results from the charging and discharging of internal
1.7X 1.3X 1.1X
1.8X
0
node capacitances and can be reduced quadratically
0.0
250 180 130 90 32 22
by lowering supply voltage (Vdd). As such, voltage
65 45
Technology node [nm] scaling has become one of the more effective
methods to reduce power consumption in commercial
Figure 1: Technology scaling trends of supply voltage parts. It is well known that CMOS circuits function at
and energy. low voltages and remain functional even when Vdd
drops below the threshold voltage (Vth). In 1972,
The aim of the designer in this era is to overcome the Meindl et al derived a theoretical lower limit on Vdd for
challenge of energy efficient computing and unleash functional operation, which has been approached in
performance from the reins of power to recapture very simple test circuits [4,5]. Since this time, there
Moore’s law in the semiconductor industry. The has been interest in subthreshold operation, initially
strategy is to provide 10X or higher energy efficiency for analog circuits [6,7,8] and more recently for digital
improvements at constant performance through processors [9,10,11,12,13,14], demonstrating
widespread application of near-threshold computing operation at Vdd below 200mV. However, the lower
(NTC), where devices are operated at or near their bound on Vdd in commercial applications is usually
threshold voltage (Vth). By reducing supply voltage reduced to no lower than ~70% of the nominal Vdd
from nominal 1.1V to 400-500mV, NTC obtains as due to concerns about performance loss and
much as 10X energy efficiency gains and represents robustness [15,16].
the re-establishment of voltage scaling and its
associated energy efficiency gains. Given such wide voltage scaling potential, it is
important to determine the Vdd at which the energy
The use of ultra-low voltage operation, and in per instruction is optimal. In the superthreshold
particular subthreshold operation (Vdd <Vth), was first regime (Vdd >Vth), energy is highly sensitive to Vdd due
proposed over three decades ago when the to the quadratic scaling of switching energy with Vdd.
theoretical lower limit of Vdd was found to be 36mV[4]. Hence voltage scaling down to the near-threshold
However, the challenges that arise from operating in regime (Vdd ~ Vth) yields an energy reduction on the
this regime have kept subthreshold operation order of 10X at the expense of approximately 10X
confined to a handful of niche markets, such as performance degradation, as seen in Figure 2.
wristwatches and hearing aids. To the mainstream However, the dependence of energy on Vdd becomes
designer, ultra-low voltage design has remained little more complex as voltage is scaled below Vth. In
more than a fascinating concept with no practical subthreshold (Vdd <Vth), circuit delay increases
relevance. However, given the current energy crisis in exponentially with Vdd causing leakage energy (the
the semiconductor industry and stagnated voltage product of leakage current, Vdd, and delay) to
scaling we foresee the need for a radical paradigm
 

 
 WEED Workshop on Energy-Efficient Design held in conjunction with ISCA 36 pp. 44-49

increase in a near-exponential fashion. This rise in of voltages. As was discussed in Section 2, there is a
leakage energy eventually dominates any reduction Vmin operating point that occurs in the subthreshold
in switching energy, creating an energy minimum operating region but is tied to operating points of less
seen in Figure 2. than 1MHz. On the other hand, only a modest
increase in energy is seen operating at the NTC
region (around .5V), while frequency characteristics
at that point are significantly better. At nominal
operating points Subliminal operates at 20.5 MHz and
33.1 pJ/inst, showing approximately a 6.6x reduction
in energy and an 11.4x reduction in frequency at the
NTC operating point.
 
4. NTC Barriers:
Although NTC provides for excellent energy-
frequency tradeoffs, it doesn’t come without its own
set of complications. NTC faces three key barriers
that must be overcome for widespread use,
performance loss, performance variation, and even
functional failure. In the following subsections we will
discuss why each of these exist and why they pose
problems to the wide spread adoption of NTC.

9 E n erg y
F re q u e n cy
1000
8
Energy/Inst (pJ)

Frequency (kHz)
Figure 2: Energy and delay in different supply voltage
7
operating regions.
6
V dd =350m V , 100
The identification of an energy minimum has led to 5 3.52p J/in st, 354kH z

interest in processors that operate at this energy

4
optimal supply voltage [12,14,17] (referred to as Vmin
and typically 250mV-350mV). However, the energy 3 10
0.20 0.25 0.30 0.35 0.40 0.45 0.50
minimum is relatively shallow. Energy typically V d d (V )
reduces by only ~2X when Vdd is scaled from the
Figure 3: Subliminal processor frequency and energy
near-threshold regime (400-500mV) to the
breakdowns at various supply voltages.
subthreshold regime, though delay rises by 50-100X
over the same region. While acceptable in ultra-low
energy sensor-based systems, this delay penalty is
4.1. Performance loss. The performance loss
not tolerable in a broad set of applications. Hence,
observed in NTC, while not as severe as that in
although introduced roughly 30 years ago, ultra-low
subthreshold operation, poses one of the most
voltage design remains confined to a small set of
formidable challenges for NTC viability. In an
markets with little or no impact on mainstream
industrial 45nm technology the fanout-of-four inverter
semiconductor products.
(FO4) delay at 400mV is 10X slower than at the
nominal 1.1V. There have been several recent
3. NTC Analysis: advances of architectural and circuit techniques that
Recent work at many leading institutions has can be used to improve performance in the NTC
produced working processors that operate at regime. These techniques, described in detail in
subthreshold voltages. For instance, the Subliminal Section 5.1, center around aggressive parallelism
processor [17] designed by Hanson et al. provides with a novel NTC oriented memory/computation
the opportunity to clearly quantify the NTC region and hierarchy. The increased communication needs in
how it compares to the subthreshold region. Figure 3 these architectures is supported by the application of
presents the energy breakdown of the design as well 3D chip integration, as made feasible by the low
as the operating frequency achieved across a range power density of NTC circuits. In addition a new

 
 WEED Workshop on Energy-Efficient Design held in conjunction with ISCA 36 pp. 44-49

technology optimization that opportunistically also circuit functionality. In particular the mismatch in
leverages the significantly improved silicon wearout device strength due to process variations such as
characteristics (e.g., oxide breakdown) observed in random dopant fluctuations (RDF) can compromise
low voltage NTC can be used to regain a substantial state elements as the feedback loop develops a
portion of the lost performance. natural inclination for one state over the other. This
issue has been most pronounced in SRAM where
Sub Vt high yield requirements and the use of minimum
5x
sized devices limit variability tolerance. For instance,
Delay a typical 45nm SRAM cell has a failure probability of
Variation -7
~10 at nominal voltage, see Figure 5. This low failure
rate allows failing cells to be readily swapped using
spare columns after fabrication. However, at an NTC
voltage of 500mV, this failure rate increases by ~5
orders of magnitude to approximately 4% (4x10-2). In
NTC
this case, nearly every row and column will have at
least one failing cell, and possibly multiple failures,
rendering simple redundancy methods completely
Super Vt ineffective. There are many alternative SRAM
approaches to help address this variability [21,22,23],
new failure rate estimation techniques [24], and
  alternative cache designs [25]. All these techniques
are used to help overcome these failures.
Figure 4: Impact of voltage scaling on gate delay
variation.
4.2. Increased performance variation. In the near- NTC
threshold regime, the dependencies of MOSFET
drive current on Vth, Vdd, and temperature approach
exponential. As a result, NTC designs display a
dramatic increase in performance uncertainty. Figure
4 shows that performance variation due to process
variation alone increases by approximately 5X from
~30% (1.3X) [18] at nominal operating voltage to as 105
much as 150%, (2.5X) at 400mV. When combined
with approximately 2X performance variation due to
supply voltage ripple and 2X variation due to
temperature, a total performance uncertainty of 10X
emerges. Given a total performance uncertainty of  
~1.5X at nominal voltage, the increased performance Figure 5: Impact of voltage scaling on SRAM failure rates.
uncertainty of NTC circuits looms as a daunting
challenge that has caused most designers to pass
over low voltage design entirely. Simply adding 5. Addressing Performance Loss:
margin so that all chips will meet the needed
performance specification in the worst-case is One of the most formidable challenges to widespread
effective in nominal voltage design. However, in NTC NTC penetration is overcoming the ~10x performance
design this approach results in some chips running at loss associated with NTC operation while maintaining
1/10th their potential performance, which is wasteful energy efficiency. Below, we explore architectural
both in performance and energy due to leakage and device level methods that form a complementary
currents. Several techniques exist to help mitigate approach to address this challenge.
these problems including Adaptive Body Biasing [19],
soft edge clocking [20]. 5.1 Cluster Based Architecture
In order to regain the performance lost in NTC
4.3. Increased functional failure. The increased without increasing supply voltage, Zhai et. al [26,27]
sensitivity to process, temperature and voltage propose the use of NTC based parallelism. In
variations not only impacts circuit performance but applications where there is an abundance of thread-

 
 WEED Workshop on Energy-Efficient Design held in conjunction with ISCA 36 pp. 44-49

level parallelism the intention is to use 10s to 100s of situation can be common in high performance
NTC processor cores that will regain 10-50X the applications where threads work on independent
performance, while remaining energy efficient. While data. However, these workloads often execute the
traditional superthreshold many-core solutions have same instruction sequences, allowing opportunity for
been studied, the NTC domain presents unique savings with a clustered instruction cache. Initial
challenges and opportunities in these architectures. research of this architecture shows that with a few
Of particular impact are the reliability of NTC memory processors (6-12), a gain of 5-6X performance
cells and differing energy optimal voltage points for improvement can be achieved.

5.2 Device Optimization

At the lowest level of abstraction, performance of
NTC systems can be greatly improved through
straightforward modifications and optimizations of the
transistor structure and its fabrication process. This
follows directly from the fact that commercially
available CMOS processes are universally tailored to
sustaining the super-threshold trends forecasted by
Moore’s law. In most cases, this results in a
transistor that is decidedly sub-optimal for low voltage
operation. Recently, this has generated substantial
interest in the academic community because of the
Figure 4:Cluster-based architecture.
potential performance gains that could be gleaned by
developing a process flow tailored for sub-threshold
logic and memory, as discussed below. operation. In large part, these gains would be
Zhai’s work showed that SRAMs, commonly used for comparable for NTC operation since the devices in
caches, have a higher energy optimal operating question still operate without a strongly inverted
voltage (Vmin) than processors, by approximately channel. For example, Paul, Raychowdhury, and
100mV [26]. This results from the lower activity in Roy [28] demonstrate that a 44% improvement in
caches, which amplifies leakage effects. As sub-threshold delay can be realized through simple
discussed, SRAM designs also face reliability issues modifications of the channel doping profile of a
in the NTC regime, leading to a need for larger SRAM standard super-threshold device. Essentially, the
cells or error correction methods (see Section 5.3), nominal device is doped with an emphasis on
further increasing leakage and the energy optimal reducing short channel effects at standard supply
operating voltage. Due to this higher Vmin, SRAMs voltage such as DIBL, punch-through, and Vth roll-off.
remain energy efficient at higher supply voltages, and These effects are much less significant when the
thus at higher speeds, compared to logic. Hence, supply is lowered below about 70% of the nominal.
there is the unique opportunity in the NTC regime to This allows one to instead focus their efforts on a
run caches faster than processors for energy doping profile that minimizes junction capacitance
efficiency, which naturally leads to architectures and sub-threshold swing without negatively impacting
where multiple processors share the same first level the device off current.
cache.
Similarly, Hanson et al. [29] showed that the slow
It follows to suggest an architecture with n clusters scaling of gate oxide relative to the channel length
and k cores, where each cluster shares a first level has lead to a 60% reduction in Ion/Ioff between the
cache that runs k times faster than the cores (Figure 90nm and 32nm nodes. This on to off ratio is a critical
6). Different voltage regions are presented in different measure of stability and noise immunity, and such a
colors and use level converters at the interfaces. This reduction results in SNM degradation of more than
architecture results in several interesting tradeoffs. 10% between the 90nm and 32nm nodes in a CMOS
First, applications that share data and communicate inverter. As a solution, they have proposed a
through memory, such as certain classes of scientific modified scaling strategy that uses increased channel
computing, can avoid coherence messages to other lengths and reduced doping to improve sub-threshold
cores in the same cluster. This reduces energy from swing. They developed new delay and energy metrics
memory coherence. However, the cores in a cluster that effectively capture the important effects of device
compete for cache space and incur more conflict scaling, and used those to drive device optimization.
misses, which may in turn increase energy use. This They found that noise margins improved by 19% and
 

 
 WEED Workshop on Energy-Efficient Design held in conjunction with ISCA 36 pp. 44-49

energy improved by 23% in 32nm subthreshold                                                                                                   

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