r5f2021 Micro Controlador

R8C/26 Group, R8C/27 Group
REJ03B0168-0210
SINGLE-CHIP 16-BIT CMOS MCU Rev.2.10
Sep 26, 2008
1. Overview
These MCUs are fabricated using a high-performance silicon gate CMOS process, embedding the R8C CPU core, and
are packaged in a 32-pin molded-plastic LQFP. It implements sophisticated instructions for a high level of instruction
efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed.
Furthermore, the R8C/27 Group has on-chip data flash (1 KB × 2 blocks).
The difference between the R8C/26 Group and R8C/27 Group is only the presence or absence of data flash.
Their peripheral functions are the same.
1.1 Applications
Electronic household appliances, office equipment, audio equipment, consumer products, automotive, etc.
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R8C/26 Group, R8C/27 Group 1. Overview
1.2 Performance Overview

Table 1.1 outlines the Functions and Specifications for R8C/26 Group and Table 1.2 outlines the Functions and
Specifications for R8C/27 Group.
Table 1.1 Functions and Specifications for R8C/26 Group

Item Specification
CPU Number of 89 instructions
fundamental
instructions
Minimum instruction 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) (other than K version)
execution time 62.5 ns (f(XIN) = 16 MHz, VCC = 3.0 to 5.5 V) (K version)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V) (N, D version)
Operating mode Single-chip
Address space 1 Mbyte
Memory capacity Refer to Table 1.3 Product Information for R8C/26 Group
Peripheral Ports I/O ports: 25 pins, Input port: 3 pins
Functions LED drive ports I/O ports: 8 pins (N, D version)
Timers Timer RA: 8 bits × 1 channel
Timer RB: 8 bits × 1 channel
(Each timer equipped with 8-bit prescaler)
Timer RC: 16 bits × 1 channel
(Input capture and output compare circuits)
Timer RE: With real-time clock and compare match function
(For J, K version, compare match function only.)
Serial interfaces 2 channels (UART0, UART1)
Clock synchronous serial I/O, UART
Clock synchronous 1 channel
serial interface I2C bus Interface(1)
Clock synchronous serial I/O with chip select
LIN module Hardware LIN: 1 channel (timer RA, UART0)
A/D converter 10-bit A/D converter: 1 circuit, 12 channels
Watchdog timer 15 bits × 1 channel (with prescaler)
Start-on-reset selectable
Interrupts Internal: 15 sources, External: 4 sources,
Software: 4 sources, Priority levels: 7 levels
Clock generation 3 circuits
circuits • XIN clock generation circuit (with on-chip feedback resistor)
• On-chip oscillator (high speed, low speed)
High-speed on-chip oscillator has a frequency adjustment function
• XCIN clock generation circuit (32 kHz) (N, D version)
• Real-time clock (timer RE) (N, D version)
Oscillation-stopped XIN clock oscillation stop detection function
detector
Voltage detection On-chip
circuit
Power-on reset circuit On-chip
Electrical Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz) (other than K version)
Characteristics VCC = 3.0 to 5.5 V (f(XIN) = 16 MHz) (K version)
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)
VCC = 2.2 to 5.5 V (f(XIN) = 5 MHz) (N, D version)
Current consumption Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
(N, D version) Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
Typ. 2.0 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz)
Typ. 0.7 µA (VCC = 3.0 V, stop mode)
Flash Memory Programming and VCC = 2.7 to 5.5 V
erasure voltage
Programming and 100 times
erasure endurance
Operating Ambient Temperature -20 to 85°C (N version)
-40 to 85°C (D, J version)(2), -40 to 125°C (K version)(2)
Package 32-pin molded-plastic LQFP
NOTES:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. Specify the D, K version if D, K version functions are to be used.
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Table 1.2 Functions and Specifications for R8C/27 Group

Item Specification
CPU Number of fundamental 89 instructions
instructions
Minimum instruction 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) (other than K version)
execution time 62.5 ns (f(XIN) = 16 MHz, VCC = 3.0 to 5.5 V) (K version)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V) (N, D version)
Operating mode Single-chip
Address space 1 Mbyte
Memory capacity Refer to Table 1.4 Product Information of R8C/27 Group
Peripheral Ports I/O ports: 25 pins, Input port: 3 pins
Functions LED drive ports I/O ports: 8 pins (N, D version)
Timers Timer RA: 8 bits × 1 channel
Timer RB: 8 bits × 1 channel
(Each timer equipped with 8-bit prescaler)
Timer RC: 16 bits × 1 channel
(Input capture and output compare circuits)
Timer RE: With real-time clock and compare match function
(For J, K version, compare match function only.)
Serial interfaces 2 channels (UART0, UART1)
Clock synchronous serial I/O, UART
Clock synchronous 1 channel
serial interface I2C bus Interface(1)
Clock synchronous serial I/O with chip select
LIN module Hardware LIN: 1 channel (timer RA, UART0)
A/D converter 10-bit A/D converter: 1 circuit, 12 channels
Watchdog timer 15 bits × 1 channel (with prescaler)
Start-on-reset selectable
Interrupts Internal: 15 sources, External: 4 sources,
Software: 4 sources, Priority levels: 7 levels
Clock generation 3 circuits
circuits • XIN clock generation circuit (with on-chip feedback resistor)
• On-chip oscillator (high speed, low speed)
High-speed on-chip oscillator has a frequency adjustment function
• XCIN clock generation circuit (32 kHz) (N, D version)
• Real-time clock (timer RE) (N, D version)
Oscillation-stopped XIN clock oscillation stop detection function
detector
Voltage detection circuit On-chip
Power-on reset circuit On-chip
Electrical Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz) (other than K version)
Characteristics VCC = 3.0 to 5.5 V (f(XIN) = 16 MHz) (K version)
VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)
VCC = 2.2 to 5.5 V (f(XIN) = 5 MHz) (N, D version)
Current consumption Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
(N, D version) Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
Typ. 2.0 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz)
Typ. 0.7 µA (VCC = 3.0 V, stop mode)
Flash Memory Programming and VCC = 2.7 to 5.5 V
erasure voltage
Programming and 10,000 times (data flash)
erasure endurance 1,000 times (program ROM)
Operating Ambient Temperature -20 to 85°C (N version)
-40 to 85°C (D, J version)(2), -40 to 125°C (K version)(2)
Package 32-pin molded-plastic LQFP
NOTES:
1. I2C bus is a trademark of Koninklijke Philips Electronics N. V.
2. Specify the D, K version if D, K version functions are to be used.
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1.3 Block Diagram

Figure 1.1 shows a Block Diagram.
8 8 6 1 3 2
I/O ports Port P0 Port P1 Port P3 Port P4 Port P5
Peripheral functions
A/D converter System clock
(10 bits × 12 channels)
generation circuit
Timers
XIN-XOUT
Timer RA (8 bits) High-speed on-chip oscillator
Timer RB (8 bits) UART or Low-Speed on-chip oscillator
Timer RC clock synchronous serial I/O XCIN-XCOUT(3)
(16 bits × 1 channel) (8 bits × 2 channels)
Timer RE (8 bits)
I2C bus interface or clock synchronous

serial I/O with chip select
(8 bits × 1 channel)
LIN module
(1 channel)
Watchdog timer R8C CPU core Memory

(15 bits)
R0H R0L SB ROM(1)
R1H R1L
USP
R2
R3 ISP
INTB RAM(2)
A0
PC
A1
FB FLG
Multiplier
NOTES:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
3. XCIN, XCOUT can be used only for N or D version.
Figure 1.1 Block Diagram
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1.4 Product Information

Table 1.3 lists the Product Information for R8C/26 Group and Table 1.4 lists the Product Information for R8C/27
Group.
Table 1.3 Product Information for R8C/26 Group Current of Sep. 2008
ROM RAM
Part No. Package Type Remarks
Capacity Capacity
R5F21262SNFP 8 Kbytes 512 bytes PLQP0032GB-A N version
R5F21264SNFP 16 Kbytes 1 Kbyte PLQP0032GB-A
R5F21265SNFP 24 Kbytes 1.5 Kbytes PLQP0032GB-A
R5F21266SNFP 32 Kbytes 1.5 Kbytes PLQP0032GB-A
R5F21262SDFP 8 Kbytes 512 bytes PLQP0032GB-A D version
R5F21264SDFP 16 Kbytes 1 Kbyte PLQP0032GB-A
R5F21265SDFP 24 Kbytes 1.5 Kbytes PLQP0032GB-A
R5F21266SDFP 32 Kbytes 1.5 Kbytes PLQP0032GB-A
R5F21264JFP 16 Kbytes 1 Kbyte PLQP0032GB-A J version
R5F21266JFP 32 Kbytes 1.5 Kbytes PLQP0032GB-A
R5F21264KFP 16 Kbytes 1 Kbyte PLQP0032GB-A K version
R5F21266KFP 32 Kbytes 1.5 Kbytes PLQP0032GB-A
R5F21262SNXXXFP 8 Kbytes 512 bytes PLQP0032GB-A N version Factory
R5F21264SNXXXFP 16 Kbytes 1 Kbyte PLQP0032GB-A programming
R5F21265SNXXXFP 24 Kbytes 1.5 Kbytes PLQP0032GB-A product(1)
R5F21266SNXXXFP 32 Kbytes 1.5 Kbytes PLQP0032GB-A
R5F21262SDXXXFP 8 Kbytes 512 bytes PLQP0032GB-A D version
R5F21264SDXXXFP 16 Kbytes 1 Kbyte PLQP0032GB-A
R5F21265SDXXXFP 24 Kbytes 1.5 Kbytes PLQP0032GB-A
R5F21266SDXXXFP 32 Kbytes 1.5 Kbytes PLQP0032GB-A
R5F21264JXXXFP 16 Kbytes 1 Kbyte PLQP0032GB-A J version
R5F21266JXXXFP 32 Kbytes 1.5 Kbytes PLQP0032GB-A
R5F21264KXXXFP 16 Kbytes 1 Kbyte PLQP0032GB-A K version
R5F21266KXXXFP 32 Kbytes 1.5 Kbytes PLQP0032GB-A
NOTE:
1. The user ROM is programmed before shipment.
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Part No. R 5 F 21 26 6 S N XXX FP

Package type:
FP: PLQP0032GB-A
ROM number
Classification
N: Operating ambient temperature -20 to 85°C (N version)
D: Operating ambient temperature -40 to 85°C (D version)
J: Operating ambient temperature -40 to 85°C (J version)
K: Operating ambient temperature -40 to 125°C (K version)
S: Low-voltage version (other no symbols)
ROM capacity
2: 8 KB
4: 16 KB
5: 24 KB
6: 32 KB
R8C/26 Group
R8C/2x Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.2 Part Number, Memory Size, and Package of R8C/26 Group
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Table 1.4 Product Information for R8C/27 Group Current of Sep. 2008
ROM Capacity
RAM
Part No. Program Package Type Remarks
Data flash Capacity
ROM
R5F21272SNFP 8 Kbytes 1 Kbyte × 2 512 bytes PLQP0032GB-A N version
R5F21274SNFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A
R5F21275SNFP 24 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A
R5F21276SNFP 32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A
R5F21272SDFP 8 Kbytes 1 Kbyte × 2 512 bytes PLQP0032GB-A D version
R5F21274SDFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A
R5F21275SDFP 24 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A
R5F21276SDFP 32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A
R5F21274JFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A J version
R5F21276JFP 32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A
R5F21274KFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A K version
R5F21276KFP 32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A
R5F21272SNXXXFP 8 Kbytes 1 Kbyte × 2 512 bytes PLQP0032GB-A N version Factory
R5F21274SNXXXFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A programming
R5F21275SNXXXFP 24 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A product(1)
R5F21276SNXXXFP 32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A
R5F21272SDXXXFP 8 Kbytes 1 Kbyte × 2 512 bytes PLQP0032GB-A D version
R5F21274SDXXXFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A
R5F21275SDXXXFP 24 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A
R5F21276SDXXXFP 32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A
R5F21274JXXXFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A J version
R5F21276JXXXFP 32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A
R5F21274KXXXFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0032GB-A K version
R5F21276KXXXFP 32 Kbytes 1 Kbyte × 2 1.5 Kbytes PLQP0032GB-A
NOTE:
1. The user ROM is programmed before shipment.
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Part No. R 5 F 21 27 6 S N XXX FP

Package type:
FP: PLQP0032GB-A
ROM number
Classification
N: Operating ambient temperature -20 to 85°C (N version)
D: Operating ambient temperature -40 to 85°C (D version)
J: Operating ambient temperature -40 to 85°C (J version)
K: Operating ambient temperature -40 to 125°C (K version)
S: Low-voltage version (other no symbols)
ROM capacity
2: 8 KB
4: 16 KB
5: 24 KB
6: 32 KB
R8C/27 Group
R8C/2x Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.3 Part Number, Memory Size, and Package of R8C/27 Group
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1.5 Pin Assignments

Figure 1.4 shows Pin Assignments (Top View).
P1_1/KI1/AN9/TRCIOA/TRCTRG
P3_4/SDA/SCS/(TRCIOC)(2)
P1_2/KI2/AN10/TRCIOB
P3_3/INT3/SSI/TRCCLK
P1_3/KI3/AN11/(TRBO)
P1_0/KI0/AN8
VREF/P4_2
P1_4/TXD0
24 23 22 21 20 19 18 17
P0_7/AN0 25 16 P1_5/RXD0/(TRAIO)/(INT1)(2)
P0_6/AN1 26 15 P1_6/CLK0/(SSI)(2)
P0_5/AN2/CLK1 27 14 P5_3/TRCIOC
R8C/26 Group P5_4/TRCIOD
P0_4/AN3/TREO 28 13
P0_3/AN4 29
R8C/27 Group 12 P3_1/TRBO
P0_2/AN5 30 11 P3_6/(TXD1)/(RXD1)/(INT1)(2)
PLQP0032GB-A
P0_1/AN6 31 (32P6U-A) 10 P1_7/TRAIO/INT1
P0_0/AN7/(TXD1)(2) 32 (top view) 9 P4_5/INT0/(RXD1)(2)
1 2 3 4 5 6 7 8
MODE
P3_5/SCL/SSCK/(TRCIOD)(2)
P3_7/TRAO/SSO/RXD1/(TXD1)(2)
XOUT/XCOUT/P4_7 (1, 3)
XIN/XCIN/P4_6 (3)
VSS/AVSS
VCC/AVCC
RESET
NOTES:
1. P4_7 is an input-only port.
2. Can be assigned to the pin in parentheses by a program.
4. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.4 Pin Assignments (Top View)
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1.6 Pin Functions

Table 1.5 lists Pin Functions.
Table 1.5 Pin Functions

Type Symbol I/O Type Description
Power supply input VCC, VSS I Apply 2.2 to 5.5 V (J, K version are 2.7 to 5.5 V) to the VCC
pin. Apply 0 V to the VSS pin.
Analog power AVCC, AVSS I Power supply for the A/D converter.
supply input Connect a capacitor between AVCC and AVSS.
Reset input RESET I Input “L” on this pin resets the MCU.
MODE MODE I Connect this pin to VCC via a resistor.
XIN clock input XIN I These pins are provided for XIN clock generation circuit I/O.
Connect a ceramic resonator or a crystal oscillator between the
XIN and XOUT pins. To use an external clock, input it to the
XIN clock output XOUT O
XIN pin and leave the XOUT pin open.
XCIN clock input XCIN I These pins are provided for XCIN clock generation circuit I/O.
(N, D version) Connect a crystal oscillator between the XCIN and XCOUT
XCIN clock output XCOUT O pins. To use an external clock, input it to the XCIN pin and
(N, D version) leave the XCOUT pin open.
INT interrupt input INT0, INT1, INT3 I INT interrupt input pins
Key input interrupt KI0 to KI3 I Key input interrupt input pins
Timer RA TRAO O Timer RA output pin
TRAIO I/O Timer RA I/O pin
Timer RB TRBO O Timer RB output pin
Timer RC TRCCLK I External clock input pin
TRCTRG I External trigger input pin
TRCIOA, TRCIOB, I/O Sharing output-compare output / input-capture input / PWM /
TRCIOC, TRCIOD PWM2 output pins
Timer RE TREO O Timer RE output pin
Serial interface CLK0, CLK1 I/O Clock I/O pin
RXD0, RXD1 I Receive data input pin
TXD0, TXD1 O Transmit data output pin
I2C bus interface SCL I/O Clock I/O pin
SDA I/O Data I/O pin
Clock synchronous SSI I/O Data I/O pin
serial I/O with chip SCS I/O Chip-select signal I/O pin
select
SSCK I/O Clock I/O pin
SSO I/O Data I/O pin
Reference voltage VREF I Reference voltage input pin to A/D converter
input
A/D converter AN0 to AN11 I Analog input pins to A/D converter
I/O port P0_0 to P0_7, I/O CMOS I/O ports. Each port has an I/O select direction register,
P1_0 to P1_7, allowing each pin in the port to be directed for input or output
P3_1, P3_3 to individually.
P3_7, Any port set to input can be set to use a pull-up resistor or not
P4_5, by a program.
P5_3, P5_4 P1_0 to P1_7 also function as LED drive ports (N, D version).
Input port P4_2, P4_6, P4_7 I Input-only ports
I: Input O: Output I/O: Input and output
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Table 1.6 Pin Name Information by Pin Number

I/O Pin Functions for of Peripheral Modules
Pin Clock
Control Pin Port Serial Synchronous I2C bus A/D
Number Interrupt Timer
Interface Serial I/O with Interface Converter
Chip Select
1 P3_5 (TRCIOD) (1) SSCK SCL
2 RXD1/
P3_7 TRAO SSO
(TXD1)(1, 3)
3 RESET
4 XOUT/XCOUT(2) P4_7
5 VSS/AVSS
6 XIN/XCIN(2) P4_6
7 VCC/AVCC
8 MODE
9 P4_5 INT0 (RXD1)(1, 3)
10 P1_7 INT1 TRAIO
11 (TXD1)/
P3_6 (INT1)(1)
(RXD1)(1, 3)
12 P3_1 TRBO
13 P5_4 TRCIOD
14 P5_3 TRCIOC
15 P1_6 CLK0 (SSI)(1)
16 P1_5 (INT1)(1) (TRAIO)(1) RXD0
17 P1_4 TXD0
18 P1_3 KI3 (TRBO) AN11
19 P1_2 KI2 TRCIOB AN10
20 VRFF P4_2
21 P1_1 KI1 TRCIOA/ AN9
TRCTRG
22 P1_0 KI0 AN8
23 P3_3 INT3 TRCCLK SSI
24 P3_4 (TRCIOC)(1) SCS SDA
25 P0_7 AN0
26 P0_6 AN1
27 P0_5 CLK1 AN2
28 P0_4 TREO AN3
29 P0_3 AN4
30 P0_2 AN5
31 P0_1 AN6
32 P0_0 (TXD1)(1, 3) AN7
NOTES:
1. This can be assigned to the pin in parentheses by a program.
3. For the combination of using pins TXD1 and RXD1, refer to Figure 15.7 Registers PINSR1 and
PMR of Hardware Manual (REJ09B0278).
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R8C/26 Group, R8C/27 Group 2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
b31 b15 b8b7 b0
R2 R0H (high-order of R0) R0L (low-order of R0)

R3 R1H (high-order of R1) R1L (low-order of R1)
Data registers(1)
R2
R3
A0
Address registers(1)
A1
FB Frame base register(1)
b19 b15 b0
INTBH INTBL Interrupt table register
The 4 high order bits of INTB are INTBH and

the 16 low order bits of INTB are INTBL.
b19 b0
PC Program counter
b15 b0
USP User stack pointer
ISP Interrupt stack pointer
SB Static base register
b15 b0
FLG Flag register
b15 b8 b7 b0
IPL U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
NOTE:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1 CPU Registers
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2.1 Data Registers (R0, R1, R2, and R3)

R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2 Address Registers (A0 and A1)

A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 to be used
as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)

FB is a 16-bit register for FB relative addressing.
2.4 Interrupt Table Register (INTB)

INTB is a 20-bit register that indicates the start address of an interrupt vector table.
2.5 Program Counter (PC)

PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7 Static Base Register (SB)

SB is a 16-bit register for SB relative addressing.
2.8 Flag Register (FLG)

FLG is an 11-bit register indicating the CPU state.
2.8.1 Carry Flag (C)

The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2 Debug Flag (D)

The D flag is for debugging only. Set it to 0.
2.8.3 Zero Flag (Z)

The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4 Sign Flag (S)

The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5 Register Bank Select Flag (B)

Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6 Overflow Flag (O)

The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
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2.8.7 Interrupt Enable Flag (I)

The I flag enables maskable interrupts.
Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8 Stack Pointer Select Flag (U)

ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)

IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10 Reserved Bit

If necessary, set to 0. When read, the content is undefined.
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R8C/26 Group, R8C/27 Group 3. Memory
3. Memory
3.1 R8C/26 Group

Figure 3.1 is a Memory Map of R8C/26 Group. The R8C/26 group has 1 Mbyte of address space from addresses
00000h to FFFFFh.
The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal
ROM area is allocated addresses 0C000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1-Kbyte internal
RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also for
calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use
and cannot be accessed by users.
00000h
SFR
(Refer to 4. Special
Function Registers
(SFRs))
002FFh
00400h
Internal RAM
0XXXh
0FFDCh
Undefined instruction
Overflow
BRK instruction
Address match
Single step
0YYYYh Watchdog timer/oscillation stop detection/voltage monitor
Internal ROM (Reserved)

(program ROM) (Reserved)
Reset
0FFFFh 0FFFFh
FFFFFh
NOTE:
1. The blank regions are reserved. Do not access locations in these regions.
Internal ROM Internal RAM

Part Number
Size Address 0YYYYh Size Address 0XXXXh
R5F21262SNFP, R5F21262SDFP,
8 Kbytes 0E000h 512 bytes 005FFh
R5F21262SNXXXFP, R5F21262SDXXXFP
R5F21264JFP, R5F21264KFP,
16 Kbytes 0C000h 1 Kbyte 007FFh
R5F21264SNXXXFP, R5F21264SDXXXFP,
R5F21264JXXXFP, R5F21264KXXXFP
R5F21265SNFP, R5F21265SDFP
24 Kbytes 0A000h 1.5 Kbytes 009FFh
32 Kbytes 08000h 1.5 Kbytes 009FFh
Figure 3.1 Memory Map of R8C/26 Group
Rev.2.10 Sep 26, 2008 Page 15 of 69

REJ03B0168-0210
R8C/26 Group, R8C/27 Group 3. Memory
3.2 R8C/27 Group

Figure 3.2 is a Memory Map of R8C/27 Group. The R8C/27 group has 1 Mbyte of address space from addresses
00000h to FFFFFh.
The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a
16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each
interrupt routine.
The internal ROM (data flash) is allocated addresses 02400h to 02BFFh.
The internal RAM area is allocated higher addresses, beginning with address 00400h. For example, a 1-Kbyte
internal RAM is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also
for calling subroutines and as stacks when interrupt requests are acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control
registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use
and cannot be accessed by users.
00000h
SFR
(Refer to 4. Special
Function Registers
(SFRs))
002FFh
00400h
Internal RAM
0XXXXh
02400h
Internal ROM 0FFDCh
Undefined instruction
(data flash)(1) Overflow
02BFFh BRK instruction
Address match
Single step
0YYYYh Watchdog timer/oscillation stop detection/voltage monitor
Internal ROM (Reserved)

(program ROM) (Reserved)
Reset
0FFFFh 0FFFFh
FFFFFh
NOTES:
1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown.
Internal ROM Internal RAM
Part Number
Size Address 0YYYYh Size Address 0XXXXh
8 Kbytes 0E000h 512 bytes 005FFh
16 Kbytes 0C000h 1 Kbyte 007FFh
24 Kbytes 0A000h 1.5 Kbytes 009FFh
32 Kbytes 08000h 1.5 Kbytes 009FFh
Figure 3.2 Memory Map of R8C/27 Group
Rev.2.10 Sep 26, 2008 Page 16 of 69

REJ03B0168-0210
R8C/26 Group, R8C/27 Group 4. Special Function Registers (SFRs)
4. Special Function Registers (SFRs)

An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.7 list the special
function registers.
Table 4.1 SFR Information (1)(1)

Address Register Symbol After reset
0000h
0001h
0002h
0003h
0004h Processor Mode Register 0 PM0 00h
0005h Processor Mode Register 1 PM1 00h
0006h System Clock Control Register 0 CM0 01101000b
0007h System Clock Control Register 1 CM1 00100000b
0008h
0009h
000Ah Protect Register PRCR 00h
000Bh
000Ch Oscillation Stop Detection Register OCD 00000100b
000Dh Watchdog Timer Reset Register WDTR XXh
000Eh Watchdog Timer Start Register WDTS XXh
000Fh Watchdog Timer Control Register WDC 00X11111b
0010h Address Match Interrupt Register 0 RMAD0 00h
0011h 00h
0012h 00h
0013h Address Match Interrupt Enable Register AIER 00h
0014h Address Match Interrupt Register 1 RMAD1 00h
0015h 00h
0016h 00h
0017h
0018h
0019h
001Ah
001Bh
001Ch Count Source Protection Mode Register CSPR 00h
10000000b(2)
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h High-Speed On-Chip Oscillator Control Register 0 FRA0 00h
0024h High-Speed On-Chip Oscillator Control Register 1 FRA1 When shipping
0025h High-Speed On-Chip Oscillator Control Register 2 FRA2 00h
0026h
0027h
0028h Clock Prescaler Reset Flag CPSRF 00h
0029h High-Speed On-Chip Oscillator Control Register 4(3) FRA4 When shipping
002Ah
002Bh High-Speed On-Chip Oscillator Control Register 6(3) FRA6 When shipping
002Ch High-Speed On-Chip Oscillator Control Register 7(3) FRA7 When shipping
002Dh
002Eh
002Fh
X: Undefined
NOTES:
2. The CSPROINI bit in the OFS register is set to 0.
3. In J, K version these regions are reserved. Do not access locations in these regions.
Rev.2.10 Sep 26, 2008 Page 17 of 69

REJ03B0168-0210

0030h
0031h Voltage Detection Register 1 (2) VCA1 00001000b
0032h Voltage Detection Register 2 (2) VCA2 • N, D version 00h(3)
00100000b(4)
• J, K version 00h(7)
01000000b(8)
0033h
0034h
0035h
0036h Voltage Monitor 1 Circuit Control Register (5) VW1C • N, D version 00001000b
• J, K version 0000X000b(7)
0100X001b(8)
0037h Voltage Monitor 2 Circuit Control Register (5) VW2C 00h
0038h Voltage Monitor 0 Circuit Control Register (6) VW0C 0000X000b(3)
0100X001b(4)
0039h
003Fh
0040h
0041h
0042h
0043h
0044h
0045h
0046h
0047h Timer RC Interrupt Control Register TRCIC XXXXX000b
0048h
0049h
004Ah Timer RE Interrupt Control Register TREIC XXXXX000b
004Bh
004Ch
004Dh Key Input Interrupt Control Register KUPIC XXXXX000b
004Eh A/D Conversion Interrupt Control Register ADIC XXXXX000b
004Fh SSU/IIC bus Interrupt Control Register(9) SSUIC/IICIC XXXXX000b
0050h
0051h UART0 Transmit Interrupt Control Register S0TIC XXXXX000b
0052h UART0 Receive Interrupt Control Register S0RIC XXXXX000b
0053h UART1 Transmit Interrupt Control Register S1TIC XXXXX000b
0054h UART1 Receive Interrupt Control Register S1RIC XXXXX000b
0055h
0056h Timer RA Interrupt Control Register TRAIC XXXXX000b
0057h
0058h Timer RB Interrupt Control Register TRBIC XXXXX000b
0059h INT1 Interrupt Control Register INT1IC XX00X000b
005Ah INT3 Interrupt Control Register INT3IC XX00X000b
005Bh
005Ch
005Dh INT0 Interrupt Control Register INT0IC XX00X000b
005Eh
005Fh
0060h
006Fh
0070h
007Fh
X: Undefined
NOTES:
2. (N, D version) Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register.
(J, K version) Software reset, watchdog timer reset, or voltage monitor 2 reset do not affect this register.
3. The LVD0ON bit in the OFS register is set to 1 and hardware reset.
4. Power-on reset, voltage monitor 0 reset or the LVD0ON bit in the OFS register is set to 0, and hardware reset.
5. (N, D version) Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect b2 and b3.
(J, K version) Software reset, watchdog timer reset, or voltage monitor 2 reset do not affect b2 and b3.
6. (N, D version) Software reset, watchdog timer reset, voltage monitor 1 reset, or voltage monitor 2 reset do not affect this register.
(J, K version) These regions are reserved. Do not access locations in these regions.
7. The LVD1ON bit in the OFS register is set to 1 and hardware reset.
8. Power-on reset, voltage monitor 1 reset, or the LVD1ON bit in the OFS register is set to 0 and hardware reset.
9. Selected by the IICSEL bit in the PMR register.
Rev.2.10 Sep 26, 2008 Page 18 of 69

REJ03B0168-0210

0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h UART0 Transmit/Receive Mode Register U0MR 00h
00A1h UART0 Bit Rate Register U0BRG XXh
00A2h UART0 Transmit Buffer Register U0TB XXh
00A3h XXh
00A4h UART0 Transmit/Receive Control Register 0 U0C0 00001000b
00A5h UART0 Transmit/Receive Control Register 1 U0C1 00000010b
00A6h UART0 Receive Buffer Register U0RB XXh
00A7h XXh
00A8h UART1 Transmit/Receive Mode Register U1MR 00h
00A9h UART1 Bit Rate Register U1BRG XXh
00AAh UART1 Transmit Buffer Register U1TB XXh
00ABh XXh
00ACh UART1 Transmit/Receive Control Register 0 U1C0 00001000b
00ADh UART1 Transmit/Receive Control Register 1 U1C1 00000010b
00AEh UART1 Receive Buffer Register U1RB XXh
00AFh XXh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h SS Control Register H / IIC bus Control Register 1(2) SSCRH / ICCR1 00h
00B9h SS Control Register L / IIC bus Control Register 2(2) SSCRL / ICCR2 01111101b
00BAh SS Mode Register / IIC bus Mode Register(2) SSMR / ICMR 00011000b
00BBh SS Enable Register / IIC bus Interrupt Enable Register(2) SSER / ICIER 00h
00BCh SS Status Register / IIC bus Status Register(2) SSSR / ICSR 00h / 0000X000b
00BDh SS Mode Register 2 / Slave Address Register(2) SSMR2 / SAR 00h
00BEh SS Transmit Data Register / IIC bus Transmit Data Register(2) SSTDR / ICDRT FFh
00BFh SS Receive Data Register / IIC bus Receive Data Register(2) SSRDR / ICDRR FFh
X: Undefined
NOTES:
2. Selected by the IICSEL bit in the PMR register.
Rev.2.10 Sep 26, 2008 Page 19 of 69

REJ03B0168-0210

00C0h A/D Register AD XXh
00C1h XXh
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h A/D Control Register 2 ADCON2 00h
00D5h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h Port P0 Register P0 00h
00E2h Port P0 Direction Register PD0 00h
00E4h
00E6h
00EAh Port P4 Direction Register PD4 00h
00EBh Port P5 Direction Register PD5 00h
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h Pin Select Register 1 PINSR1 00h
00F8h Port Mode Register PMR 00h
00F9h External Input Enable Register INTEN 00h
00FAh INT Input Filter Select Register INTF 00h
00FBh Key Input Enable Register KIEN 00h
00FCh Pull-Up Control Register 0 PUR0 00h
00FDh Pull-Up Control Register 1 PUR1 00h
00FEh Port P1 Drive Capacity Control Register(2) P1DRR 00h
00FFh
X: Undefined
NOTES:
Rev.2.10 Sep 26, 2008 Page 20 of 69

REJ03B0168-0210

0100h Timer RA Control Register TRACR 00h
0101h Timer RA I/O Control Register TRAIOC 00h
0102h Timer RA Mode Register TRAMR 00h
0103h Timer RA Prescaler Register TRAPRE FFh
0104h Timer RA Register TRA FFh
0105h
0106h LIN Control Register LINCR 00h
0107h LIN Status Register LINST 00h
0108h Timer RB Control Register TRBCR 00h
0109h Timer RB One-Shot Control Register TRBOCR 00h
010Ah Timer RB I/O Control Register TRBIOC 00h
010Bh Timer RB Mode Register TRBMR 00h
010Ch Timer RB Prescaler Register TRBPRE FFh
010Dh Timer RB Secondary Register TRBSC FFh
010Eh Timer RB Primary Register TRBPR FFh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h Timer RE Second Data Register / Counter Data Register TRESEC 00h
0119h Timer RE Minute Data Register / Compare Data Register TREMIN 00h
011Ah Timer RE Hour Data Register(2) TREHR 00h
011Bh Timer RE Day of Week Data Register(2) TREWK 00h
011Ch Timer RE Control Register 1 TRECR1 00h
011Dh Timer RE Control Register 2 TRECR2 00h
011Eh Timer RE Count Source Select Register TRECSR 00001000b
011Fh
0120h Timer RC Mode Register TRCMR 01001000b
0121h Timer RC Control Register 1 TRCCR1 00h
0122h Timer RC Interrupt Enable Register TRCIER 01110000b
0123h Timer RC Status Register TRCSR 01110000b
0124h Timer RC I/O Control Register 0 TRCIOR0 10001000b
0125h Timer RC I/O Control Register 1 TRCIOR1 10001000b
0126h Timer RC Counter TRC 00h
0127h 00h
0128h Timer RC General Register A TRCGRA FFh
0129h FFh
012Ah Timer RC General Register B TRCGRB FFh
012Bh FFh
012Ch Timer RC General Register C TRCGRC FFh
012Dh FFh
012Eh Timer RC General Register D TRCGRD FFh
012Fh FFh
0130h Timer RC Control Register 2 TRCCR2 00011111b
0131h Timer RC Digital Filter Function Select Register TRCDF 00h
0132h Timer RC Output Master Enable Register TRCOER 01111111b
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
NOTES:
Rev.2.10 Sep 26, 2008 Page 21 of 69

REJ03B0168-0210

0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
NOTE:
Rev.2.10 Sep 26, 2008 Page 22 of 69

REJ03B0168-0210

0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h Flash Memory Control Register 4 FMR4 01000000b
01B4h
01B5h Flash Memory Control Register 1 FMR1 1000000Xb
01B6h
01B7h Flash Memory Control Register 0 FMR0 00000001b
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
FFFFh Option Function Select Register OFS (Note 2)

X: Undefined
NOTES:
2. The OFS register cannot be changed by a program. Use a flash programmer to write to it.
Rev.2.10 Sep 26, 2008 Page 23 of 69

REJ03B0168-0210
R8C/26 Group, R8C/27 Group 5. Electrical Characteristics
5. Electrical Characteristics
5.1 N, D Version
Table 5.1 Absolute Maximum Ratings

Symbol Parameter Condition Rated Value Unit
VCC/AVCC Supply voltage -0.3 to 6.5 V
VI Input voltage -0.3 to VCC + 0.3 V
VO Output voltage -0.3 to VCC + 0.3 V
Pd Power dissipation Topr = 25°C 500 mW
Topr Operating ambient temperature -20 to 85 (N version) / °C
-40 to 85 (D version)
Tstg Storage temperature -65 to 150 °C
Table 5.2 Recommended Operating Conditions

Standard
Symbol Parameter Conditions Unit
Min. Typ. Max.
VCC/AVCC Supply voltage 2.2 − 5.5 V
VSS/AVSS Supply voltage − 0 − V
VIH Input “H” voltage 0.8 VCC − VCC V
VIL Input “L” voltage 0 − 0.2 VCC V
IOH(sum) Peak sum output Sum of all pins IOH(peak) − − -160 mA
“H” current
IOH(sum) Average sum Sum of all pins IOH(avg) − − -80 mA
output “H” current
IOH(peak) Peak output “H” Except P1_0 to P1_7 − − -10 mA
current P1_0 to P1_7 − − -40 mA
IOH(avg) Average output Except P1_0 to P1_7 − − -5 mA
“H” current P1_0 to P1_7 − − -20 mA
IOL(sum) Peak sum output Sum of all pins IOL(peak) − − 160 mA
“L” currents
IOL(sum) Average sum Sum of all pins IOL(avg) − − 80 mA
output “L” currents
IOL(peak) Peak output “L” Except P1_0 to P1_7 − − 10 mA
currents P1_0 to P1_7 − − 40 mA
IOL(avg) Average output Except P1_0 to P1_7 − − 5 mA
“L” current P1_0 to P1_7 − − 20 mA
f(XIN) XIN clock input oscillation frequency 3.0 V ≤ VCC ≤ 5.5 V 0 − 20 MHz
2.7 V ≤ VCC < 3.0 V 0 − 10 MHz
2.2 V ≤ VCC < 2.7 V 0 − 5 MHz
f(XCIN) XCIN clock input oscillation frequency 2.2 V ≤ VCC ≤ 5.5 V 0 − 70 kHz
− System clock OCD2 = 0 3.0 V ≤ VCC ≤ 5.5 V 0 − 20 MHz
XlN clock selected 2.7 V ≤ VCC < 3.0 V 0 − 10 MHz
2.2 V ≤ VCC < 2.7 V 0 − 5 MHz
OCD2 = 1 FRA01 = 0 − 125 − kHz
On-chip oscillator clock Low-speed on-chip
selected oscillator clock selected
FRA01 = 1 − − 20 MHz
High-speed on-chip
oscillator clock selected
3.0 V ≤ VCC ≤ 5.5 V
FRA01 = 1 − − 10 MHz
High-speed on-chip
2.7 V ≤ VCC ≤ 5.5 V
FRA01 = 1 − − 5 MHz
High-speed on-chip
2.2 V ≤ VCC ≤ 5.5 V
NOTES:
1. VCC = 2.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. The average output current indicates the average value of current measured during 100 ms.
Rev.2.10 Sep 26, 2008 Page 24 of 69

REJ03B0168-0210
Table 5.3 A/D Converter Characteristics

Standard
Min. Typ. Max.
− Resolution Vref = AVCC − − 10 Bits
− Absolute 10-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V − − ±3 LSB
accuracy 8-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V − − ±2 LSB
10-bit mode φAD = 10 MHz, Vref = AVCC = 3.3 V − − ±5 LSB
Rladder Resistor ladder Vref = AVCC 10 − 40 kΩ
tconv Conversion time 10-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V 3.3 − − µs
8-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V 2.8 − − µs
Vref Reference voltage 2.2 − AVCC V
VIA Analog input voltage(2) 0 − AVCC V
− A/D operating Without sample and hold Vref = AVCC = 2.7 to 5.5 V 0.25 − 10 MHz
clock frequency With sample and hold Vref = AVCC = 2.7 to 5.5 V 1 − 10 MHz
Without sample and hold Vref = AVCC = 2.2 to 5.5 V 0.25 − 5 MHz
With sample and hold Vref = AVCC = 2.2 to 5.5 V 1 − 5 MHz
NOTES:
1. AVCC = 2.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
P0
P1
30pF
P3
P4
P5
Figure 5.1 Ports P0, P1, and P3 to P5 Timing Measurement Circuit
Rev.2.10 Sep 26, 2008 Page 25 of 69

REJ03B0168-0210
Table 5.4 Flash Memory (Program ROM) Electrical Characteristics

Standard
Min. Typ. Max.
− Program/erase endurance(2) R8C/26 Group 100(3) − − times
R8C/27 Group 1,000(3) − − times
− Byte program time − 50 400 µs
− Block erase time − 0.4 9 s
td(SR-SUS) Time delay from suspend request until − − 97 + CPU clock µs
suspend × 6 cycles
− Interval from erase start/restart until 650 − − µs
following suspend request
− Interval from program start/restart until 0 − − ns
− Time from suspend until program/erase − − 3 + CPU clock µs
restart × 4 cycles
− Program, erase voltage 2.7 − 5.5 V
− Read voltage 2.2 − 5.5 V
− Program, erase temperature 0 − 60 °C
− Data hold time(7) Ambient temperature = 55°C 20 − − year
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 1,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit
the number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
Rev.2.10 Sep 26, 2008 Page 26 of 69

REJ03B0168-0210
Table 5.5 Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4)
Standard
Min. Typ. Max.
− Program/erase endurance(2) 10,000(3) − − times
(program/erase endurance ≤ 1,000 times)
− Byte program time − 65 − µs
(program/erase endurance > 1,000 times)
− Block erase time − 0.3 − s
suspend × 6 cycles
restart × 4 cycles
− Program, erase temperature -20(8) − 85 °C
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times
is the same as that in program ROM.
before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A and B can further
reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the
number of erase operations to a certain number.
8. -40°C for D version.
Rev.2.10 Sep 26, 2008 Page 27 of 69

REJ03B0168-0210
Suspend request
(maskable interrupt request)
FMR46
Clock-dependent
Fixed time time
Access restart
td(SR-SUS)
Figure 5.2 Time delay until Suspend
Table 5.6 Voltage Detection 0 Circuit Electrical Characteristics

Standard
Symbol Parameter Condition Unit
Min. Typ. Max.
Vdet0 Voltage detection level 2.2 2.3 2.4 V
− Voltage detection circuit self power consumption VCA25 = 1, VCC = 5.0 V − 0.9 − µA
td(E-A) Waiting time until voltage detection circuit operation − − 300 µs
starts(2)
Vccmin MCU operating voltage minimum value 2.2 − − V
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version).
2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2
register to 0.

Standard
Min. Typ. Max.
Vdet1 Voltage detection level(4) 2.70 2.85 3.00 V
− Voltage monitor 1 interrupt request generation time(2) − 40 − µs
starts(3)
NOTES:
2. Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.
register to 0.
4. This parameter shows the voltage detection level when the power supply drops.
The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply
drops by approximately 0.1 V.

Standard
Min. Typ. Max.
Vdet2 Voltage detection level 3.3 3.6 3.9 V
− Voltage monitor 2 interrupt request generation time(2) − 40 − µs
starts(3)
NOTES:
2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
3. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
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Table 5.9 Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics(3)
Standard
Min. Typ. Max.
Vpor1 Power-on reset valid voltage(4) − − 0.1 V
Vpor2 Power-on reset or voltage monitor 0 reset valid 0 − Vdet0 V
voltage
trth External power VCC rise gradient(2) 20 − − mV/msec
NOTES:
1. The measurement condition is Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. This condition (external power VCC rise gradient) does not apply if VCC ≥ 1.0 V.
3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the
VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1.
4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on
reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if -20°C ≤ Topr ≤ 85°C, maintain tw(por1) for
3,000 s or more if -40°C ≤ Topr < -20°C.
Vdet0(3) Vdet0(3)
2.2 V trth
External trth
Power VCC
Vpor2
Vpor1
tw(por1) Sampling time(1, 2)
Internal
reset signal
(“L” valid)
1 1
× 32 × 32
fOCO-S fOCO-S
NOTES:
1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage
range (2.2 V or above) during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit of Hardware Manual for details.
3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit of Hardware Manual for details.
Figure 5.3 Reset Circuit Electrical Characteristics
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Table 5.10 High-speed On-Chip Oscillator Circuit Electrical Characteristics

Standard
Min. Typ. Max.
fOCO40M High-speed on-chip oscillator frequency VCC = 4.75 to 5.25 V 39.2 40 40.8 MHz
temperature • supply voltage dependence 0°C ≤ Topr ≤ 60°C(2)
VCC = 3.0 to 5.5 V 38.8 40 41.2 MHz
-20°C ≤ Topr ≤ 85°C(2)
VCC = 3.0 to 5.5 V 38.4 40 41.6 MHz
-40°C ≤ Topr ≤ 85°C(2)
VCC = 2.7 to 5.5 V 38 40 42 MHz
-20°C ≤ Topr ≤ 85°C(2)
VCC = 2.7 to 5.5 V 37.6 40 42.4 MHz
-40°C ≤ Topr ≤ 85°C(2)
VCC = 2.2 to 5.5 V 35.2 40 44.8 MHz
-20°C ≤ Topr ≤ 85°C(3)
VCC = 2.2 to 5.5 V 34 40 46 MHz
-40°C ≤ Topr ≤ 85°C(3)
VCC = 5.0 V ± 10% 38.8 40 40.8 MHz
-20°C ≤ Topr ≤ 85°C(2)
VCC = 5.0 V ± 10% 38.4 40 40.8 MHz
-40°C ≤ Topr ≤ 85°C(2)
High-speed on-chip oscillator frequency when VCC = 5.0 V, Topr = 25°C − 36.864 − MHz
correction value in FRA7 register is written to VCC = 3.0 to 5.5 V -3% − 3% %
FRA1 register(4) -20°C ≤ Topr ≤ 85°C
− Value in FRA1 register after reset 08h(3) − F7h(3) −
− Oscillation frequency adjustment unit of high- Adjust FRA1 register − +0.3 − MHz
speed on-chip oscillator (value after reset) to -1
− Oscillation stability time − 10 100 µs
− Self power consumption at oscillation VCC = 5.0 V, Topr = 25°C − 400 − µA
NOTES:
1. VCC = 2.2 to 5.5 V, Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. These standard values show when the FRA1 register value after reset is assumed.
3. These standard values show when the corrected value of the FRA6 register is written to the FRA1 register.
4. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in
UART mode.
Table 5.11 Low-speed On-Chip Oscillator Circuit Electrical Characteristics

Standard
Min. Typ. Max.
fOCO-S Low-speed on-chip oscillator frequency 30 125 250 kHz
NOTE:
1. VCC = 2.2 to 5.5 V, Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
Table 5.12 Power Supply Circuit Timing Characteristics

Standard
Min. Typ. Max.
td(P-R) Time for internal power supply stabilization during 1 − 2000 µs
power-on(2)
td(R-S) STOP exit time(3) − − 150 µs
NOTES:
1. The measurement condition is VCC = 2.2 to 5.5 V and Topr = 25°C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.
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Table 5.13 Timing Requirements of Clock Synchronous Serial I/O with Chip Select(1)
Standard Unit
Symbol Parameter Conditions
Min. Typ. Max.
tSUCYC SSCK clock cycle time 4 − − tCYC(2)
tHI SSCK clock “H” width 0.4 − 0.6 tSUCYC
tLO SSCK clock “L” width 0.4 − 0.6 tSUCYC
tRISE SSCK clock rising Master − − 1 tCYC(2)
time Slave − − 1 µs
tFALL SSCK clock falling Master − − 1 tCYC(2)
tSU SSO, SSI data input setup time 100 − − ns
tH SSO, SSI data input hold time 1 − − tCYC(2)
tLEAD SCS setup time Slave 1tCYC + 50 − − ns
tLAG SCS hold time Slave 1tCYC + 50 − − ns
tOD SSO, SSI data output delay time − − 1 tCYC(2)
tSA SSI slave access time 2.7 V ≤ VCC ≤ 5.5 V − − 1.5tCYC + 100 ns
2.2 V ≤ VCC < 2.7 V − − 1.5tCYC + 200 ns
tOR SSI slave out open time 2.7 V ≤ VCC ≤ 5.5 V − − 1.5tCYC + 100 ns
2.2 V ≤ VCC < 2.7 V − − 1.5tCYC + 200 ns
NOTES:
1. VCC = 2.2 to 5.5 V, VSS = 0 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
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4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIH or VOH
tHI tFALL tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO tSUCYC
SSO (output)
tOD
SSI (input)
tSU tH
VIH or VOH
SCS (output)
VIH or VOH
tHI tFALL tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO tSUCYC
SSO (output)
tOD
SSI (input)
tSU tH
CPHS, CPOS: Bits in SSMR register
Figure 5.4 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master)
Rev.2.10 Sep 26, 2008 Page 32 of 69

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4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIH or VOH
tLEAD tHI tFALL tRISE tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO tSUCYC
SSO (input)
tSU tH
SSI (output)
tSA tOD tOR
SCS (input) VIH or VOH
VIH or VOH
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO tSUCYC
SSO (input)
tSU tH
SSI (output)
tSA tOD tOR
Figure 5.5 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave)
Rev.2.10 Sep 26, 2008 Page 33 of 69

REJ03B0168-0210
tHI
VIH or VOH
SSCK
VIH or VOH
tLO tSUCYC
SSO (output)
tOD
SSI (input)
tSU tH
Figure 5.6 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous
Communication Mode)
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Table 5.14 Timing Requirements of I2C bus Interface(1)

Standard Unit
Symbol Parameter Condition
Min. Typ. Max.
tSCL SCL input cycle time 12tCYC + 600(2) − − ns
tSCLH SCL input “H” width 3tCYC + 300(2) − − ns
tSCLL SCL input “L” width 5tCYC + 500(2) − − ns
tsf SCL, SDA input fall time − − 300 ns
tSP SCL, SDA input spike pulse rejection time − − 1tCYC(2) ns
tBUF SDA input bus-free time 5tCYC(2) − − ns
tSTAH Start condition input hold time 3tCYC(2) − − ns
tSTAS Retransmit start condition input setup time 3tCYC(2) − − ns
tSTOP Stop condition input setup time 3tCYC(2) − − ns
tSDAS Data input setup time 1tCYC + 20(2) − − ns
tSDAH Data input hold time 0 − − ns
NOTES:
1. VCC = 2.2 to 5.5 V, VSS = 0 V and Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
VIH
SDA
VIL
tBUF
tSTAH tSCLH tSP tSTOP
tSTAS
SCL
P(2) S(1) Sr(3) P(2)
tSCLL
tsf tsr tSDAS
tSCL
tSDAH
NOTES:
1. Start condition
2. Stop condition
3. Retransmit start condition
Figure 5.7 I/O Timing of I2C bus Interface
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Table 5.15 Electrical Characteristics (1) [VCC = 5 V]

Standard
Min. Typ. Max.
VOH Output “H” voltage Except P1_0 to P1_7, IOH = −5 mA VCC - 2.0 − VCC V
XOUT IOH = -200 µA VCC - 0.5 − VCC V
P1_0 to P1_7 Drive capacity HIGH IOH = -20 mA VCC - 2.0 − VCC V
Drive capacity LOW IOH = -5 mA VCC - 2.0 − VCC V
XOUT Drive capacity HIGH IOH = -1 mA VCC - 2.0 − VCC V
Drive capacity LOW IOH = -500 µA VCC - 2.0 − VCC V
VOL Output “L” voltage Except P1_0 to P1_7, IOL = 5 mA − − 2.0 V
XOUT IOL = 200 µA − − 0.45 V
P1_0 to P1_7 Drive capacity HIGH IOL = 20 mA − − 2.0 V
Drive capacity LOW IOL = 5 mA − − 2.0 V
XOUT Drive capacity HIGH IOL = 1 mA − − 2.0 V
Drive capacity LOW IOL = 500 µA − − 2.0 V
VT+-VT- Hysteresis INT0, INT1, INT3, 0.1 0.5 − V
KI0, KI1, KI2, KI3,
TRAIO, RXD0, RXD1,
CLK0, CLK1,
SSI, SCL, SDA, SSO
RESET 0.1 1.0 − V
IIH Input “H” current VI = 5 V, VCC = 5 V − − 5.0 µA
IIL Input “L” current VI = 0 V, VCC = 5 V − − -5.0 µA
RPULLUP Pull-up resistance VI = 0 V, VCC = 5 V 30 50 167 kΩ
RfXIN Feedback XIN − 1.0 − MΩ
resistance
RfXCIN Feedback XCIN − 18 − MΩ
resistance
VRAM RAM hold voltage During stop mode 1.8 − − V
NOTE:
1. VCC = 4.2 to 5.5 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 20 MHz, unless otherwise specified.
Rev.2.10 Sep 26, 2008 Page 36 of 69

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Table 5.16 Electrical Characteristics (2) [Vcc = 5 V]

(Topr = -20 to 85°C (N version) / -40 to 85°C (D version), unless otherwise specified.)
Standard
Min. Typ. Max.
ICC Power supply current High-speed XIN = 20 MHz (square wave) − 10 17 mA
(VCC = 3.3 to 5.5 V) clock mode High-speed on-chip oscillator off
Single-chip mode, Low-speed on-chip oscillator on = 125 kHz
output pins are open, No division
other pins are VSS XIN = 16 MHz (square wave) − 9 15 mA
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 10 MHz (square wave) − 6 − mA
No division
Divide-by-8
Divide-by-8
XIN = 10 MHz (square wave) − 2.5 − mA
Divide-by-8
High-speed XIN clock off − 10 15 mA
on-chip High-speed on-chip oscillator on fOCO = 20 MHz
oscillator Low-speed on-chip oscillator on = 125 kHz
mode No division
XIN clock off − 4 − mA
High-speed on-chip oscillator on fOCO = 20 MHz
Divide-by-8
XIN clock off − 5.5 10 mA
No division
XIN clock off − 2.5 − mA
Divide-by-8
Low-speed XIN clock off − 130 300 µA
on-chip High-speed on-chip oscillator off
mode Divide-by-8, FMR47 = 1
clock mode High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR47 = 1
XIN clock off − 30 − µA
Program operation on RAM
Flash memory off, FMSTP = 1
Rev.2.10 Sep 26, 2008 Page 37 of 69

REJ03B0168-0210

Standard
Min. Typ. Max.
ICC Power supply current Wait mode XIN clock off − 25 75 µA
(VCC = 3.3 to 5.5 V) High-speed on-chip oscillator off
output pins are open, While a WAIT instruction is executed
other pins are VSS Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off − 23 60 µA
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off − 4.0 − µA
XCIN clock oscillator on = 32 kHz (high drive)
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XCIN clock oscillator on = 32 kHz (low drive)
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
Stop mode XIN clock off, Topr = 25°C − 0.8 3.0 µA
CM10 = 1
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85°C − 1.2 − µA
CM10 = 1
VCA27 = VCA26 = VCA25 = 0
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REJ03B0168-0210
Timing Requirements
(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V]
Table 5.18 XIN Input, XCIN Input

Standard
Symbol Parameter Unit
Min. Max.
tc(XIN) XIN input cycle time 50 − ns
tWH(XIN) XIN input “H” width 25 − ns
tWL(XIN) XIN input “L” width 25 − ns
tc(XCIN) XCIN input cycle time 14 − µs
tWH(XCIN) XCIN input “H” width 7 − µs
tWL(XCIN) XCIN input “L” width 7 − µs
tC(XIN) VCC = 5 V
tWH(XIN)
XIN input
tWL(XIN)
Figure 5.8 XIN Input and XCIN Input Timing Diagram when VCC = 5 V
Table 5.19 TRAIO Input

Standard
Min. Max.
tc(TRAIO) TRAIO input cycle time 100 − ns
tWH(TRAIO) TRAIO input “H” width 40 − ns
tWL(TRAIO) TRAIO input “L” width 40 − ns
tC(TRAIO) VCC = 5 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.9 TRAIO Input Timing Diagram when VCC = 5 V
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Table 5.20 Serial Interface

Standard
Min. Max.
tc(CK) CLKi input cycle time 200 − ns
tW(CKH) CLKi input “H” width 100 − ns
tW(CKL) CLKi input “L” width 100 − ns
td(C-Q) TXDi output delay time − 50 ns
th(C-Q) TXDi hold time 0 − ns
tsu(D-C) RXDi input setup time 50 − ns
th(C-D) RXDi input hold time 90 − ns
i = 0 or 1
tC(CK) VCC = 5 V
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q) tsu(D-C) th(C-D)
RXDi
i = 0 or 1
Figure 5.10 Serial Interface Timing Diagram when VCC = 5 V
Table 5.21 External Interrupt INTi (i = 0, 1, 3) Input

Standard
Min. Max.
tW(INH) INTi input “H” width 250(1) − ns
tW(INL) INTi input “L” width 250(2) − ns
NOTES:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
VCC = 5 V
tW(INL)
INTi input
tW(INH)
i = 0, 1, 3
Figure 5.11 External Interrupt INTi Input Timing Diagram when VCC = 5 V
Rev.2.10 Sep 26, 2008 Page 40 of 69

REJ03B0168-0210

Standard
Min. Typ. Max.
VOH Output “H” voltage Except P1_0 to P1_7, IOH = -1 mA VCC - 0.5 − VCC V
XOUT
P1_0 to P1_7 Drive capacity IOH = -5 mA VCC - 0.5 − VCC V
HIGH
Drive capacity IOH = -1 mA VCC - 0.5 − VCC V
LOW
XOUT Drive capacity IOH = -0.1 mA VCC - 0.5 − VCC V
HIGH
Drive capacity IOH = -50 µA VCC - 0.5 − VCC V
LOW
XOUT
P1_0 to P1_7 Drive capacity IOL = 5 mA − − 0.5 V
HIGH
Drive capacity IOL = 1 mA − − 0.5 V
LOW
XOUT Drive capacity IOL = 0.1 mA − − 0.5 V
HIGH
Drive capacity IOL = 50 µA − − 0.5 V
LOW
KI0, KI1, KI2, KI3,
TRAIO, RXD0, RXD1,
CLK0, CLK1,
SSI, SCL, SDA, SSO
RESET 0.1 0.4 − V
IIH Input “H” current VI = 3 V, VCC = 3 V − − 4.0 µA
IIL Input “L” current VI = 0 V, VCC = 3 V − − -4.0 µA
RPULLUP Pull-up resistance VI = 0 V, VCC = 3 V 66 160 500 kΩ
RfXIN Feedback resistance XIN − 3.0 − MΩ
RfXCIN Feedback resistance XCIN − 18 − MΩ
NOTE:
1. VCC = 2.7 to 3.3 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 10 MHz, unless otherwise specified.
Rev.2.10 Sep 26, 2008 Page 41 of 69

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Standard
Min. Typ. Max.
ICC Power supply current High-speed XIN = 10 MHz (square wave) − 6 − mA
Single-chip mode, No division
output pins are open,
other pins are VSS
Divide-by-8
oscillator
No division
mode
Divide-by-8
oscillator
Divide-by-8, FMR47 = 1
mode
FMR47 = 1
Wait mode XIN clock off − 25 70 µA
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
CM10 = 1
VCA27 = VCA26 = VCA25 = 0
CM10 = 1
VCA27 = VCA26 = VCA25 = 0
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Timing requirements

Standard
Min. Max.
tC(XIN) VCC = 3 V
tWH(XIN)
XIN input
tWL(XIN)
Figure 5.12 XIN Input and XCIN Input Timing Diagram when VCC = 3 V

Standard
Min. Max.
tC(TRAIO) VCC = 3 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
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REJ03B0168-0210

Standard
Min. Max.
tW(CKL) CLKi Input “L” width 150 − ns
i = 0 or 1
tC(CK) VCC = 3 V
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
RXDi
i = 0 or 1

Standard
Min. Max.
NOTES:
VCC = 3 V
tW(INL)
INTi input
tW(INH)
i = 0, 1, 3
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Table 5.28 Electrical Characteristics (5) [VCC = 2.2 V]

Standard
Min. Typ. Max.
VOH Output “H” voltage Except P1_0 to P1_7, IOH = -1 mA VCC - 0.5 − VCC V
XOUT
P1_0 to P1_7 Drive capacity IOH = -2 mA VCC - 0.5 − VCC V
HIGH
Drive capacity IOH = -1 mA VCC - 0.5 − VCC V
LOW
HIGH
LOW
XOUT
P1_0 to P1_7 Drive capacity IOL = 2 mA − − 0.5 V
HIGH
Drive capacity IOL = 1 mA − − 0.5 V
LOW
HIGH
LOW
KI0, KI1, KI2, KI3,
TRAIO, RXD0, RXD1,
CLK0, CLK1,
SSI, SCL, SDA, SSO
RESET 0.05 0.15 − V
IIH Input “H” current VI = 2.2 V − − 4.0 µA
IIL Input “L” current VI = 0 V − − -4.0 µA
RPULLUP Pull-up resistance VI = 0 V 100 200 600 kΩ
RfXIN Feedback resistance XIN − 5 − MΩ
RfXCIN Feedback resistance XCIN − 35 − MΩ
NOTE:
1. VCC = 2.2 V at Topr = -20 to 85°C (N version) / -40 to 85°C (D version), f(XIN) = 5 MHz, unless otherwise specified.
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Table 5.29 Electrical Characteristics (6) [Vcc = 2.2 V]

Standard
Min. Typ. Max.
ICC Power supply current High-speed XIN = 5 MHz (square wave) − 3.5 − mA
output pins are open,
other pins are VSS
Divide-by-8
High-speed XIN clock off − 3.5 − mA
oscillator
No division
mode
Divide-by-8
oscillator
Divide-by-8, FMR47 = 1
mode
FMR47 = 1
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
CM10 = 1
VCA27 = VCA26 = VCA25 = 0
CM10 = 1
VCA27 = VCA26 = VCA25 = 0
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Timing requirements
(Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25°C) [VCC = 2.2 V]

Standard
Min. Max.
tC(XIN) VCC = 2.2 V

tWH(XIN)
XIN input
tWL(XIN)
Figure 5.16 XIN Input and XCIN Input Timing Diagram when VCC = 2.2 V

Standard
Min. Max.
tC(TRAIO) VCC = 2.2 V

tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.17 TRAIO Input Timing Diagram when VCC = 2.2 V
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REJ03B0168-0210

Standard
Min. Max.
i = 0 or 1
tC(CK) VCC = 2.2 V

tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
RXDi
i = 0 or 1
Figure 5.18 Serial Interface Timing Diagram when VCC = 2.2 V

Standard
Min. Max.
tW(INH) INTi input “H” width 1000 (1) − ns
NOTES:
VCC = 2.2 V
tW(INL)
INTi input
tW(INH)
i = 0, 1, 3
Figure 5.19 External Interrupt INTi Input Timing Diagram when VCC = 2.2 V
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5.2 J, K Version
Table 5.34 Absolute Maximum Ratings

Symbol Parameter Condition Rated Value Unit
VCC/AVCC Supply voltage -0.3 to 6.5 V
VI Input voltage -0.3 to VCC + 0.3 V
VO Output voltage -0.3 to VCC + 0.3 V
Pd Power dissipation -40 °C ≤ Topr ≤ 85 °C 300 mW
85 °C ≤ Topr ≤ 125 °C 125 mW
Topr Operating ambient temperature -40 to 85 (J version) / °C
-40 to 125 (K version)
Tstg Storage temperature -65 to 150 °C
Table 5.35 Recommended Operating Conditions

Standard
Min. Typ. Max.
VCC/AVCC Supply voltage 2.7 − 5.5 V
VSS/AVSS Supply voltage − 0 − V
VIH Input “H” voltage 0.8 VCC − VCC V
VIL Input “L” voltage 0 − 0.2 VCC V
IOH(sum) Peak sum output Sum of all pins − − -60 mA
“H” current IOH(peak)
IOH(peak) Peak output “H” − − -10 mA
current
IOH(avg) Average output − − -5 mA
“H” current
IOL(sum) Peak sum output Sum of all pins − − 60 mA
“L” currents IOL(peak)
IOL(peak) Peak output “L” − − 10 mA
currents
IOL(avg) Average output − − 5 mA
“L” current
f(XIN) XIN clock input oscillation frequency 3.0 V ≤ VCC ≤ 5.5 V (other than K 0 − 20 MHz
version)
3.0 V ≤ VCC ≤ 5.5 V (K version) 0 − 16 MHz
2.7 V ≤ VCC < 3.0 V 0 − 10 MHz
− System clock OCD2 = 0 3.0 V ≤ VCC ≤ 5.5 V (other than K 0 − 20 MHz
XlN clock selected version)
3.0 V ≤ VCC ≤ 5.5 V (K version) 0 − 16 MHz
2.7 V ≤ VCC < 3.0 V 0 − 10 MHz
OCD2 = 1 FRA01 = 0 − 125 − kHz
On-chip oscillator Low-speed on-chip oscillator clock
clock selected selected
FRA01 = 1 − − 20 MHz
High-speed on-chip oscillator clock
selected (other than K version)
FRA01 = 1 − − 10 MHz
High-speed on-chip oscillator clock
selected
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. The average output current indicates the average value of current measured during 100 ms.
Rev.2.10 Sep 26, 2008 Page 49 of 69

REJ03B0168-0210
Table 5.36 A/D Converter Characteristics

Standard
Min. Typ. Max.
− Resolution Vref = AVCC − − 10 Bits
− Absolute 10-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V − − ±3 LSB
accuracy 8-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V − − ±2 LSB
Rladder Resistor ladder Vref = AVCC 10 − 40 kΩ
tconv Conversion time 10-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V 3.3 − − µs
8-bit mode φAD = 10 MHz, Vref = AVCC = 5.0 V 2.8 − − µs
Vref Reference voltage 2.7 − AVCC V
VIA Analog input voltage(2) 0 − AVCC V
− A/D operating Without sample and hold 0.25 − 10 MHz
clock frequency With sample and hold 1 − 10 MHz
NOTES:
1. AVCC = 2.7 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
P0
P1
30pF
P3
P4
P5
Figure 5.20 Ports P0, P1, and P3 to P5 Timing Measurement Circuit
Rev.2.10 Sep 26, 2008 Page 50 of 69

REJ03B0168-0210
Table 5.37 Flash Memory (Program ROM) Electrical Characteristics

Standard
Min. Typ. Max.
− Program/erase endurance(2) R8C/26 Group 100(3) − − times
R8C/27 Group 1,000(3) − − times
suspend × 6 cycles
restart × 4 cycles
− Program, erase temperature 0 − 60 °C
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.
If the programming and erasure endurance is n (n = 100 or 1,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit
the number of erase operations to a certain number.
Rev.2.10 Sep 26, 2008 Page 51 of 69

REJ03B0168-0210
Table 5.38 Flash Memory (Data flash Block A, Block B) Electrical Characteristics(4)
Standard
Min. Typ. Max.
− Program/erase endurance(2) 10,000(3) − − times
− Byte program time − 65 − µs
− Block erase time − 0.3 − s
suspend × 6 cycles
restart × 4 cycles
− Program, erase temperature -40 − 85(8) °C
NOTES:
1. VCC = 2.7 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
4. Standard of block A and block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times
is the same as that in program ROM.
before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A and B can further
reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the
number of erase operations to a certain number.
8. 125°C for K version.
Rev.2.10 Sep 26, 2008 Page 52 of 69

REJ03B0168-0210
Suspend request
(maskable interrupt request)
FMR46
Clock-dependent
Fixed time time
Access restart
td(SR-SUS)
Figure 5.21 Time delay until Suspend

Standard
Min. Typ. Max.
Vdet1 Voltage detection level(2, 4) 2.70 2.85 3.0 V
td(Vdet1-A) Voltage monitor 1 reset generation time(5) − 40 200 µs
starts(3)
Vccmin MCU operating voltage minimum value 2.70 − − V
NOTES:
1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = -40 to 85°C (J version) / -40 to 125°C (K version).
2. Hold Vdet2 > Vdet1.
register to 0.
4. This parameter shows the voltage detection level when the power supply drops.
The voltage detection level when the power supply rises is higher than the voltage detection level when the power supply
drops by approximately 0.1 V.
5. Time until the voltage monitor 1 reset is generated after the voltage passes Vdet1 when VCC falls. When using the digital filter,
its sampling time is added to td(Vdet1-A). When using the voltage monitor 1 reset, maintain this time until VCC = 2.0 V after the
voltage passes Vdet1 when the power supply falls.

Standard
Min. Typ. Max.
Vdet2 Voltage detection level(2) 3.3 3.6 3.9 V
td(Vdet2-A) Voltage monitor 2 reset/interrupt request generation − 40 200 µs
time(3, 5)
starts(4)
NOTES:
1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = -40 to 85°C (J version) / -40 to 125°C (K version).
2. Hold Vdet2 > Vdet1.
3. Time until the voltage monitor 2 reset/interrupt request is generated after the voltage passes Vdet2.
4. Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
5. When using the digital filter, its sampling time is added to td(Vdet2-A). When using the voltage monitor 2 reset, maintain this time
until VCC = 2.0 V after the voltage passes Vdet2 when the power supply falls.
Rev.2.10 Sep 26, 2008 Page 53 of 69

REJ03B0168-0210
Table 5.41 Power-on Reset Circuit, Voltage Monitor 1 Reset Electrical Characteristics(3)
Standard
Min. Typ. Max.
Vpor1 Power-on reset valid voltage(4) − − 0.1 V
Vpor2 Power-on reset or voltage monitor 1 reset valid 0 − Vdet1 V
voltage
trth External power VCC rise gradient VCC ≤ 3.6 V 20(2) − − mV/msec
VCC > 3.6 V 20(2) − 2,000 mV/msec
NOTES:
1. The measurement condition is Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. This condition (the minimum value of external power VCC rise gradient) does not apply if Vpor2 ≥ 1.0 V.
3. To use the power-on reset function, enable voltage monitor 1 reset by setting the LVD1ON bit in the OFS register to 0, the
VW1C0 and VW1C6 bits in the VW1C register to 1 respectively, and the VCA26 bit in the VCA2 register to 1.
4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on
reset. When turning on the power for the first time, maintain tw(por1) for 30 s or more if -20°C ≤ Topr ≤ 125°C, maintain tw(por1) for
3,000 s or more if -40°C ≤ Topr < -20°C.
Vdet1(3) Vdet1(3)
trth trth
2.0 V
External
power VCC td(Vdet1-A)
Vpor2
Vpor1
tw(por1)
Sampling time(1, 2)
Internal reset
signal
(“L” valid)
1 1
× 32 × 32
fOCO-S fOCO-S
NOTES:
1. When using the voltage monitor 1 digital filter, ensure VCC is 2.0 V or higher during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit of Hardware Manual for details.
3. Vdet1 indicates the voltage detection level of the voltage detection 1 circuit. Refer to 6. Voltage Detection
Circuit of Hardware Manual for details.
Figure 5.22 Reset Circuit Electrical Characteristics
Rev.2.10 Sep 26, 2008 Page 54 of 69

REJ03B0168-0210
Table 5.42 High-speed On-Chip Oscillator Circuit Electrical Characteristics

Standard
Min. Typ. Max.
fOCO40M High-speed on-chip oscillator frequency VCC = 4.75 to 5.25 V 39.2 40 40.8 MHz
temperature · supply voltage dependence 0°C ≤ Topr ≤ 60°C(2)
VCC = 3.0 to 5.5 V 38.8 40 41.2 MHz
-20°C ≤ Topr ≤ 85°C(2)
VCC = 3.0 to 5.5 V 38.4 40 41.6 MHz
-40°C ≤ Topr ≤ 85°C(2)
VCC = 3.0 to 5.5 V 38 40 42 MHz
-40°C ≤ Topr ≤ 125°C(2)
VCC = 2.7 to 5.5 V 37.6 40 42.4 MHz
-40°C ≤ Topr ≤ 125°C(2)
− Value in FRA1 register after reset 08h − F7h −
− Oscillation frequency adjustment unit of high- Adjust FRA1 register − +0.3 − MHz
speed on-chip oscillator (value after reset) to -1
NOTES:
1. VCC = 2.7 to 5.5 V, Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. These standard values show when the FRA1 register value after reset is assumed.
Table 5.43 Low-speed On-Chip Oscillator Circuit Electrical Characteristics

Standard
Min. Typ. Max.
fOCO-S Low-speed on-chip oscillator frequency 40 125 250 kHz
NOTE:
1. VCC = 2.7 to 5.5 V, Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
Table 5.44 Power Supply Circuit Timing Characteristics

Standard
Min. Typ. Max.
td(P-R) Time for internal power supply stabilization during 1 − 2000 µs
power-on(2)
td(R-S) STOP exit time(3) − − 150 µs
NOTES:
1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = 25°C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.
Rev.2.10 Sep 26, 2008 Page 55 of 69

REJ03B0168-0210
Table 5.45 Timing Requirements of Clock Synchronous Serial I/O with Chip Select(1)
Standard Unit
Symbol Parameter Conditions
Min. Typ. Max.
tSUCYC SSCK clock cycle time 4 − − tCYC(2)
tHI SSCK clock “H” width 0.4 − 0.6 tSUCYC
tLO SSCK clock “L” width 0.4 − 0.6 tSUCYC
tRISE SSCK clock rising Master − − 1 tCYC(2)
tFALL SSCK clock falling Master − − 1 tCYC(2)
tSU SSO, SSI data input setup time 100 − − ns
tH SSO, SSI data input hold time 1 − − tCYC(2)
tLEAD SCS setup time Slave 1tCYC + 50 − − ns
tLAG SCS hold time Slave 1tCYC + 50 − − ns
tOD SSO, SSI data output delay time − − 1 tCYC(2)
tSA SSI slave access time − − 1.5tCYC + 100 ns
tOR SSI slave out open time − − 1.5tCYC + 100 ns
NOTES:
1. VCC = 2.7 to 5.5 V, VSS = 0 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
Rev.2.10 Sep 26, 2008 Page 56 of 69

REJ03B0168-0210
VIH or VOH
SCS (output)
VIH or VOH
tHI tFALL tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO tSUCYC
SSO (output)
tOD
SSI (input)
tSU tH
VIH or VOH
SCS (output)
VIH or VOH
tHI tFALL tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO tSUCYC
SSO (output)
tOD
SSI (input)
tSU tH
Figure 5.23 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master)
Rev.2.10 Sep 26, 2008 Page 57 of 69

REJ03B0168-0210
VIH or VOH
SCS (input)
VIH or VOH
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO tSUCYC
SSO (input)
tSU tH
SSI (output)
tSA tOD tOR
SCS (input) VIH or VOH
VIH or VOH
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO tSUCYC
SSO (input)
tSU tH
SSI (output)
tSA tOD tOR
Figure 5.24 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave)
Rev.2.10 Sep 26, 2008 Page 58 of 69

REJ03B0168-0210
tHI
VIH or VOH
SSCK
VIH or VOH
tLO tSUCYC
SSO (output)
tOD
SSI (input)
tSU tH
Figure 5.25 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous
Communication Mode)
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REJ03B0168-0210
Table 5.46 Timing Requirements of I2C bus Interface(1)

Standard Unit
Symbol Parameter Condition
Min. Typ. Max.
tSCL SCL input cycle time 12tCYC + 600(2) − − ns
tSCLH SCL input “H” width 3tCYC + 300(2) − − ns
tSCLL SCL input “L” width 5tCYC + 500(2) − − ns
tsf SCL, SDA input fall time − − 300 ns
tSP SCL, SDA input spike pulse rejection time − − 1tCYC(2) ns
tBUF SDA input bus-free time 5tCYC(2) − − ns
tSTAH Start condition input hold time 3tCYC(2) − − ns
tSTAS Retransmit start condition input setup time 3tCYC(2) − − ns
tSTOP Stop condition input setup time 3tCYC(2) − − ns
tSDAS Data input setup time 1tCYC + 20(2) − − ns
tSDAH Data input hold time 0 − − ns
NOTES:
1. VCC = 2.7 to 5.5 V, VSS = 0 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
VIH
SDA
VIL
tBUF
tSTAH tSCLH tSP tSTOP
tSTAS
SCL
P(2) S(1) Sr(3) P(2)
tSCLL
tsf tsr tSDAS
tSCL
tSDAH
NOTES:
1. Start condition
2. Stop condition
3. Retransmit start condition
Figure 5.26 I/O Timing of I2C bus Interface
Rev.2.10 Sep 26, 2008 Page 60 of 69

REJ03B0168-0210

Standard
Min. Typ. Max.
VOH Output “H” voltage Except XOUT IOH = -5 mA VCC - 2.0 − VCC V
IOH = -200 µA VCC - 0.3 − VCC V
XOUT Drive capacity HIGH IOH = -1 mA VCC - 2.0 − VCC V
Drive capacity LOW IOH = -500 µA VCC - 2.0 − VCC V
VOL Output “L” voltage Except XOUT IOL = 5 mA − − 2.0 V
IOL = 200 µA − − 0.45 V
XOUT Drive capacity HIGH IOL = 1 mA − − 2.0 V
Drive capacity LOW IOL = 500 µA − − 2.0 V
KI0, KI1, KI2, KI3,
TRAIO, RXD0, RXD1,
CLK0, CLK1,
SSI, SCL, SDA, SSO
RESET 0.1 1.0 − V
IIH Input “H” current VI = 5 V, VCC = 5V − − 5.0 µA
IIL Input “L” current VI = 0 V, VCC = 5V − − -5.0 µA
RPULLUP Pull-up resistance VI = 0 V, VCC = 5V 30 50 167 kΩ
RfXIN Feedback XIN − 1.0 − MΩ
resistance
NOTE:
1. VCC = 4.2 to 5.5 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), f(XIN) = 20 MHz, unless otherwise specified.
Rev.2.10 Sep 26, 2008 Page 61 of 69

REJ03B0168-0210

(Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.)
Standard
Min. Typ. Max.
ICC Power supply current High-speed XIN = 20 MHz (square wave) − 10 17 mA
output pins are open, XIN = 16 MHz (square wave) − 9 15 mA
other pins are VSS High-speed on-chip oscillator off
No division
No division
Divide-by-8
Divide-by-8
Divide-by-8
on-chip High-speed on-chip oscillator on fOCO = 20 MHz (J version)
oscillator No division
mode XIN clock off − 4 − mA
High-speed on-chip oscillator on fOCO = 20 MHz (J version)
Divide-by-8
XIN clock off − 5.5 10 mA
No division
Divide-by-8
oscillator Divide-by-8, FMR47 = 1
mode
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
CM10 = 1
VCA27 = VCA26 = VCA25 = 0
CM10 = 1
VCA27 = VCA26 = VCA25 = 0
CM10 = 1
VCA27 = VCA26 = VCA25 = 0
Rev.2.10 Sep 26, 2008 Page 62 of 69

REJ03B0168-0210
Timing Requirements
Table 5.49 XIN Input

Standard
Min. Max.
tC(XIN) VCC = 5 V
tWH(XIN)
XIN input
tWL(XIN)
Figure 5.27 XIN Input Timing Diagram when VCC = 5 V

Standard
Min. Max.
tC(TRAIO) VCC = 5 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Rev.2.10 Sep 26, 2008 Page 63 of 69

REJ03B0168-0210

Standard
Min. Max.
i = 0 or 1
tC(CK) VCC = 5 V
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
RXDi
i = 0 or 1

Standard
Min. Max.
NOTES:
VCC = 5 V
tW(INL)
INTi input
tW(INH)
i = 0, 1, 3
Rev.2.10 Sep 26, 2008 Page 64 of 69

REJ03B0168-0210

Standard
Min. Typ. Max.
VOH Output “H” voltage Except XOUT IOH = -1 mA VCC - 0.5 − VCC V
HIGH
LOW
VOL Output “L” voltage Except XOUT IOL = 1 mA − − 0.5 V
HIGH
LOW
KI0, KI1, KI2, KI3,
TRAIO, RXD0, RXD1,
CLK0,CLK1,
SSI, SCL, SDA, SSO
RESET 0.1 0.4 − V
IIH Input “H” current VI = 3 V, VCC = 3V − − 4.0 µA
IIL Input “L” current VI = 0 V, VCC = 3V − − -4.0 µA
RPULLUP Pull-up resistance VI = 0 V, VCC = 3V 66 160 500 kΩ
RfXIN Feedback resistance XIN − 3.0 − MΩ
NOTE:
1. VCC = 2.7 to 3.3 V at Topr = -40 to 85°C (J version) / -40 to 125°C (K version), f(XIN) = 10 MHz, unless otherwise specified.
Rev.2.10 Sep 26, 2008 Page 65 of 69

REJ03B0168-0210

(Topr = -40 to 85°C (J version) / -40 to 125°C (K version), unless otherwise specified.)
Standard
Min. Typ. Max.
ICC Power supply current High-speed XIN = 10 MHz (square wave) − 6 − mA
output pins are open, No division
other pins are VSS XIN = 10 MHz (square wave) − 2 − mA
Divide-by-8
mode No division
Divide-by-8
mode Divide-by-8, FMR47 = 1
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
CM10 = 1
VCA27 = VCA26 = VCA25 = 0
CM10 = 1
VCA27 = VCA26 = VCA25 = 0
CM10 = 1
VCA27 = VCA26 = VCA25 = 0
Rev.2.10 Sep 26, 2008 Page 66 of 69

REJ03B0168-0210
Timing requirements
Table 5.55 XIN Input

Standard
Min. Max.
tC(XIN) VCC = 3 V
tWH(XIN)
XIN input
tWL(XIN)
Figure 5.31 XIN Input Timing Diagram when VCC = 3 V

Standard
Min. Max.
tC(TRAIO) VCC = 3 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Rev.2.10 Sep 26, 2008 Page 67 of 69

REJ03B0168-0210

Standard
Min. Max.
tW(CKL) CLKi Input “L” width 150 − ns
i = 0 or 1
tC(CK) VCC = 3 V
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
RXDi
i = 0 or 1

Standard
Min. Max.
NOTES:
VCC = 3 V
tW(INL)
INTi input
tW(INH)
i = 0, 1, 3
Rev.2.10 Sep 26, 2008 Page 68 of 69

REJ03B0168-0210
R8C/26 Group, R8C/27 Group Package Dimensions
Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Technology website.
JEITA Package Code RENESAS Code Previous Code MASS[Typ.]

P-LQFP32-7x7-0.80 PLQP0032GB-A 32P6U-A 0.2g
HD
*1
D
24 17
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
16 2. DIMENSION "*3" DOES NOT
25
INCLUDE TRIM OFFSET.
bp
b1
HE
E
c1
c
*2
Reference Dimension in Millimeters

Symbol
Min Nom Max
D 6.9 7.0 7.1
Terminal cross section
E 6.9 7.0 7.1
32
9 A2 1.4
ZE
HD 8.8 9.0 9.2

HE 8.8 9.0 9.2
1 8
A 1.7
ZD Index mark
A1 0 0.1 0.2
F A2 bp 0.32 0.37 0.42
A
c
b1 0.35
c 0.09 0.145 0.20
c1 0.125
A1
L
L1 0° 8°
e 0.8
Detail F
y
*3 x 0.20
e bp
x y 0.10
ZD 0.7
ZE 0.7
L 0.3 0.5 0.7
L1 1.0
Rev.2.10 Sep 26, 2008 Page 69 of 69

REJ03B0168-0210
REVISION HISTORY R8C/26 Group, R8C/27 Group Datasheet
Description
Rev. Date
Page Summary
0.10 Nov 14, 2005 − First edition issued
0.20 Feb 06, 2006 2, 3 Table 1.1 Functions and Specifications for R8C/26Group and Table 1.2
Functions and Specifications for R8C/27 Group;
Minimum instruction execution time and Supply voltage revised
9 Table 1.6 Pin Name Information by Pin Number;
“XOUT” → “XOUT/XCOUT” and “XIN” → “XIN/XCIN” revised
18 Table 4.4 SFR Information (4);
00FEh: “DRR” → “P1DRR” revised
19 Table 4.5 SFR Information (5);
-0119h: “Timer RE Minute Data Register / Compare Register” →
“Timer RE Minute Data Register / Compare Data Register”
-011Ah: “Timer RE Time Data Register” →
“Timer RE Hour Data Register”
-011Bh: “Timer RE Day Data Register” →
“Timer RE Day of Week Data Register” revised
22 to 45 5. Electrical Characteristics added
1.00 Nov 08, 2006 All pages “Preliminary” deleted
2 Table 1.1 revised
3 Table 1.2 revised
4 Figure 1.1 revised
5 Table 1.3 revised
6 Table 1.4 revised
9 Table 1.6 revised
15 Table 4.1;
• 001Ch: “00h” → “00h, 10000000b” revised
• 000Fh: “000XXXXXb” → “00X11111b” revised
• 0029h: “High-Speed On-Chip Oscillator Control Register 4, FRA4,
When shipping” added
• 002Bh: “High-Speed On-Chip Oscillator Control Register 6, FRA6,
When shipping” added
• 0032h: “00h, 01000000b” → “00h, 00100000b” revised
• 0038h: “00001000b, 01001001b” → “0000X000b, 0100X001b” revised
• NOTE3 and 4 revised; NOTE6 added
18 Table 4.4;
• 00E0h, 00E1h, 00E5h, 00E8h, 00E9h: “XXh” → “00h” revised
• 00FDh: “XX00000000b” → “00h” revised
22 Table 5.2 revised
23 Figure 5.1 title revised
26 Figure 5.2 title revised and Table 5.7 NOTE4 added
A-1
Description
Rev. Date
Page Summary
1.00 Nov 08, 2006 27 Table 5.9, Figure 5.3 revised and Table 5.10 deleted
28 Table 5.10, Table 5.11 revised
47 Package Dimensions; “Diagrams showing the latest...website.” added
1.10 Nov 29, 2006 All pages “J, K version” added
1 1 “J and K versions are under development...notice.” added
1.1 revised
2 Table 1.1 revised
3 Table 1.2 revised
4 Figure 1.1 NOTE3 added
5 Table 1.3, Figure 1.2 revised
6 Table 1.4, Figure 1.3 revised
8 Table 1.5 revised
9 Table 1.6 NOTE2 added
15 Table 4.1; “0000h to 003Fh” → “0000h to 002Fh” revised
• NOTE3 added
16 Table 4.2; “0040h to 007Fh” → “0030h to 007Fh” revised
• 0032h, 0036h: “After reset” is revised
• 0038h: NOTE revised
• NOTES 2, 5, 6 revised and NOTE 7, 8 added
48 to 66 5.2 J, K Version added
1.20 Jan 17, 2007 18 Table 4.4 NOTE2 added
1.30 May 25, 2007 2 Table 1.1 revised
3 Table 1.2 revised
5 Table 1.3 revised
7 Table 1.4 revised
15 Figure 3.1 part number revised
A-2
Description
Rev. Date
Page Summary
1.30 May 25, 2007 16 Figure 3.2 part number revised
1.40a Jun 14, 2007 5, 7 Table 1.3 and Table 1.4 revised
2.00 Mar 01, 2008 1, 49 1.1, 5.2 “J and K versions are ...” deleted
5, 7 Table 1.3, Table 1.4 revised
15, 16 Figure 3.1, Figure 3.2; “Expanded area” deleted
17 Table 4.1 “002Ch” added
18 Table 4.2 “0036h”; J, K version “0100X000b” → “0100X001b”
24, 49 Table 5.2, Table 5.35; NOTE2 revised
30 Table 5.10 revised, NOTE4 added
2.10 Sep 26, 2008 − “RENESAS TECHNICAL UP DATE” reflected: TN-16C-A172A/E
26, 51 Table 5.4, Table 5.37 NOTE2, NOTE4 revised
27, 52 Table 5.5, Table 5.38 NOTE2, NOTE5 revised
53 Table 5.39 Parameter: Voltage monitor 1 reset generation time added
NOTE5 added
Table 5.40 revised
Figure 5.22 revised
All trademarks and registered trademarks are the property of their respective owners.
A-3
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes:
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes
warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property
rights or any other rights of Renesas or any third party with respect to the information in this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a
result of errors or omissions in the information included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability
of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular
application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications
or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality
and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or
undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall
have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as
swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.
Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have
any other inquiries.
RENESAS SALES OFFICES http://www.renesas.com

Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
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Tel: <852> 2265-6688, Fax: <852> 2377-3473
Renesas Technology Taiwan Co., Ltd.
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Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399
Renesas Technology Singapore Pte. Ltd.
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Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
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Tel: <603> 7955-9390, Fax: <603> 7955-9510
© 2008. Renesas Technology Corp., All rights reserved. Printed in Japan.

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R8C/26 Group, R8C/27 Group

Rev.2.10 Sep 26, 2008 Page 1 of 69

1.2 Performance Overview

Table 1.1 Functions and Specifications for R8C/26 Group

Rev.2.10 Sep 26, 2008 Page 2 of 69

Table 1.2 Functions and Specifications for R8C/27 Group

Rev.2.10 Sep 26, 2008 Page 3 of 69

1.3 Block Diagram

I/O ports Port P0 Port P1 Port P3 Port P4 Port P5

I2C bus interface or clock synchronous

Watchdog timer R8C CPU core Memory

Figure 1.1 Block Diagram

Rev.2.10 Sep 26, 2008 Page 4 of 69

1.4 Product Information

Rev.2.10 Sep 26, 2008 Page 5 of 69

Part No. R 5 F 21 26 6 S N XXX FP

S: Low-voltage version (other no symbols)

Rev.2.10 Sep 26, 2008 Page 6 of 69

Rev.2.10 Sep 26, 2008 Page 7 of 69

Part No. R 5 F 21 27 6 S N XXX FP

S: Low-voltage version (other no symbols)

Rev.2.10 Sep 26, 2008 Page 8 of 69

1.5 Pin Assignments

Figure 1.4 Pin Assignments (Top View)

Rev.2.10 Sep 26, 2008 Page 9 of 69

1.6 Pin Functions

Table 1.5 Pin Functions

Rev.2.10 Sep 26, 2008 Page 10 of 69

Table 1.6 Pin Name Information by Pin Number

Rev.2.10 Sep 26, 2008 Page 11 of 69

2. Central Processing Unit (CPU)

b31 b15 b8b7 b0

R2 R0H (high-order of R0) R0L (low-order of R0)

INTBH INTBL Interrupt table register

The 4 high order bits of INTB are INTBH and

ISP Interrupt stack pointer

SB Static base register

FLG Flag register

Figure 2.1 CPU Registers

Rev.2.10 Sep 26, 2008 Page 12 of 69

2.1 Data Registers (R0, R1, R2, and R3)

2.2 Address Registers (A0 and A1)

2.3 Frame Base Register (FB)

2.4 Interrupt Table Register (INTB)

2.5 Program Counter (PC)

2.7 Static Base Register (SB)

2.8 Flag Register (FLG)

2.8.1 Carry Flag (C)

2.8.2 Debug Flag (D)

2.8.3 Zero Flag (Z)

2.8.4 Sign Flag (S)

2.8.5 Register Bank Select Flag (B)

2.8.6 Overflow Flag (O)

Rev.2.10 Sep 26, 2008 Page 13 of 69

2.8.7 Interrupt Enable Flag (I)

2.8.8 Stack Pointer Select Flag (U)

2.8.9 Processor Interrupt Priority Level (IPL)

2.8.10 Reserved Bit

Rev.2.10 Sep 26, 2008 Page 14 of 69