ZL30320 DataSheet
ZL30320 DataSheet
ZL30320 DataSheet
ToP
Port M2 Port M1
Network I/F MAC Ethernet Bridge MAC Processor I/F
(GMII/TBI/MII/RMII) (GMII/TBI/MII/RMII)
osci
Master SSI Register
Osc
Timestamp Engine Access I/F
osco
PLL
ETH_CLK0
Input Ports
APLL ETH_CLK1
ref0 &
Ref
DPLL
sync0 Monitors p0_clk0
P0
p0_clk1
Synthesizer
p0_fp0
p0_fp1
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Copyright 2012, Microsemi Corporation. All Rights Reserved.
ZL30320 Data Sheet
Applications
• IEEE 1588 and Synchronous Ethernet timing
• GSM and UMTS air interface synchronization over a packet network
• Circuit Emulation Services over Packets
• IP-PBX and VoIP Gateways
• Video Conferencing
• Broadband Video Distribution
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Microsemi Corporation
ZL30320 Data Sheet
Change Summary
Changes from the September 2011 issue to the October 2012 issue.
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Microsemi Corporation
ZL30320 Data Sheet
Description
Network infrastructures are gradually converging onto a packet-based architecture. With this convergence, there
are a significant number of synchronous applications that require accurate timing to be distributed over the packet
networks. Examples of precision timing sensitive applications that need the transport of synchronization over
packet networks include transport of TDM over packet networks, connections to 2 G and 3 G cellular base stations,
Voice over IP, IP PBXs, video-conferencing and broadband video.
There are two main ways to enable synchronization over a packet network, synchronizing the packet network itself,
as in the Synchronous Ethernet approach, or distributing the timing using the packets as in Microsemi’s Timing over
Packet (ToP) technology. The two techniques can also be combined to provide a very powerful hybrid solution.
Synchronous Ethernet delivers a very accurate frequency reference, but doesn’t address phase and time
synchronization. ToP can be used to supplement the excellent frequency distribution of Synchronous Ethernet with
accurate phase and time information. Alternatively, ToP can be used to extend the reach of the Synchronous
Ethernet reference across an asynchronous network, such as a LAN connected to a synchronous WAN.
Microsemi has combined both methods into a single device. The ZL30320 incorporates an extremely low-jitter
frequency synthesizer, capable of generating all the frequencies required for Synchronous Ethernet operation,
together with Microsemi’s patent-pending Timing over Packet (ToP) technology based on the industry-standard
IEEE1588TM “PTP” (Precision Time Protocol). Not only can it function as a fully-featured Digital PLL, it also
supports the distribution of time, phase and frequency across both layer 2 and layer 3 networks, using both
Synchronous Ethernet and IEEE1588 protocols, either alone or in combination.
The ZL30320 is a member of a family of footprint-compatible devices offering the full range of features required for
timing and synchronization across the packet network. These devices facilitate design of a flexible card that can be
upgraded as required by simply placing another member of the same family.
ZL30310 ZL30310; Combined IEEE1588TM ToP and Synchronous Ethernet, coupled with a GR-1244 Stratum
2/3E/3/4/4E GR-253 SONET, G.812 (types 2 and 3) G.813, and G.8262 quality phase locked loop for
timing card applications, plus a second independent PLL for rate conversion or generation of additional
derived clocks.
ZL30312 Combined IEEE1588TM ToP and Synchronous Ethernet, coupled with a GR-1244 Stratum 3/4/4E and
GR-253 SEONET and G.813 quality phase locked loop for timing card applications, plus a second
independent PLL for rate conversion or generation of additional derived clocks.
ZL30314 Combined IEEE1588TM ToP and Synchronous Ethernet, coupled with a GR1244 Stratum 3/4/4E and
G.813 Option 1 quality phase locked loop for timing card applications, plus a second independent PLL
for rate conversion or generation of additional derived clocks.
ZL30316 Combined IEEE1588TM ToP and Synchronous Ethernet, coupled with two independent, flexible phase
locked loops for line card applications
ZL30320 Combined IEEE1588TM ToP and Synchronous Ethernet for line card applications
ZL30321 Synchronous Ethernet line card device in a ToP compatible footprint, containing two independent DPLLs
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ZL30320 Data Sheet
When operating as a server, the Microsemi device locks onto the incoming clock reference as a conventional PLL,
filtering any jitter that may be present. It also synchronizes to any low-frequency alignment signal, e.g., an 8 kHz
TDM frame pulse, or a 1 Hz alignment input. The device delivers streams of packets, each containing a timestamp
indicating the precise time that the packet was launched into the network, relative to the acquired reference. It also
receives packets from clients, and returns a message indicating the exact time that the client message was
received at the server. Using this information, clients are able to align their own timebase with that of the server.
As a client, the Microsemi device can track two independent servers, and determine which one is providing the best
time reference. If either the primary reference or the network between the server and client fails, the device can
switch to the alternative reference without introducing a phase discontinuity. Alternatively, the client can switch to a
conventional clock reference.
The solution timing recovery algorithm continuously tracks the frequency offset and phase drift between the clocks
located at the server and the client nodes connected via the packet switched network. The algorithm is tolerant of
lost packets, and of packet delay variation caused by packet queuing, route changes and other effects. In the event
of a failure in the packet network, or the advent of severe congestion preventing or seriously delaying the delivery of
timing packets, the device will put the recovered clocks into holdover until the flow of timing packets is restored.
When the device is in holdover mode the drift of the local oscillator directly affects the accuracy of the output clocks.
When using ToP technology, the device is designed to meet ANSI standard T1.101 and ITU-T standards G.823 and
G.824 for synchronization distribution. It maintains a mean frequency accuracy of better than ±10 ppb and time
alignment of better than ±1 μs when operated over a suitable network.
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ZL30320 Data Sheet
Table of Contents
1.0 Physical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.0 External Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 Clock Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1.1 Output Clock Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2 Ethernet Output Clock Loop Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.1 Ethernet Filter Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.3 Local Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.3.1 Use of a Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4 Packet Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.4.1 GMII and MII Signal Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.5 CPU and Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.5.1 Reset Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.6 JTAG and Test Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.7 Power and Ground Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.7.1 Power Up/Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.7.2 Power Supply Decoupling and Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.8 Non-connects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.0 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.1 Time Server Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 Client Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.3 Boundary Clock Mode of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4 Timing Redundancy and Holdover . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1 Ethernet Bridge and MAC Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1.1 Overview of Bridge Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1.2 Handling of Timing Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.1.2.1 Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.1.2.2 Timestamp Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1.2.3 Timing Packet Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.1.3 Handling of Non-Timing Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.1.3.1 Broadcast and ARP filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.1.4 Queuing System and Buffer Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.1.4.1 Packet Dropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.1.4.2 Flow Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1.5 MAC Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1.5.1 GMII/TBI/MII/RMII Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1.5.2 MAC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.5.3 Link Up/Down Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.5.4 Management Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1.5.5 Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.1.5.6 Layout Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2 Timestamp Engine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2.1 Server Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.2.2 Client Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.2.3 Boundary Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.2.4 Combined Synchronous Ethernet and Timing over Packet Operation. . . . . . . . . . . . . . . . . . . . . . . 44
4.3 DPLL Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.3.1 DPLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.3.2 DPLL Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.3.2.1 DPLL Mode Of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.3.3 Loop Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.3.4 Pull-in/hold-in Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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Table of Contents
4.3.5 Phase slope Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.3.6 Holdover. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.3.7 Reference and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.3.8 Reference Monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.3.9 Sync Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.3.10 Reference Monitoring for Custom Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.3.11 Output Clocks and Frame Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
4.3.11.1 Output Clock and Frame Pulse Squelching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.3.11.2 Disabling Output Clocks and Frame Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.3.11.3 Disabling Output Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.4 Synchronous Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.4.1 Transmission Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.4.2 Page Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.4.3 Accessing Multi-byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.5 Timing Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.5.1 Hardware Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.5.2 User Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.5.2.1 User-Provided Software Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.5.3 Microsemi-Provided Software Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.5.3.1 Solution API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.5.3.2 IEEE 1588 Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.5.3.3 Other Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.5.4 Software Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.5.4.1 Use of Multicast vs. Unicast Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
5.0 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.1 Absolute Maximum Ratings* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
5.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.0 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.1 Clock Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.1.1 Input Timing For Sync References* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.1.2 Input To Output Timing For Ref<n> References* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
6.1.3 Output Clock Duty Cycle1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.1.4 Output Clock and Frame Pulse Fall and Rise Times1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.1.5 E1 Output Frame Pulse Timing* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
6.1.6 Measured Output Jitter On Ethernet Clock CMOS Outputs with Active MII Interface (ETH_CLK[0,1])
72
6.1.7 Measured Output Jitter On Ethernet Clock CMOS Outputs with Active GMII Interface (ETH_
CLK[0,1])72
6.2 Packet Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.2.1 Typical Reset Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.2.2 MII Transmit Timing: MAC to PHY Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.2.3 MII Receive Timing: MAC to PHY Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.2.4 MII Transmit Timing: PHY Emulation Mode (MAC to MAC connections) . . . . . . . . . . . . . . . . . . . . 76
6.2.5 MII Receive Timing: PHY Emulation Mode (MAC to MAC connections) . . . . . . . . . . . . . . . . . . . . . 77
6.2.6 RMII Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.2.7 RMII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.2.8 GMII Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.2.9 GMII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.2.10 TBI Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.2.11 Management Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3 Synchronous Serial Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
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Table of Contents
6.4 JTAG Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
7.0 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
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List of Figures
Figure 1 - ZL30320 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - ZL30320 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3 - Ethernet Loop Filter Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 4 - Ethernet Loop Filter Layout Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5 - Clock Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 6 - Typical Power-Up Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 7 - Power Supply Decoupling for the ZL30320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 8 - ZL30320 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 9 - Example ZL30320 Time Server driven from a Conditioned GPS or BITS/SSU reference . . . . . . . . . . 28
Figure 10 - Example ZL30320 Timing Client. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 11 - Ethernet Bridge Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 12 - GMII Connection (MAC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 13 - GMII Connection (PHY Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 14 - TBI Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 15 - MII Connection (MAC Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 16 - MII Connection (PHY Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 17 - RMII Connection (MAC Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 18 - RMII Connection (PHY Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 19 - Relationship of Timestamp Engine to DPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 20 - Operation as a Timing over Packet Server . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 21 - Operation as a Timing over Packet Client . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 22 - Automatic Mode State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 23 - Output Frame Pulse Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 24 - Behaviour of the Guard Soak Timer during CFM or SCM Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 25 - Frequency Acceptance and Rejection Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 26 - Reference Monitoring Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 27 - Sync Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 28 - Defining SCM Limits for Custom Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 29 - Custom CFM Configuration for 25 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 30 - Output Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 31 - Phase Delay Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 32 - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 33 - Serial Peripheral Interface Functional Waveforms - LSB First Mode . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 34 - Serial Peripheral Interface Functional Waveforms - MSB First Mode . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 35 - Page Addressing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 36 - High Level Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 41 - Sync Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 42 - Input To Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 43 - Output Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 44 - Output Clock Fall and Rise Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 45 - E1 Output Frame Pulse Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 46 - Typical Reset Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 47 - MII Transmit Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 48 - MII Receive Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 49 - MII Transmit Timing Diagram - PHY Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 50 - MII Receive Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 51 - RMII Transmit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 52 - RMII Receive Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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Figure 53 - GMII Transmit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 54 - GMII Receive Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 55 - TBI Transmit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 56 - TBI Receive Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 57 - Management Interface Timing for Ethernet Port - Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 58 - Management Interface Timing for Ethernet Port - Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 59 - Serial Peripheral Interface Timing - LSB First Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 60 - Serial Peripheral Interface Timing - MSB First Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 61 - JTAG Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 62 - JTAG Clock and Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
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List of Figures
Table 1 - ZL30320 Ball Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 2 - Gigabit Ethernet Ports Signal Mapping in Different Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 3 - MDIO Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 4 - DPLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 5 - DPLL1 Loop Bandwidth Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 6 - DPLL1 Pull-in Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 7 - DPLL Phase Slope Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 8 - Set of Pre-Defined Auto-Detect Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 9 - Set of Pre-Defined Auto-Detect Sync Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 10 - Frequency Out of Range Limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 11 - Supported Output Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 12 - APLL LVCMOS Output Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 13 - P0 Frame Pulse Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 14 - P0 Frame Pulse Widths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 15 - Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 16 - MII Transmit Timing - 100 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 17 - MII Receive Timing - 100 Mbps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 18 - MII Transmit Timing - 100 Mbps - PHY Emulation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 19 - MII Receive Timing - 100 Mbps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 20 - RMII Transmit Timing - 100 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 21 - RMII Receive Timing - 100 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 22 - GMII Transmit Timing - 1000 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 23 - GMII Receive Timing - 1000 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 24 - TBI Timing - 1000 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 25 - MAC Management Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 26 - JTAG Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
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ZL30320 Data Sheet
Features:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
P0_CLK
B AVDD18 AVDD33 AVDD33 VDD33 NC NC NC NC VDD33 NC NC NC NC VDD33 VSS B
[1]
IC M1_
E V DD33 VDD33 NC AVSS NC NC NC NC NC NC NC NC VDD18 RST_B E
(tie low) TXER
M1_ M1_
J IC IC NC VDD18 NC VSS VSS VSS VSS VSS V SS V SS VDD33 M1_CRS J
RXER REFCLK
M2_TXD M2_TXD
M NC IC NC VDD18 NC IC IC IC IC NC TDI TDO NC OSC_O M
[3] [7]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
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ZL30320 Data Sheet
Table 1 - ZL30320 Ball Table 1 - ZL30320 Ball NC - not connected - leave open circuit.
IC - internally connected - leave open circuit.
Assignments Assignments IC (tie low) - internally connected, must be
tied to VSS.
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If clocks must be fanned out to multiple receivers, then an external clock buffer should generally be used. In some
circumstances, it is acceptable to branch the clock at the source, provided that standard signal integrity practices
are strictly followed to prevent degradations at the receiver.
D2, D3 FILTER_REF[0:1] Analog I/O 2 Analog PLL External Loop Filter References (Analog)
300 Ω 270 nF
D1
ETH_FILTER
D2
FILTER_REF[0]
D3
FILTER_REF[1] 2.0 nF
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ZL30320 Data Sheet
The following guidelines for layout should be applied to minimize noise in the proximity of the loop filter.
• Group the loop filter discrete components tightly and as close to the ZL30320 body as possible, minimizing
trace lengths.
• Keep all unrelated traces and components 100 mil away from the loop filter discrete components and traces
(applies to all PCB layers).
• Cut away all planes in the cross section of PCB beneath the loop filter to prevent coupling with noise from
power or ground planes.
• Keep components on same side as ZL30320 and do not use vias.
Figure 4 shows an example of the loop filter placement and routing:
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ZL30320 Data Sheet
3.3 V
N16 20 MHz
OSC_I
TCXO/OCXO
M16
OSC_O Unconnected
• Provision a source termination resistor at the output of the oscillator and assign to 0 ohms initially. If there is
ringing at the receiver, then the value should be increased.
• Place oscillator within about 50 mm of the ZL30320 device, and keep the clock trace away from other traces.
• Ensure that the oscillator power noise is minimized. Include RLC or ferrite-C lowpass filters as required to
achieve low noise.
• If an OCXO is provisioned, adequate bulk decoupling should be provisioned so that the device’s oven
activity does not cause “bumps” in the supply voltage.
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• Apply signal spacings which will minimize cross talk between xMII clocks and all other signals, including
trace switchbacks with same signal.
• Measures should also be taken to minimize cross talk between data signals of different xMII busses.
• Source termination resistors should be provisioned at all xMII clock drivers to support impedance matching.
If excessive overshoot is a concern, then data signals should also have source terminations.
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ZL30320 Data Sheet
The reset pin can be controlled with on-board system reset circuitry or by using a stand-alone power-up reset circuit
as shown in Figure 6. This circuit provides approximately 60 μs of reset low time. The RST_B input has schmitt
trigger properties to prevent level bouncing.
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ZL30320 Data Sheet
3.3 V
R
10 kΩ
RST_B E15
C
10 nF
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• "power islands” should be created for the device, for the 3.3 V and for the 1.8 V. A power island is a local
copper area, separated from the main power plane by a series passive component. Its purpose is to provide
improved isolation from noise on the board power planes. Ferrite beads provide additional suppression of
digital switching noise generated by other integrated circuits connected to the main power planes. A
recommended bead is LI0805H121R or similar. Note that beads have some DC resistance which increases
the minimum required supply voltage for the device (by about 1% for the above bead).
• Each power island should be provisioned with bulk capacitors of a low-ESR 220 µF Tantalum and 10 µF
Ceramic. For this configuration, broadband (20 Hz to 20 MHz) input power noise should not be greater than
20mVpk-pk on the power supply side of the ferrite element.
• A 0.1 µF decoupling capacitor (ceramic X5R or X7R) must be allocated for each power pin and placed as
close as possible to the via connected to the power pin. The smallest available package size should be
used. Each decoupling capacitor should be connected directly to only one power pin, and should not share
vias to power or ground with other capacitors. Device size should be EIA 0402 or smaller for best high-
frequency response and to facilitate optimal placement.
• Priority should be given to placement of decoupling capacitors in nearest proximity to power pin groups
AVDD33, and AVDD18.
• In addition, AVDD18 pin sub-groups B1, C2 and T14 require specific RC filters as shown in Figure 7. The
location requirements for 0.1 µF decoupling capacitors on these pins takes priority over the location for
source terminators or any other components.
• There may be conflicts for “best” placement between capacitors and source termination resistors. It is
important to use size 0402 or smaller capacitors to minimize the occurrence of such issues.
• The ball C3 (AVDD18) can be connected to the AVDD18 plane, however it is preferred for this ball to be
connected to the VDD18 plane in a star type connection as shown Figure 7.
• The balls B2 and B3 (AVDD33) can be connected to the AVDD33 plane, however it is preferred for these balls
to be connected to the VDD33 plane in a star type connection as shown Figure 7.
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ZL30320 Data Sheet
10 uF 0.1 uF
220uF 10 uF 0.1 uF
10 uF 0.1 uF
ZL303xx
10 uF 0.1 uF
10 uF 0.1 uF
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ZL30320 Data Sheet
2.8 Non-connects
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ZL30320 Data Sheet
• as a timing server
• as a timing client
• as a boundary clock
Figure 8 shows an application diagram of the ZL30320 operating in server, client or boundary clock modes.
Timing Repeater
Client 4
BITS Client Server
SSU
GPS
Network 2
Primary
Time Server
Network 1
Client 2
Client 3
Client 1
The ZL30320 generates the clock to the Ethernet PHY device at either 25, 50, 62.5 or 125 MHz depending on the
requirements.
For ToP, the host microprocessor generates streams of packets in either the industry-standard IEEE1588TM “PTP”
format (Precision Time Protocol), or the RTP format (Real-time Transport Protocol, RFC3550), which is compatible
with Microsemi’s first generation Timing over Packet devices (ZL30301 and ZL30302). As these packets pass
through the ZL30320 device, an accurate timestamp is inserted into the packet denoting the exact time of
transmission of the packet into the network.
These timing packets are either broadcast to all devices in the network, multicast to a number of selected devices
(i.e., those in the addressed multicast group), or unicast to a number of separate client devices. Typical packet
rates are in the range 16 - 64 packets per second. The server may also receive timing messages from clients,
requesting the server to respond with the time of arrival of the message. The ZL30320 device timestamps such
messages on arrival, and forwards the timestamp to the host for it to generate the appropriate response.
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Microsemi Corporation
ZL30320 Data Sheet
Figure 9 shows an example of a Time Server connected to a BITS or SSU synchronization source. The ZL30320
acquires the input reference, and internally generates the high frequency clock needed to drive the timestamp
engine, locked to the input reference. The timestamp may be phase aligned to the framing signal, allowing the
framing signal at the client to be aligned to that of the server. The device also generates the clock for the Ethernet
PHY, and this may be used as a Synchronous Ethernet reference.
Host
Network Processor Processor
Interface Data Interface
Ethernet Ethernet
MAC MAC MAC
PHY Bridge
Processor
Control Interface
PHY clock Master Timestamp SSI
SSI (Master)
Osc Engine
BITS or SSU
(alternative Mux
PRS Clock Clock
reference Input
DPLL Synths PHY clock RS232
source)
Figure 9 - Example ZL30320 Time Server driven from a Conditioned GPS or BITS/SSU reference
The quality of the recovered clock from a ToP server is targeted to meet ANSI standard T1.101 and ITU-T
standards G.823 and G.824 for synchronization distribution over an appropriate network. It maintains a mean
frequency accuracy of better than ±10 ppb and time alignment of better than ±1 μs when operated over a suitable
network.
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Microsemi Corporation
ZL30320 Data Sheet
Host
Network Processor Processor
Interface Data Interface
Ethernet Ethernet
MAC MAC MAC
PHY Bridge
Processor
Control Interface
PHY clock out Master Timestamp SSI
SSI
Osc Engine (Master)
For example, in Figure 8, at the boundary clock node the ZL30320 will work as a client node for the Network 1 and
as a server node for the Network 2. The device simultaneously operates in both server and client modes to achieve
the boundary clock function.
Various statistics on the status or the quality of the recovered clocks are available to base the choice of clock on.It
is possible to switch the clock automatically to the best available server stream, or to switch manually once a failure
has occurred.
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Microsemi Corporation
ZL30320 Data Sheet
100M/1G MAC
exit
timestamp
queue
buffer timing packet identifier
exit
timestamps
timing arrival
packets timestamp
arrival
timestamp
appender Read
playout
time Reference clock
timing and alignment
packets from PLL
Timestamp
sched.
timing packet identifier buffer buffer Engine
insertion
broadcast scheduling engine /
timestamp
filter timestamp insertion
arrival
MII / RMII /
GMII / TBI
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Microsemi Corporation
ZL30320 Data Sheet
Simultaneously with packet transmission, the exit time of the packet is forwarded into a small queue to be read by
the processor over the SSI. This is required to enable follow-up messages in a timing server, and to provide the
transmission time of delay request messages in a timing client.
4.1.2.1 Classification
The classification engine determines whether packets are timing packets or non-timing packets. It checks the
packet header to examine the protocol stack. To allow for variations in the protocol stack, the classifier is a very
simple “brute-force” mask and match comparator across the first 64 bytes of the packet. This is sufficient to allow
for variations such as presence or absence of VLAN tags, use of IPv4 or IPv6, operation over MPLS, operation
directly over Ethernet etc. The classifier can be configured to support one protocol stack at a time.
It is important to note that the comparator is simply a binary process: it only identifies whether a packet is a timing
packet intended for a specific device or not. It does not attempt to identify flows or message types within that
category.
Two classification rules are provided, to allow for differences in the protocol stack in each direction (e.g. the reversal
of source and destination addresses, or the presence of VLAN tags in one direction only. These two rules are
programmed using the API call zl303xx_LanWritePktClassifyRule.
The mask register allows each bit of the header to be individually included or excluded from the comparison. Where
a mask bit is set to 1, the corresponding bit of the match register is excluded. This allows the rule to be constructed
such that any field or bit of the header can be included or excluded from the classification process.
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ZL30320 Data Sheet
The timestamp inserted into the packet can be in either PTP format (64 bits wide), NTP format (64 bits wide), or
RTP format (32 bits wide). If RTP is used, the timestamp represents an unsigned 32-bit count of 10 MHz clock
periods, starting from a random value. It should be noted that the initial software released with the device only
operates with PTP (IEEE1588TM-2007). An RTP version is planned for backwards compatibility with Microsemi’s
earlier Timing over Packet family (ZL30301 and ZL30302). It is not currently planned to produce an NTP version.
The locations of the temporary action field and where the timestamp is to be inserted are determined by the API call
zl303xx_LanConfigTxTsControl. The location of the UDP checksum is determined by the call
zl303xx_LanConfigTxUDPChksum.
If follow-up recording is enabled, the precise time of exit is recorded in a 64-entry FIFO queue, along with an index
number uniquely identifying the packet. This can be read by the CPU for use in a follow-up message, or at a client
for reading the time of transmission of a delay_request message.
This time is inserted or appended to the packet at a pre-determined location. Normally it is not desired to overwrite
any of the fields within the timing packet, therefore this is written into the Ethernet frame beyond the IP datagram.
The software retrieves this information from the Ethernet frame when it processes the packet. The UDP checksum
is not updated in this direction, since the timestamp is normally beyond the datagram and therefore doesn’t
contribute to the checksum. The Ethernet FCS is updated as the packet is transmitted out of port 1.
The location in the packet where the timestamp is to be inserted is determined by the API call
zl303xx_LanConfigRxTsControl.
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ZL30320 Data Sheet
This enables the software to control the rate and time of transmission much more precisely than is possible in
software alone. The feature is useful in certain algorithms where the time of transmission of packets is important.
Packet scheduling is not controlled by the API. It is used by the clock recovery algorithms to improve the quality of
the recovered clocks at the clients.
Non-timing packets may be dropped if the buffer memory overflows. Dropping may be avoided by the effective use
of flow control (see section 4.1.4.2, “Flow Control“). If both ports operate at the same nominal rate, the buffers are
sufficiently large to avoid packet dropping in most circumstances.
The timebase can be set in units of 2n * 100 μs (where n is from 1 to 7), with the maximum number of packets being
set between 0 and 255. Above that rate, all broadcast or ARP packets are dropped by the device.
• queue to port 1
• queue to port 2
• scheduled timing packet queue
These three queues use a shared memory architecture for efficiency and flexibility. This enables the memory to be
allocated flexibly to each queue on demand. The total buffer memory available to the Ethernet bridge is 32 Kbytes.
This is allocated in 128 byte segments, accommodating a maximum of 256 packets.
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Microsemi Corporation
ZL30320 Data Sheet
The queues may back up for a number of reasons. For example, the receiving device on port 2 may send a flow
control frame (also known as a pause frame) to pause the flow of packets from the Microsemi device. Since port 2
can no longer send packets, its queue will start to fill up. When it reaches the threshold value, the device will send a
flow control frame out on port 1, to prevent any further packets from reaching the device before the queue fills up
completely and packets start to be dropped.
When the congestion on port 2 clears and the flow control is released, the queues to port 2 will empty, and the flow
control on port 1 will be released.
When operating as a PHY, the MII transmit clocks (M1_TXCLK or M2_TXCLK) become outputs, and the interface
supplies the timing to the opposing MAC. This clock is used to time both the transmit and receive data. In this mode
the receive clocks (M1_RXCLK and M2_RXCLK) are not used. PHY emulation mode may be configured separately
for each interface.
The clock generation module in the Microsemi device can generate Ethernet clocks at 25, 50, 62.5 or 125 MHz in
order to remove the requirement for a separate oscillator at the PHY device.
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Microsemi Corporation
ZL30320 Data Sheet
GTXCLK GTXCLK
TXCLK TXCLK
MAC TXEN TXEN
TX TXER TXER
TXD[7:0]
TXD[7:0]
CRS
CRS
COL
COL
RXCLK
RXCLK
MAC RXDV
RXDV
RX RXER
RXER
RXD[7:0]
RXD[7:0]
M2_REFCLK
10
01 M1_REFCLK
00 ETH_CLK0
/1 CLK125
grefclk_sel
~ /n
ETH_CLK1 Local XO (25MHz)
125MHz
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Microsemi Corporation
ZL30320 Data Sheet
CRS
CRS
COL
COL
RXCLK
GTXCLK
MAC RXDV
TXEN
RX RXER
TXER
RXD[7:0]
TXD[7:0]
M2_REFCLK
10
M1_REFCLK
01
ETH_CLK0
00 /1 REFCLK
grefclk_sel
~ /n
ETH_CLK1
125MHz
SD From SD on
RBC1 Transceiver
RBC1
RBC0
RBC0
MAC
RX
RXD[9:0]
RXD[9:0]
M2_REFCLK
10
M1_REFCLK
01
00 ETH_CLK0
/1
grefclk_sel
~ /n
ETH_CLK1
125MHz
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Microsemi Corporation
ZL30320 Data Sheet
CRS
CRS
COL
COL
RXCLK
RXCLK
MAC RXDV
RXDV
RX RXER
RXER
RXD[3:0]
RXD[3:0]
M2_REFCLK
10
01
M1_REFCLK
00 ETH_CLK0
/5 Local XO (25MHz)
grefclk_sel
~ /n
ETH_CLK1
125MHz
CRS
CRS
COL
COL
RXCLK
TXCLK
MAC RXDV
TXEN
RX RXER
TXER
RXD[7:0]
TXD[7:0]
M2_REFCLK
10
M1_REFCLK
01
00 ETH_CLK0
/5
grefclk_sel
~ /n
ETH_CLK1
125MHz
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Microsemi Corporation
ZL30320 Data Sheet
TXCLK
MAC TXEN RMII TXEN
TXEN
TX TXER TX
TXD[3:0] TXD[1:0]
TXD[1:0]
CRS
COL
RXCLK
MAC RXDV RMII CRS_DV
CRS_DV
RX RXER RX
RXD[3:0] RXD[1:0]
RXD[1:0]
rmii_clk"n"_sel
1
/2.5 0
M2_REFCLK Equal trace
10 lengthsfrom
01
M1_REFCLK
ETH_CLK0 buffer
00 /2.5 REFCLK (50MHz)
grefclk_sel
~ /n
ETH_CLK1
CLOCK
BUFFER
125MHz
TXCLK
MAC TXEN RMII TXEN
CRS_DV
TX TXER TX
TXD[3:0] TXD[1:0]
RXD[1:0]
CRS
COL
RXCLK
MAC RXDV RMII CRS_DV
TXEN
RX RXER RX
RXD[3:0] RXD[1:0]
TXD[1:0]
rmii_clk"n"_sel
1
/2.5 0
M2_REFCLK Equal trace
10 lengthsfrom
01
M1_REFCLK
buffer
00 ETH_CLK0
/2.5 REFCLK (50MHz)
grefclk_sel
~ /n
ETH_CLK1
CLOCK
BUFFER
125MHz
MAC Module
The Gigabit Ethernet Media Access Control (GE MAC) module provides the necessary buffers and control interface
between the Microsemi device and an external device. The GE MAC implements a GMII/MII interface, which offers
a simple migration from 10/100M to 1 G. For GE fiber optics media, the device has an integrated Physical Code
Sub-layer (PCS) module, which includes an 8B10B encoder and decoder, auto-negotiation, and a Ten Bit Interface
(TBI). For reduced signal layout, the device has an integrated Reduced MII (RMII) module, which does a MII to
RMII interface conversion.
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Microsemi Corporation
ZL30320 Data Sheet
The MAC of the Microsemi device meets the IEEE 802.3 specification. It is able to operate in 100 M in either Half or
Full Duplex mode with a back pressure/flow control mechanism, or in 1000 M in Full duplex mode with flow control
mechanism. It is highly recommended to always operate the MAC in full duplex mode.
The PCS comprises the PCS Transmit, Synchronization, PCS Receive and auto-negotiation processes for
1000BASE-X.
• The PCS Transmit process sends the TBI signals TXD[9:0] to the physical medium and generates the GMII
Collision Detect (COL) signal based on whether a reception is occurring simultaneously with transmission.
Additionally, the Transmit process generates an internal “transmitting” flag and monitors auto-negotiation to
determine whether to transmit data or to reconfigure the link.
• The PCS Synchronization process determines whether or not the receive channel is operational.
• The PCS Receive process receives the TBI signals RXD[9:0] from the physical medium, and generates the
GMII RXD[7:0] signals and the internal “receiving” flag for use by the Transmit processes.
• The PCS auto-negotiation process allows the Microsemi device to exchange configuration information
between two devices that share a link segment and to automatically configure the link for the appropriate
speed of operation for both devices.
The TBI interface is connected to the SERDES as shown in Figure 14.
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Microsemi Corporation
ZL30320 Data Sheet
When auto-negotiation is used and a port is in MAC mode, the addresses used to pll the PHY devices are fixed.
The PHY device attached to port M1 is address 0x08, and the PHY device attached to port M2 is address 0x09. If
user decides to use manual management polling any PHY address can be used.
When one of the two ports is configured in MAC mode, then the management link associated with that port is used
to auto-negotiate with its PHY. But, when both ports are configured in MAC mode, then the management link of port
M1 is used to auto-negotiate with both PHYs.
M1 M2
MDIO Control
Processor Interface Network Interface
MAC PHY M1
MAC MAC M1
PHY MAC M2
PHY PHY N/A
Table 3 - MDIO Control
4.1.5.5 Statistics
The device maintains statistics counters, sufficient to enable the standard Ethernet MIBs such as RFC1757 to be
supported. The statistics collected are:
• Total number of bytes sent • Number of frames received with length of 64 bytes
• Number of unicast frames sent • Number of frames received with length 65 to 127 bytes
• Number of non-unicast frames sent • Number of frames received with length 128 to 255 bytes
• Number of flow-control frames sent • Number of frames received with length 256 to 511 bytes
• Number of frame send failures • Number of frames received with length 512 to 1023 bytes
• Number of bytes received (both good and bad) • Number of frames received with length 1024 to maximum
• Number of frames received (both good and bad) • Number of jabber frames received
• Total number of bytes received • Number of frame fragments received
• Total number of frames received • Number of frames received with alignment errors
• Number of flow-control frames received • Number of frames received with FCS errors
• Number of multicast frames received • Number of short events
• Number of broadcast frames received • Number of collisions
• Number of undersize frames received • Number of dropped frames
An interrupt is generated to the CPU on overflow of the respective counters, allowing the CPU to keep track of the
various statistics for compiling into the MIB format. The state of each of the counters for each port can be read
using the API call zl303xx_LanGetStats. Formatting the raw data into a MIB is a function of the application
software, and is not provided by the Microsemi solution software.
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Microsemi Corporation
ZL30320 Data Sheet
the equivalent length of rise time = rise time (ps) / delay (ps/mm)
For example:
As a signal travels along a trace it creates a magnetic field, which induces noise voltages in adjacent traces causing
crosstalk. If the crosstalk is of sufficiently strong amplitude, false data can be induced in the trace. The voltage that
the external fields cause is proportional to the strength of the field and the length of the trace exposed to the field.
Therefore to minimize the effect of crosstalk some basic guidelines should be followed.
First, increase separation of sensitive signals, a rough rule of thumb is that doubling the separation reduces the
coupling by a factor of four. Alternatively, shield the victim traces from the aggressor by either routing on another
layer separated by a power plane (in a correctly decoupled design the power planes have the same AC potential) or
by placing guard traces between the signals (usually held ground potential).
Particular effort should be made to minimize crosstalk from ZL30320 outputs and ensuring fast rise time to these
inputs.
In Summary:
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ZL30320 Data Sheet
direct control
from CPU
input
frames
Clock Synthesizer
PLL/ToP output
Clock Synthesizer clocks/
frames
1 Hz alignment
Timestamp Engine
inserted into
Insertion Timestamp outgoing timing
PTP, NTP and RTP formats
messages
measures arrival
system clock, System Timestamp time of incoming
80MHz 32 bit free-running counter
timing messages
Arrival time events are always captured in system time, so they are unaffected by any modulation of the PLL
frequency. However, packets leaving the device are timestamped with timestamps related to insertion time.
Insertion timestamps are formatted according to the IEEE 1588 timestamp format.
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ZL30320 Data Sheet
direct control
from CPU
input
frames
Clock Synthesizer
output
PLL/ToP
Clock Synthesizer clocks/
frames
1 Hz alignment
Timestamp Engine
inserted into
Insertion Timestamp outgoing timing
PTP, NTP and RTP formats
messages
measures arrival
system clock, System Timestamp time of incoming
80MHz 32 bit free-running counter
timing messages
The CPU should wait a second and then read back the insertion timestamp, just to make sure the operation
completed successfully (e.g., that the programming of the “whole seconds” portion and zeroing of the “fractional
seconds” portion took place in the same 1 s interval, since there is a danger that the timestamp ends up exactly one
second out). However, once verified, the alignment process is normally a one-off alignment at initialization. The
phase should be checked periodically against the 1 pps, but re-alignment shouldn’t be needed unless the reference
clock loses lock against UTC.
Packets received from the client devices (e.g., PTP delay_request messages) are timestamped as they arrive at
the network interface. This uses “system time”, the 32 bit free-running counter driven from the 80 MHz system clock
(which is in turn locked to the 20 MHz local oscillator). For the construction of PTP delay_response messages that
has to be translated back into insertion time. Since the precise relationship between the two is known, this process
is a simple mathematical operation.
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Microsemi Corporation
ZL30320 Data Sheet
direct control
from CPU
input
frames
Clock Synthesizer
PLL/ToP
Clock Synthesizer
1 Hz alignment
Timestamp Engine
inserted into
Insertion Timestamp outgoing timing
PTP, NTP and RTP formats
messages
measures arrival
system clock, System Timestamp time of incoming
80MHz 32 bit free-running counter
timing messages
If two-way time transfer is used, the round-trip time may be calculated, and the insertion timestamp may be aligned
with the insertion time at the time server. The 1 Hz frame pulse from the P0 synthesizer may then be aligned to the
timestamp transition, ensuring that it is locked to the 1 Hz input at the server. Since insertion time is driven by the
DCO, the timing recovery software is then able to keep it locked back to the server. As before, the alignment
process should therefore be a one-off operation.
However, the packet timing messages (e.g., PTP sync, delay_request and delay_response messages) indicate the
offset between the client and server timestamps. The CPU can adjust the absolute value of the timestamp, such
that the client timestamp is aligned to the server. Provided the physical reference at the client is traceable to the
same physical reference as the server, the timestamps should stay aligned.
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ZL30320 Data Sheet
Feature DPLL
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Microsemi Corporation
ZL30320 Data Sheet
Lock
Another reference is Acquisition
qualified and available
for selection
Phase lock on
No references are
qualified and available the selected
reference is
for selection Holdover achieved
Selected reference
Normal
Normal
fails (Locked)
(Locked)
Free-run
The free-run mode occurs immediately after a reset cycle or when the DPLL has never been synchronized to a
reference input. In this mode, the frequency accuracy of the output clocks is equal to the frequency accuracy of the
external master oscillator.
Lock Acquisition
The input references are continuously monitored for frequency accuracy and phase regularity. If at least one of the
input references is qualified by the reference monitors, then the DPLL will begin lock acquisition on that input. Given
a stable reference input, the device will enter in the Normal (locked) mode.
Normal (locked)
The usual mode of operation for the DPLL is the normal mode where the DPLL phase locks to a selected qualified
reference input and generates output clocks and frame pulses with a frequency accuracy equal to the frequency
accuracy of the reference input. While in the normal mode, the DPLL’s clock and frame pulse outputs comply with
the MTIE and TDEV wander generation specifications as described in Telcordia and ITU-T telecommunication
standards.
Holdover
When the DPLL operating in the normal mode loses its reference input, and no other qualified references are
available, it will enter the holdover mode and continue to generate output clocks based on historical frequency data
collected while the DPLL was synchronized. The transition between normal and holdover modes is controlled by
the DPLL so that its initial frequency offset is better than 1 ppb which meets the requirement of Stratum 3E. The
frequency drift after this transition period is dependant on the frequency drift of the external master oscillator.
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Microsemi Corporation
ZL30320 Data Sheet
• Automatic Normal Mode. In this mode, the device DPLL uses an internal state machine to select the mode of
operation as Free-run, Normal, or Holdover. Automatic reference switching is also enabled so that the highest
priority qualified reference is selected. If that reference fails, an automatic reference switch-over to the next
highest priority and qualified reference is initiated. If there are no suitable references for selection, DPLL1 will
stay in free-run or enter the holdover state.
• Manual Normal Mode. In this mode, the device DPLL stays in Normal mode. Automatic reference switching
is disabled and the selected reference is determined by the dpll1_refsel register (0x20). If the selected
reference fails, the device automatically enters the Holdover mode.
• Manual Holdover Mode. In this mode, the device DPLL stays in Holdover mode which means that it is not
locked to any reference input. Instead, it generates a frequency based on historical frequency data collected
while the DPLL was locked to the last valid reference.
• Manual Freerun Mode. In this mode, the device DPLL stays in Free-run mode. The DPLL generates an output
frequency that is based on the center frequency of its external reference oscillator.
The default mode of operation after reset the device is Automatic Normal Mode.
BW (Hz) Application
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Microsemi Corporation
ZL30320 Data Sheet
885 ns/s GR-1244 Stratum 2, 3E, 3 (objective), GR-253-CORE SMC and Stratum 3 for
SONET
7.5 μs/s G.813 option 1
61 μs/s GR-1244 Stratum 3
Unrestricted (default) No phase slope limiting
Table 7 - DPLL Phase Slope Limiting
4.3.6 Holdover
The device DPLL continuously collect phase data while synchronized to a valid reference. These data samples are
accumulated and averaged to determine a stable holdover frequency in the event that all of the valid references are
lost. To prevent reference input jitter from corrupting the final holdover value, samples are taken on phase data
filtered by the DPLL’s loop bandwidth. DPLL offers an additional stage of filtering that can be enabled if the DPLL’s
loop bandwidth does not provide adequate filtering. This allows the DPLL to operate in a wide bandwidth mode and
still provide an accurate holdover value. This is useful when the DPLL1 is used in a redundant mode. The holdover
filter bandwidth is programmable using the hold_filt_bw field of the dpll1_ctrl_1 register (0x1E).
The holdover performance of the output clocks will depend on two factors. One is the initial offset of the DPLL, and
the other is the frequency drift (or stability) of the external oscillator. The initial offset of the DPLL meets the
requirements for Stratum 3/G.813 opt 1, Stratum 3E/G.812 type 3 the overall holdover performance dependant on
the frequency drift of the external oscillator.OCXO or TCXO for Stratum 2/G.812 type 2 and Stratum 3E/6.812 type.
The input is a single-ended LVCMOS clock with a frequency ranging from 2 kHz to 77.76 MHz. Built-in frequency
detection circuitry automatically determines the frequency of the reference if its frequency is within the set of pre-
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ZL30320 Data Sheet
defined frequencies as shown in Table 8. Once detected, the resulting frequency of the reference can be read from
the ref_frq_detected registers (0x10 - 0x13).
The reference input (ref0) have programmable pre-dividers (N0) which allows it to lock to frequencies higher than
77.76 MHz or to non-standard frequencies. By default the pre-dividers divide by 1, but they can be programmed to
divide by 1.5, 2, 2.5, 3, 4, 5, 6, 7, and 8 using the predivider_control register (0x7E). For example, an input
frequency of 125 MHz can be divided down by 5 using the pre-dividers to create a 25 MHz input reference. The
25 MHz can then be programmed as a custom input frequency. Similarly, a 62.5 MHz input clock can be divided by
2.5 to create 25 MHz. Note: Division by non-integer numbers (e.g. 1.5, 2.5) uses both edges of the reference clock.
As a result, higher jitter levels at the output clocks may occur if the reference clock is not 50% duty cycle.
In addition to the reference input, the DPLL has an optional frame pulse synchronization input sync0 used to align
the output frame pulses. Note that the sync input cannot be used to synchronize the DPLL, it only determines the
alignment of the frame pulse outputs. An example of output frame pulse alignment is shown in Figure 23.
ref0
Without a frame pulse x = 0, 1
signal at the sync sync0 - no frame pulse signal present
input, the output
frame pulses will align
to any arbitrary cycle p0_clkx/p1_clkx
of its associated
output clock. p0_fpx
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Microsemi Corporation
ZL30320 Data Sheet
The sync input accepts a single-ended LVCMOS frame pulse. Since alignment is determined from the rising edge
of the frame pulse, there is no duty cycle restriction on this input, but there is a minimum pulse width requirement of
5 ns. Frequency detection for the sync inputs is automatic for the supported frame pulse frequencies shown in
Table 9.
1 Hz
166.67 Hz
(48x 125 μs frames)
400 Hz
1 kHz
2 kHz
8 kHz
64 kHz
Table 9 - Set of Pre-Defined Auto-Detect Sync Frequencies
The sync input can be enabled or disabled using the sync_enable register (08_0x68). By default the sync input is
enabled so that DPLL generates frame aligned frame pulse outputs when a frame pulse is available at the sync
input. It is also possible to invert the sync input.
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As shown in Figure 24, a GST failure (gst_fail) is triggered when the accumulated failures have reached the upper
threshold during the disqualification observation window. When there are no CFM or SCM failures, the accumulator
decrements until it reaches its lower threshold during the qualification window.
ref
upper threshold
lower threshold
td tq
td - disqualification time
gst_fail tq - qualification time = n * td
Figure 24 - Behaviour of the Guard Soak Timer during CFM or SCM Failures
Precise Frequency Monitor (PFM)
The PFM is used to keep track of the frequency of the reference clock. It measures its frequency over a 10 second
period and indicates a failure when the measured frequency exceeds the out-of-range (OOR) limits configured in
the oor_ctrl[0:3] registers (0x16 to 0x19). The OOR should be set according to the application as shown in Table 10.
When determining the frequency accuracy of the reference input, the PFM uses the external oscillator’s output
frequency (focsi) as its point of reference. As a result, the actual acceptance and rejection frequencies can be offset
with respect to the external oscillator’s output frequency. This is accounted for in the acceptance and rejection
requirements as described in Telcordia GR-1244 section 3.4.1. An example of the acceptance and rejection ranges
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Microsemi Corporation
ZL30320 Data Sheet
for Stratum 3/3E application (acceptance in the range of +/- 9.2 ppm, rejection at +/- 12 ppm) given a +/- 4.6 ppm
free-run frequency accuracy of a Stratum 3/3E reference oscillator is shown in Figure 25.
-16.6 -13.8 -12 -9.2 -7.4 -4.6 0 ppm +4.6 +7.4 +9.2 +12 +13.8 +16.6
It is possible to mask an individual reference monitor from triggering a reference failure by setting the
ref_mon_fail_mask_3:0 registers (0x0C - 0x0F). These are represented by mask_scmn, mask_cfmn, mask_gstn,
and mask_pfmn in Figure 26. In addition, the CFM and SCM reference monitor indicators can be masked from
indicating failures to the GST reference monitor using the gst_mask1:0 registers (0x1A - 0x1B). These are
represented as mask_cfm_gstn and mask_scm_gstn.
Setting mask bit to logic 0 will disable the individual monitor ability from triggering a reference fail. While setting it to
logic 1 will allow that monitor to trigger a reference fail.
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mask_scmn
refn mask_cfmn
cfm_failn
CFM
Logical ref_fail_isrn
mask_cfm_gstn GST gst_failn OR
scm_failn
SCM mask_gstn mask_isrn
mask_scm_gstn
PFM pfm_failn
mask_pfmn
T
sync0 1
N* =T
ref0
ref0
1 N
Each of the custom configurations also have definable SCM and CFM limits. The SCM limits are programmable
using the custA_scm_low_lim, custA_scm_high_lim, custB_scm_low_lim, custB_scm_high_lim registers (0x69,
0x6A, 0x73, 0x74). The SCM low and high limits determine the acceptance window for the clock period as shown in
Figure 28. Any clock edge that does not fall into the acceptance window will trigger an SCM failure. High and low
limits are programmed as multiples of a 300 MHz cycle (3.33 ns).
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1
Nominal Period =
Custom Frequency
scm_low_lim
scm_high_lim
Acceptance Window
For example, if the Custom A frequency was defined as 25 MHz (using registers 0x67, 0x68), its nominal period is
40 ns. To fail the input reference when its period falls below 20 ns (-50% of the nominal period), the custA_scm_low
register is programmed to 0x06 (6 x 1/300 MHz = 20 ns). To fail the input reference if its period exceeds 60 ns
(+50% of the nominal period), the custA_scm_high register is programmed with 0x12 (18 x 1/300 MHz = 60 ns).
For low speed input references less than 1.8 MHz, the SCM counter does not provide enough range to reliably
perform its function. Therefore for custom inputs of less than 1.8 MHz the device should set the scm_low_lim and
scm_high_lim to 0 and the CFM should be used as the single cycle monitor.
The CFM quickly determines large changes in frequency by verifying that there are N amount of input reference
clock cycles within a programmable sample window. The value of N is programmable in the custA_cfm_cycle and
the custB_cfm_cycle registers (0x6F, 0x79). The size of the sample window is defined in terms of high and low
limits and are programmed as multiples of 80 MHz cycles. These are defined using the custA_cfm_low_0,
custA_cfm_low_1, custA_cfm_high_0, custA_cfm_high_1, custB_cfm_low_0, custB_cfm_low_1,
custB_cfm_high_0, custB_cfm_high_1 registers (0x6B-0x6E, 0x75-0x78). A divide-by-4 circuit can be enabled to
increase the resolution of the sample window. This is recommended when the input reference frequency exceeds
19.44 MHz. The divide-by-4 is enabled using the custA_div and custB_div registers (0x70, 0x7A). Equations for
calculating the high and low limits are shown in Figure 29.
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sample window
N 0 N 0
cfm_low_limit
cfm_high_limit
D D
cfm_low_limit = x N x 80 MHz cfm_high_limit = x N x 80 MHz
cust_freq + 3% cust_freq - 3%
where N and D are dependant on the setting of the custom frequency. Recommended values are shown
in the following table:
Example: Custom configuration A is set for 25 MHz (custA_mult13_8 = 0x0C, custA_mult7_0 = 0x35)
(0C35hex = 3125dec, 3125 x 8 kHz = 25 MHz)
The values for D and N are determined using the table above with respect to a 25 MHz input reference.
D=4 (custA_div = 0x01)
N = 128 (custA_cfm_cycle = 0x7F)
The CFM low and high values are calculated using the equations above:
4
cfm_low_limit = x 128 x 80 MHz = 1591dec = 0637hex (custA_cfm_low15_8 = 0x06)
25.75 MHz (custA_cfm_low7_0 = 0x37)
4
cfm_high_limit = x 128 x 80 MHz = 1689dec = 0699hex (custA_cfm_high15_8 = 0x06)
24.25 MHz
(custA_cfm_high7_0 = 0x99)
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As shown in Figure 30, the output clocks and frame pulses are always synchronous with the DPLL,
eth_clk0
DPLL APLL
eth_clk1
p0_clk0
P0 p0_clk1
Synthesizer p0_fp0
p0_fp1
apll_clkn_freq eth_clkn
bit settings Output Frequency
eth_clkn_run = 1
0001 125 MHz
0010 62.5 MHz
0011 Reserved
0100 Reserved
0101 50 MHz
0110 25 MHz
0111 12.5 MHz
1xxx Reserved
Table 12 - APLL LVCMOS Output Clock Frequencies
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The frequency of the p0_clk0 output is programmable from 2 kHz up to 100 MHz where,
fp0_clk0 = N x 8 kHz
The value of N is a 16-bit word which is programmable using the p0_freq_0 and p0_freq_1 registers (0x38, 0x39).
For an output frequency of 2 kHz, let N = 0.
The p0_clk1 output frequency is programmed as a multiple of the p0_clk0 output frequency where
fp0_clk0
fp0_clk1 =
2M
The value of M is defined in the p0_clk1_div register (0x3B). The minimum and maximum frequency limits of 2 kHz
to 100 MHz are also applicable to p0_clk1.
The frequency of the frame pulses generated from the p0 synthesizer (p0_fp0, p0_fp1) is programmable using the
p0_fp0_freq register and the p0_fp1_freq registers (0x3E, 0x43). Valid frequencies are listed in Table 13.
p0_fpn Frequency
166.6667 Hz (48x 125 μs frames)
400 Hz
1 kHz
2 kHz
4 kHz
8 kHz
32 kHz
64 kHz
1 Hz (Synchrounous to p0_clkn, with either 1UI or
4msec pulse width)
1 PPS (Asynchronous with 200nsec pulse width)
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The pulse width of the frame pulse is programmable using the p0_fpn_type register (0x3F, 0x44). Valid pulse widths
are shown in Table 14.
p0_fpn Comment
Pulse Width
One period of a 4.096 MHz clock These are pre-defined pulse widths that are usable when
p0_clkn is set to a frequency that is a multiple of the E1 rate
One period of a 8.192 MHz clock
(2.048 MHz). When p0_clkn is not an E1 multiple, the
One period of a 16.384 MHz clock p0_fpn_type must be set to’111’
One period of a 32.768 MHz clock
One period of a 65.536 MHz clock
One period of p0_clkn The frame pulse width is equal to one period of the p0_clkn.
This setting must be used when the p0_clkn is not an E1
multiple.
Table 14 - P0 Frame Pulse Widths
The style (frame pulse or 50% duty cycle clock), alignment (rising or falling edge of its associated clock), and its
polarity (positive or negative) is programmable using the p0_fpn_type register (0x3F, 0x44).
The Zarlink device allows programmable static delay compensation for controlling input-to-output and output-to-
output delays of its clocks and frame pulse.
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DPLL1 APLL
Fine Delay APLL
Coarse Delay 0x53 eth_clk0
DPLL1 Fine Delay
0x63 0x55 Coarse Delay 0x54 eth_clk1
In addition to the fine delay introduced in the DPLL path, the APLL and P0 synthesizers have the ability to add their
own fine delay adjustments by programming registers 0x55 and 0x3D. These registers are also programmed as 8-
bit two’s complement values representing delays defined in steps of 119.2 ps with a range of -15.26 ns to +15.14
ns.
The output clocks of the APLL and P0 synthesizers can be independently offset by 90, 180, and 270 degrees using
the coarse delay registers (0x53, 0x54, 0x3A, 0x3C).
The output frame pulses can be independently offset with respect to each other using the frame pulse delay
registers (0x40 - 0x42, 0x45 - 0x47). Frame pulse generated from the p0 synthesizer (p0_fp0, p0_fp1) associated
with p0 clock (p0_clk0, p0_clk1) that are multiples of 2.048 MHz (E1) can be delayed in steps of 1/262.144 MHz
(or approx. 3.81 ns). The delay value is programmed as a 16-bit value defined in registers 0x40/0x41. The
maximum amount of delay is 125 μs (= 32767 * 1/262.14 MHz). In addition, the frame pulse can be delayed in steps
of 125 μs (up to 2^6 * 125 μs = 8 ms) using the 0x42 register for p0_fp.
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ZL30320 Data Sheet
The interface allows for multiple of Microsemi devices to be controlled by a single CPU, by having an individual
CS_B for each of Microsemi devices and sharing the data and clock signals.
The serial peripheral interface supports half-duplex processor mode which means that during a write cycle to the
Microsemi device, output data from the SO pin must be ignored. Similarly, the input data on the SI pin is ignored by
the device during a read cycle from the device.
Functional waveforms for the LSB first mode are shown in Figure 33, while Figure 34 describe the MSB first mode.
CS_B
SCK
Read operation:
SI Rd A0 A1 A2 A3 A4 A5 A6 X X X X X X X X
SO D0 D1 D2 D3 D4 D5 D6 D7
Write operation:
SI Wr A0 A1 A2 A3 A4 A5 A6 D0 D1 D2 D3 D4 D5 D6 D7
SO X X X X X X X X
Command/Address Data
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ZL30320 Data Sheet
CS_B
SCK
Read operation:
SI Rd A6 A5 A4 A3 A2 A1 A0 X X X X X X X X
SO D7 D6 D5 D4 D3 D2 D1 D0
Write operation:
SI Wr A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
SO X X X X X X X X
Command/Address Data
For registers at addresses 0x65 to 0x7F, there are 16 pages of registers (although only 13 are actually used). To
access these registers, the page pointer register at address 0x64 must be written to first, selecting the correct page.
The access can then continue as normal. Therefore for registers at these addresses, 32 bits of bandwidth are
consumed on the SPI (8 bits command/address, 8 bits page pointer, followed by 8 bits command/address, 8 bits
data).
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address 0x00
address 0x01
address 0x63
address 0x64 page pointer register
address 0x65
Page B
Page F
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The solution API has been developed around the VxWorks Real Time Operating System, however it has been
designed to minimize the dependency on the RTOS, and make porting to a new RTOS as easy as possible.
Therefore all operating system calls have been mapped via macros and isolated to one header file. This file
contains the macros and detailed comments about their usage.
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• Clock Recovery: This uses the information in the timing packets to recover a clock at a particular frequency.
Part of this module is provided as object code only.
• Device Control. Provides a software interface for controlling the device.
• PLL/DCO Control. For a client device this controls the recovered frequency output.
• Generic SSI driver. This block provides a generic interface for an SSI device.
1. It reduces the overall volume of timing packets (e.g., PTP sync messages) in the network, and in particular the
concentration of packets leaving the server
2. It increases the number of clients a server can address, since it doesn’t have to generate a unique timing stream
for each client (note it still has to service PTP delay_request messages from each individual client).
However, there are also some disadvantages. Multicast packets are not forwarded as efficiently in the network.
Whenever a multicast packet reaches a switch or router, it has to be replicated many times in order to be sent out of
each exit port of the device. This replication process adds both delay and delay variation to the packet. Therefore
the delay variation accumulated by the time a timing packet stream reaches a client is much greater when using
multicast than with unicast. Further, some routers are configured to block or limit the rate of multicast packets,
making those streams more unreliable.
The main disadvantage of unicast packets is that the server is much less efficient. This is because the server has to
create a separate sync message stream to each individual client. Where the sync message rate is high, and the
number of clients is also high, this consumes a large amount of CPU time. For this reason, the CPU at a server
device should normally be dedicated to the task of running the server, and shouldn’t be expected to cope with other
tasks.
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5.0 DC Characteristics
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Input Levels
Output Levels
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6.0 AC Characteristics
REF[0]
tSYNC_LD tSYNC_LG
SYNC[0]
tSYNC_W
REF[0]
tD
P0_CLK[0,1]
ETH_CLK[0,1]
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1 LVCMOS Output Duty Cycle2 tSYM 45 55 % 2 kHz < fclk ≤ 125 MHz
2 40 60 % 50 MHz on eth_clk0/1
1. Duty cycle is measured over the specified operating voltage and temperature ranges at specified spot frequencies.
2. Measured on spot frequencies of 1.544 MHz, 2.048 MHz, 3.088 MHz, 4.096 MHz, 6.312 MHz, 8.192 MHz, 8.448 MHz, 16.384 MHz,
32.768 MHz, 34.368 MHz, 44.736 MHz, 65.536 MHz, 125 MHz.
tperiod
P0_CLK[0,1], ETH_CLK[0,1]
tlow tlow
tSYM =
tperiod
6.1.4 Output Clock and Frame Pulse Fall and Rise Times1
90% 90%
10% 10%
t rise tfall
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* All measurements taken over the specified operating voltage and temperature range
1
clkfreq
P0_CLK[0,1]
1
fpfreq
tdelay tdelay
P0_FP[0,1]
fppulse_width
tdelay_inv tdelay_inv
P0_FP[0,1]
(Inverted)
fppulse_width
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6.1.6 Measured Output Jitter On Ethernet Clock CMOS Outputs with Active MII Interface
(ETH_CLK[0,1])
6.1.7 Measured Output Jitter On Ethernet Clock CMOS Outputs with Active GMII Interface
(ETH_CLK[0,1])
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RS T_ B
t RAS
PH Y _ R S T _ B
t PRAS
E N b it (s ee not e)
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100 Mbps
Parameter Symbol Units Notes
Min. Typ. Max.
Mn_TXCLK period tTCC - 40 - ns
Mn_TXCLK high time tTCH 14 - 26 ns
Mn_TXCLK low time tTCL 14 - 26 ns
Mn_TXCLK rise time tTCR - - 5 ns
Mn_TXCLK fall time tTCF - - 5 ns
Mn_TXCLK rise to tDV 2 - 25 ns Load = 25 pF
Mn_TXD[3:0] active delay
Mn_TXCLK rise to Mn_TXEN tEV 2 - 25 ns Load = 25 pF
active delay
Mn_TXCLK rise to Mn_TXER tER 2 - 25 ns Load = 25 pF
active delay
Table 16 - MII Transmit Timing - 100 Mbps
tEV tEV
Mn_TXEN
tDV
Mn_TXD[3:0]
tER tER
Mn_TXER
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100 Mbps
Parameter Symbol Units Notes
Min. Typ. Max.
tDVS tDVH
Mn_RXDV
tDH
tDS
Mn_RXD[3:0]
tERH
tERS
Mn_RXER
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6.2.4 MII Transmit Timing: PHY Emulation Mode (MAC to MAC connections)
For MAC to MAC connections, the ZL30320 can emulate a PHY, with Mn_TXCLK as an output. Data signals (Mn_
TXD, Mn_TXEN and Mn_TXER) are driven from the falling edge of Mn_TXCLK to provide sufficient hold time at the
receiving device.
100 Mbps
Parameter Symbol Units Notes
Min. Typ. Max.
tER tER
Mn_TXER
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6.2.5 MII Receive Timing: PHY Emulation Mode (MAC to MAC connections)
For MAC to MAC connections, the ZL30320 can emulate a PHY. In this mode Mn_RXCLK is not connected, and
the data is timed relative to Mn_TXCLK which is an output.
100 Mbps
Parameter Symbol Units Notes
Min. Typ. Max.
tDVS tDVH
Mn_RXDV
tDH
tDS
Mn_RXD[3:0]
tERH
tERS
Mn_RXER
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ZL30320 Data Sheet
100 Mbps
Parameter Symbol Units Notes
Min. Typ. Max.
tEV tEV
Mn_TXEN
tDV
Mn_TXD[1:0]
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100 Mbps
Parameter Symbol Units Notes
Min. Typ. Max.
Mn_REFCLK
tDVS tDVH
Mn_RXDV
tDH
tDS
Mn_RXD[1:0]
tERH
tERS
Mn_RXER
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1000 Mbps
Parameter Symbol Units Notes
Min. Typ. Max.
tEV tEV
Mn_TXEN
tDV
Mn_TXD[7:0]
tER tER
Mn_TXER
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ZL30320 Data Sheet
1000 Mbps
Parameter Symbol Units Notes
Min. Typ. Max.
tDVS tDVH
Mn_RXDV
tDH
tDS
Mn_RXD[7:0]
tERH
tERS
Mn_RXER
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1000 Mbps
Parameter Symbol Units Notes
Min. Typ. Max.
Mn_GTXCLK period tGCC 7.5 8 - ns
Mn_GTXCLK duty cycle 40 - 60 %
Mn_GTXCLK rise time tGCR - - 1 ns
Mn_GTXCLK fall time tGCF - - 1 ns
Mn_TXD[9:0] Output Delay tDV 1 - 5.5 ns
(Mn_GTXCLK rising edge)
Mn_RBC0/Mn_RBC1 period tRC - 16 - ns
Mn_RBC0/Mn_RBC1 duty 40 - 60 %
cycle
Mn_RBC0/Mn_RBC1 rise time tRR - - 2 ns
Mn_RBC0/Mn_RBC1 fall time tRF - - 2 ns
Mn_RXD[9:0] setup time tDS 2 - - ns
(Mn_RBC0 rising edge)
Mn_RXD[9:0] hold time tDH 1 - - ns
(Mn_RBC0 rising edge)
Mn_REFCLK period tFC - 8 - ns
Mn_REFCLK duty cycle 40 - 60 %
Table 24 - TBI Timing - 1000 Mbps
tGCC
Mn_GTXCLK
tDV
Mn_TXD[9:0] /I/ /S/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /T/ /R/ /I/
tRC
Mn_RBC1
tA-B tA-B
tRC
Mn_RBC0
tDH tDH
tDS tDS
Mn_RXD[9:0] /I/ /S/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /T/ /R/ /I/
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tMHI tMLO
Mn_MDC
tMS tMH
Mn_MDIO
tMP
Mn_MDC
tMD
Mn_MDIO
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SI
tSDH t SCH
t SDS
SCK
tSCS tSCL tSCC tSCH
CS_B
tSD
t OHZ
SO
SI
tSDH tSCH
tSDS
SCK
t SCL tSCC
tSCS tSD tSCH
CS_B
tOHZ
SO
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ZL30320 Data Sheet
tJL
tJH tJCP
TCK
tTH
tTS
TMS
tTS tTH
TDI Don't Care DC
tTDV tTDZ
TDO HiZ HiZ
tJL tJH
TCK
tRAS tRS
TRST
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Data Sheet
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ZL30320
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Package Dimensions
This publication is issued to provide information only and (unless agreed by Microsemi in writing) may not be used, applied or
reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or
services concerned. The products, their specifications, services and other information appearing in this publication are subject to
change by Microsemi without notice. No warranty or guarantee express or implied is made regarding the capability, performance or
suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not
constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to
fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used
is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These
products are not suitable for use in any medical and other products whose failure to perform may result in significant injury or death to
the user. All products and materials are sold and services provided subject to Microsemi’s conditions of sale which are available on
request.